JPH03288474A - Active matrix type liquid crystal display - Google Patents

Active matrix type liquid crystal display

Info

Publication number
JPH03288474A
JPH03288474A JP2089975A JP8997590A JPH03288474A JP H03288474 A JPH03288474 A JP H03288474A JP 2089975 A JP2089975 A JP 2089975A JP 8997590 A JP8997590 A JP 8997590A JP H03288474 A JPH03288474 A JP H03288474A
Authority
JP
Japan
Prior art keywords
transistor
drain
well
liquid crystal
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2089975A
Other languages
Japanese (ja)
Inventor
Takehisa Kato
剛久 加藤
Koji Senda
耕司 千田
Fumiaki Emoto
文昭 江本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2089975A priority Critical patent/JPH03288474A/en
Publication of JPH03288474A publication Critical patent/JPH03288474A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To offer an active matrix type liquid crystal display excellent in maintainability of image information without carriers, generated by the light entering the channel of a transistor, flowing into a drain, by providing an opposite conductivity of semiconductor layer on one conductivity of semiconductor substrate, and providing a transistor for driving a picture element on the semiconductor layer. CONSTITUTION:A p-well 2, which is formed by implanting boronic ions, is provided on an n-type silicon substrate 1, and in that p-well 2 is formed an active matrix type liquid crystal display wherein an n-channel transistor is used. In case that the light enters the p-well 2 and generates positive holes and electrons, the positive holes do not flow to the drain 3b due to the potential barrier existing between the p-well 2 and the drain 3b, and is accumulated in the p-well 2. Moreover, since the potential of the n-type silicon substrate 1 is higher than the drain 3b, most of the electrons generated flow to the n-type silicon substrate 1. According to this constitution, the currents generated by light can be reduced, and the maintainability of image information when the transistor is not supplied with currents can be improved.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、半導体基板上に形成されたアクティブマトリ
クス型液晶表示装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix liquid crystal display device formed on a semiconductor substrate.

従来の技術 近年、アクティブマトリクス型液晶表示装置の多画素化
が進められている。アクティブマトリクス方式では、一
画素につき一餡のトランジスタを配して、画素駆動を行
っている。
2. Description of the Related Art In recent years, the number of pixels in active matrix liquid crystal display devices has been increasing. In the active matrix method, one transistor is arranged per pixel to drive the pixel.

以下、図面を参照しながら、従来のアクティブマトリク
ス型液晶表示装置の主要部である半導体基板上に形成さ
れた画素駆動用トランジスタについて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A pixel driving transistor formed on a semiconductor substrate, which is a main part of a conventional active matrix liquid crystal display device, will be described below with reference to the drawings.

第3図は従来の画素駆動用トランジスタの断面図である
FIG. 3 is a cross-sectional view of a conventional pixel driving transistor.

31はp型シリコン基板、3a、3bはn型不純物層で
それぞれソース3a、  ドレイン3bを構成している
。4はゲート酸化膜、5はゲート線すなわちゲート電極
であり、nチャネルMO3型トランジスタを構成してい
る。6は眉間絶縁膜、7はデータ線、8は画素電極、9
は素子間分離のためのシリコン酸化膜(SiO2)層、
10はチャネルストッパーのp+領領域ある。
31 is a p-type silicon substrate, and 3a and 3b are n-type impurity layers forming a source 3a and a drain 3b, respectively. 4 is a gate oxide film, and 5 is a gate line, that is, a gate electrode, which constitutes an n-channel MO3 type transistor. 6 is an insulating film between the eyebrows, 7 is a data line, 8 is a pixel electrode, 9
is a silicon oxide film (SiO2) layer for isolation between elements,
10 is the p+ region of the channel stopper.

以上のように構成された画素駆動用トランジスタについ
て、以下その動作について説明する。
The operation of the pixel driving transistor configured as described above will be described below.

データn7を通して送られてきた映像信号電圧をゲート
線5にアドレス信号を与えることによって画素電極8へ
伝達する。映像信号電圧を画素電極8へ伝達し終ると、
ソース3a・ドレイン3b間が遮断されるので、映像信
号電圧は画素に印加された状態で次の映像信号電圧がく
るまで維持される。
The video signal voltage sent through data n7 is transmitted to the pixel electrode 8 by applying an address signal to the gate line 5. After transmitting the video signal voltage to the pixel electrode 8,
Since the source 3a and drain 3b are cut off, the video signal voltage remains applied to the pixel until the next video signal voltage arrives.

発明が解決しようとする課題 しかしながら、上記の従来の構成では、画素への書き込
み禁止期間にトランジスタが非導通時に、p型シリコン
基板のチャネル部へ光が入射した場合、光が生成するキ
ャリアがドレインおよびソースに流入することによって
電流が流れる。その結果、画素電極の電位が変動し、ト
ランジスタが非導通時にもかかわらず、画素情報が失わ
れるという課題を有していた。
Problems to be Solved by the Invention However, in the conventional configuration described above, when light enters the channel portion of the p-type silicon substrate while the transistor is non-conducting during the write-inhibited period to the pixel, the carriers generated by the light are transferred to the drain. A current flows by flowing into the source. As a result, the potential of the pixel electrode fluctuates, causing a problem in that pixel information is lost even when the transistor is non-conductive.

本発明は上記従来の課題を解決するもので、光生成電流
を低下することのできるアクティブマトリクス型液晶表
示装置を提供することを目的とする。
The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide an active matrix liquid crystal display device that can reduce photogenerated current.

課題を解決するための手段 上記目的を達成するために、本発明のアクティブマトリ
クス型液晶表示装置は、一導電型半導体基板上に反対導
電型の半導体層を設け、その上に画素駆動用トランジス
タを形成した構成としている。なお、使用時には上記半
導体層をグランド電位に接地し、上記半導体基板に電圧
を印加する。
Means for Solving the Problems In order to achieve the above object, an active matrix liquid crystal display device of the present invention includes a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and a pixel driving transistor on the semiconductor layer. The structure is as follows. Note that during use, the semiconductor layer is grounded to a ground potential, and a voltage is applied to the semiconductor substrate.

作用 この構成によって、トランジスタのチャネルに光が入射
することによって生成されるキャリアは、チャネル領域
と半導体基板間の電界によって外部へ流出させられ、ま
たは電位障壁が存在するためにドレインに流入すること
がない。
Effect: With this configuration, carriers generated when light enters the channel of the transistor can be flowed out by the electric field between the channel region and the semiconductor substrate, or can flow into the drain due to the presence of a potential barrier. do not have.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例における画素駆動用トランジ
スタの断面図である。n型シリコン基板1上に、ボロン
イオンを注入して形成したpウェル2を設け、そのpウ
ェル2内にnチャネルトランジスタを用いたアクティブ
マトリクス型液晶表示装置を形成している。製造工程と
しては、例えば、ゲート酸化膜4および分離部となる5
i02層9をマスクとして、リンイオン打ち込みによっ
てn型不純物層を形成してソース3aおよびドレイン3
bを得る。ゲート線5と、データ線7および画素電極8
は、眉間絶縁膜6を介して形成される。また10はチャ
ネルストッパーとなるp+領領域ある。
FIG. 1 is a cross-sectional view of a pixel driving transistor in one embodiment of the present invention. A p-well 2 formed by implanting boron ions is provided on an n-type silicon substrate 1, and an active matrix liquid crystal display device using n-channel transistors is formed within the p-well 2. In the manufacturing process, for example, the gate oxide film 4 and the isolation portion 5 are
Using the i02 layer 9 as a mask, an n-type impurity layer is formed by phosphorus ion implantation to form the source 3a and drain 3.
get b. Gate line 5, data line 7 and pixel electrode 8
is formed via the glabella insulating film 6. Further, 10 is a p+ region which serves as a channel stopper.

以上のように構成されたnチャネルトランジスタについ
て、pウェル2をグランド電位に接地し、n型シリコン
基板1がドレイン3aより高電位となるように正電圧を
印加して動作させる。第2図はトランジスタのドレイン
3bからn型基板1方向へのポテンシャルエネルギー図
である。光がpウェル2へ入射して、正孔および電子を
生成した場合、pウェル2からドレイン3bには電位障
壁が存在するために、正孔はドレイン3bへ流入するこ
となくpウェル2中に蓄えられる。またドレイン3bよ
りn型シリコン基板1の電位の方が高いため、生成され
た電子の大部分はn型シリコン基板1側に流出する。
The n-channel transistor configured as described above is operated by grounding the p-well 2 to the ground potential and applying a positive voltage so that the n-type silicon substrate 1 has a higher potential than the drain 3a. FIG. 2 is a potential energy diagram from the drain 3b of the transistor toward the n-type substrate 1. When light enters the p-well 2 and generates holes and electrons, there is a potential barrier from the p-well 2 to the drain 3b, so the holes do not flow into the drain 3b and flow into the p-well 2. It can be stored. Furthermore, since the potential of the n-type silicon substrate 1 is higher than that of the drain 3b, most of the generated electrons flow to the n-type silicon substrate 1 side.

以上のように本実施例によれば、光生成電流を低下する
ことができ、トランジスタが非導通時における画素情報
の保持特性を改善することができる。
As described above, according to this embodiment, the photo-generated current can be reduced, and the pixel information retention characteristics when the transistor is non-conductive can be improved.

なお、上記の実施例で説明したアクティブマトリクス型
液晶表示装置の画素駆動用トランジスタをpチャネルト
ランジスタとしても良い。pチャネルトランジスタの場
合、p型シリコン基板上に設けたnウェル上にpチャネ
ルトランジスタを形成した構成となり、nウェルをグラ
ンド電位に接地し、p型シリコン基板に負電圧を印加し
て使用する。
Note that the pixel driving transistor of the active matrix liquid crystal display device described in the above embodiment may be a p-channel transistor. In the case of a p-channel transistor, the p-channel transistor is formed on an n-well provided on a p-type silicon substrate, and is used by grounding the n-well to a ground potential and applying a negative voltage to the p-type silicon substrate.

発明の効果 以上のように本発明は、一導電型半導体基板上に反対導
電型の半導体層を設け、その半導体層上に画素駆動用の
トランジスタを設けることによって、トランジスタのチ
ャネルに入射した光が生成するキャリヤがドレインに流
入せず、画素情報の保持特性に優れたアクティブマトリ
クス型液晶表示装置を実現できるものである。
Effects of the Invention As described above, the present invention provides a semiconductor layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and a pixel driving transistor is provided on the semiconductor layer, so that light incident on the channel of the transistor is It is possible to realize an active matrix liquid crystal display device in which generated carriers do not flow into the drain and have excellent pixel information retention characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における画素駆動用トランジ
スタの断面図、第2図は同トランジスタのポテンシャル
エネルギーの特性図、第3図は従来の画素駆動用トラン
ジスタの断面図である。 1・・・・・・n型シリコン基板(半導体基板)、2・
・・・・・pウェル(半導体層〉、3b・・・・・・ド
レイン、5・・・・・・ゲート線、7・・・・・・デー
タ線、8・・・・・・画素電極。
FIG. 1 is a sectional view of a pixel driving transistor according to an embodiment of the present invention, FIG. 2 is a characteristic diagram of potential energy of the same transistor, and FIG. 3 is a sectional view of a conventional pixel driving transistor. 1... n-type silicon substrate (semiconductor substrate), 2.
...P well (semiconductor layer), 3b...Drain, 5...Gate line, 7...Data line, 8...Pixel electrode .

Claims (1)

【特許請求の範囲】[Claims]  一次元または二次元マトリクス状に配列されたトラン
ジスタおよびそのドレインにつながる画素電極からなる
画素と、前記トランジスタの導通または非導通を制御す
るゲート線と、前記画素に映像信号電圧を与えるデータ
線とからなるアクティブマトリクス型液晶表示装置にお
いて、一導電型半導体基板上に反対導電型半導体層を設
け、前記反対導電型半導体層上に前記トランジスタを形
成したアクティブマトリクス型液晶表示装置。
A pixel consisting of transistors arranged in a one-dimensional or two-dimensional matrix and a pixel electrode connected to the drain thereof, a gate line that controls conduction or non-conduction of the transistor, and a data line that applies a video signal voltage to the pixel. An active matrix liquid crystal display device comprising: a semiconductor layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type; and the transistor formed on the semiconductor layer of the opposite conductivity type.
JP2089975A 1990-04-04 1990-04-04 Active matrix type liquid crystal display Pending JPH03288474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2089975A JPH03288474A (en) 1990-04-04 1990-04-04 Active matrix type liquid crystal display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2089975A JPH03288474A (en) 1990-04-04 1990-04-04 Active matrix type liquid crystal display

Publications (1)

Publication Number Publication Date
JPH03288474A true JPH03288474A (en) 1991-12-18

Family

ID=13985679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2089975A Pending JPH03288474A (en) 1990-04-04 1990-04-04 Active matrix type liquid crystal display

Country Status (1)

Country Link
JP (1) JPH03288474A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0869014A (en) * 1994-06-20 1996-03-12 Canon Inc Display
US5801400A (en) * 1995-01-10 1998-09-01 Victor Company Of Japan, Ltd. Active matrix device
US5978056A (en) * 1995-10-15 1999-11-02 Victor Company Of Japan, Ltd Reflection-type display apparatus having antireflection films

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723282A (en) * 1980-07-18 1982-02-06 Toshiba Corp Solid state image sensor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723282A (en) * 1980-07-18 1982-02-06 Toshiba Corp Solid state image sensor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0869014A (en) * 1994-06-20 1996-03-12 Canon Inc Display
US5801400A (en) * 1995-01-10 1998-09-01 Victor Company Of Japan, Ltd. Active matrix device
US5978056A (en) * 1995-10-15 1999-11-02 Victor Company Of Japan, Ltd Reflection-type display apparatus having antireflection films

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