JPH03290950A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the deterioration of element isolation characteristics by a method wherein a same conductivity type conductive layer is formed on the main surface of a semiconductor layer. CONSTITUTION:An n-type field plate electrode 9 is composed of an n-type conductive layer such as a phosphorus-doped polycrystalline silicon layer. A p-type field plate electrode 10 is composed of a p-type conductive layer such as a boron-doped polycrystalline silicon layer. As a difference in work function between the field plate electrode and the surface of the substrate directly under the filed plate electrode is small in this structure, the surface of the substrate is hardly inversed. Therefore, it is not necessary to adjust an impurity concentration for enhancement in the substrate directly under the field plate electrode and field-shield isolation having a large element isolation capability can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and in particular, in a semiconductor device equipped with field effect transistors, a so-called field plate electrode is used for element isolation between each field effect transistor. The invention relates to semiconductor devices.

[Prior Art] Conventionally, as a method for separating semiconductor elements, for example, LOGOS, which is disclosed in Japanese Patent Application Laid-open No. 190869/1983, has been used.
(Local 0ridation of 5il
icon) method is commonly used. However, in the LOGOS method, the oxide film digs into the impurity region, which is called a bird's beak, which is unique to this method. This serves to reduce the channel width of the field effect transistor and accelerate the narrow channel effect of increasing the gate voltage threshold. Therefore, as long as element isolation using the LOGOS method is used, it has been difficult to miniaturize field effect transistors.

On the other hand, as an element isolation method that can cope with miniaturization of field effect transistors or can withstand radiation damage, semiconductor devices using field shield isolation have been proposed, for example, in Japanese Patent Laid-Open Nos. 55-80332 and 60-47437. It is disclosed in the publication No.

FIG. 2 is a sectional view showing a conventional CMO8 type semiconductor device in which such field shield isolation is applied to both an n-channel type MOS transistor section and a p-channel type MO8 transistor section. Referring to FIG. 2, on the p-type silicon substrate 1 are an n-type well layer 2 and an n-type well layer 3.
is formed. There is an element isolation part E in the n-type well layer 2.
A p-channel type MOS) transistor section A1. A2 is formed. In the n-type well layer 3, n-channel type MOS (MOS) transistor parts B1 and B2 separated by an element isolation part E are formed.

The p-channel type MO3) transistor section Al, A2 has a gate electrode 7 and two p0 impurity regions 4 as source or drain regions spaced apart by the gate electrode 7. Gate electrode 7 is formed on n-type well layer 2 with gate insulating film 6 interposed therebetween. Further, the n-channel type MOS) transistor portions B1 and B2 include a gate electrode 7 and an n+ impurity region 5 spaced apart by the gate electrode 7. Gate electrode 7 is formed on n-type well layer 3 with gate insulating film 6 interposed therebetween. p-channel type MOS transistor section Al, A2
An element isolation section E is configured to electrically isolate between the two. This element isolation portion E is constituted by a field plate electrode 20 formed on the n-type well layer 2 with an insulating film 8 interposed therebetween. In addition, n-channel type MOS
) An element isolation section E having a similar structure is configured to electrically isolate between the transistor sections Bl and B2.

This element isolation section E separates the voltage applied to the field plate electrode 20 from the field plate electrode 20.
By holding the surfaces of the n-type well layer 2 and n-type well layer 3 immediately below at a potential that does not invert, the p-channel type MO8
) transistor portions Al, A2, n-channel type MOS) transistor portions Bl, B2 are electrically isolated from each other.

[Problems to be Solved by the Invention] According to the conventional field shield separation, each field plate electrode is composed of a conductive film made of the same material. For example, in the element isolation part E of the n-channel MOS transistor parts Bl and B2 shown in FIG.
Consider the case where the conductive layer is composed of a type conductive layer. In this case, n
There is a large work function difference between the type fee kFj rate electrode 20 and the surface of the n-type well layer 3 directly below the field plate electrode. If this n-type field plate electrode is M
When considered as the gate of an OS transistor, its threshold voltage becomes low. Therefore, even if the n-type field plate electrode 20 is held at the same potential as the surface of the n-type well layer 3 immediately below it or the same potential as the source of each n-type MOS transistor, a lot of leakage occurs due to subthreshold current. Therefore, there was a problem in that the separation characteristics of the field shield deteriorated. In order to solve this problem, it has conventionally been necessary to sufficiently implant enhancement impurities into the substrate surface directly under the field plate electrode. For example, in the above example, it was necessary to implant p-type impurities into the n-type well layer 3 directly under the n-type field plate electrode 20.

Therefore, this invention was made to solve the above problems, and it maintains the field plate electrode at the same potential as the substrate surface directly under the field plate electrode or the same potential as the source of the field effect transistor to be separated. An object of the present invention is to provide a semiconductor device that can ensure necessary isolation characteristics without implanting enhancement impurities.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate, a semiconductor layer of a first conductivity type, a plurality of field effect transistors of a second conductivity type, and a conductivity of a first conductivity type. and a layer. A first conductivity type semiconductor layer is formed on a semiconductor substrate. The field effect transistors of the second conductivity type are formed at intervals on the main surface of the semiconductor layer of the first conductivity type. The conductive layer of the first conductivity type is formed on the main surface of the semiconductor layer of the first conductivity type with an insulating film interposed therebetween in order to electrically isolate the field effect transistors of the second conductivity type. .

[Function] In the present invention, a conductive layer of the first conductivity type is formed on the main surface of the semiconductor layer of the first conductivity type.

Therefore, the difference in work function between the first conductive type conductive layer and the surface of the first conductive type semiconductor layer immediately below it is small. Therefore, even if the potential of the conductive layer of the first conductivity type is held at the same potential as the surface of the semiconductor layer immediately below it or the same potential as the source of each field effect transistor to be separated, the surface of the semiconductor layer is difficult to invert. , element isolation characteristics do not deteriorate.

[Embodiment] FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. A CMOS semiconductor device is shown in which the present invention is applied to both an n-channel MOS transistor section and a p-channel MOS transistor section. Referring to FIG. 1, on a p-type silicon substrate 1, an n-type well layer 2 and a p-type well layer 3 are formed. The n-type well layer 2 includes an element isolation section C and p-channel type MO transistor sections Al and A2 electrically isolated by the element isolation section C. The p-type well layer 3 has an element isolation part and an n-channel MO8 which is electrically isolated by the element isolation part.
h transistor parts Bl and B2 are configured. p channel type MO3) transistor part Al, A2 is gate electrode 7
and a pair of p' impurity regions 4 as source or drain regions spaced apart thereby. The gate electrode 7 has a gate insulating film 6 on the n-type well layer 2.
It is formed by interposing. In addition, n-channel type MO
The S transistor sections B1 and B2 are composed of a gate electrode 7 and a pair of n'''' impurity regions 5 as source or drain regions separated by the gate electrode 7.

An element isolation section C that electrically isolates the p-channel type MOS transistor sections Al and A2 has an n-type field plate electrode 9 formed on the n-type well layer 2 with an insulating film 8 interposed therebetween. Further, the element isolation iD that electrically isolates the n-channel MOS transistor parts Bl and B2 has an n-type field plate electrode 10 formed on the p-type well layer 3 with an insulating film 8 interposed therebetween. . n
The type field plate electrode 9 is formed by an n-type conductive layer, such as phosphorus-doped polysilicon.

The n-type field plate electrode 10 is formed of a p-type ring conductive layer such as polysilicon doped with boron.

In FIG. 1, in order for the n-type field plate electrode 9 to exhibit an element isolation function, it must be at the same potential as the n-type well layer 2 or the p-channel MOS transistor portions Al, A2.
The potential of the n-type field plate electrode 9 is held at the same potential as the source region. On the other hand, the n-type field plate electrode 10 exhibits an element isolation function by maintaining its potential at the same potential as the source regions of the n-channel MOS transistor sections BT and B2 or at the same potential as the p-type well layer 3. do.

In the above embodiment, by arranging an n-type field plate electrode directly above the n-type well layer 2 or arranging a p-type field plate electrode directly above the p-type well layer, the area immediately below the field plate electrode is Turn the surface of the substrate over.

For this purpose, the field plate electrode is constructed by using polysilicon as the material of the field plate electrode and doping it with n-type or p-type impurities, respectively. A conductive material such as a metal other than polysilicon may be used as the material of the field plate electrode to make it difficult to turn over the substrate directly under the field plate electrode.

In addition, although the above embodiment describes an example in which the element isolation structure of the present invention is applied to a CMOS type semiconductor device, the field shield isolation of the present invention is applied to the isolation of field effect transistors having at least one conductivity type. You may.

[Effects of the Invention] As described above, according to the present invention, a material having a small work function difference with the substrate surface directly under the field plate electrode is used as the material for the field plate electrode, so that the surface of the substrate is difficult to invert. Therefore, it is possible to obtain field shield isolation having a large element isolation capability without the need to adjust the impurity concentration for enhancement in the substrate immediately below the field plate electrode.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a CMO8 type semiconductor device to which an embodiment of the element isolation structure according to the present invention is applied. FIG. 2 is a cross-sectional view showing a CMO8 type semiconductor device to which conventional field shield isolation is applied. In the figure, 1 is a p-type silicon substrate, 2 is an n-type well layer, 3 is a p-type well layer, 8 is an insulating film, 9 is an n-type field plate electrode, 10 is a p-type field plate electrode, A
1. A2 is a p-channel type MOS transistor section, Bl,
B2 is an n-channel type MO8) transistor part, C is an element isolation part on the n-type well, and D is an element isolation part on the p-type well.

Claims (1)

[Claims] (1) a semiconductor substrate; a first conductivity type semiconductor layer formed on the semiconductor substrate and having a main surface; and a plurality of semiconductor layers formed at intervals on the main surface of the first conductivity type semiconductor layer; An insulating film is formed on the main surface of the first conductivity type semiconductor layer to electrically isolate the second conductivity type field effect transistor from the second conductivity type field effect transistor. and a conductive layer of a first conductivity type.