JPH0424877B2 - - Google Patents
Info
- Publication number
- JPH0424877B2 JPH0424877B2 JP57022363A JP2236382A JPH0424877B2 JP H0424877 B2 JPH0424877 B2 JP H0424877B2 JP 57022363 A JP57022363 A JP 57022363A JP 2236382 A JP2236382 A JP 2236382A JP H0424877 B2 JPH0424877 B2 JP H0424877B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- disposed
- impurity concentration
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 10
- 239000002784 hot electron Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明はMIS電界効果トランジスタ（以下、単
にMOSトランジスタと記す）に関するもので、
特に、短いチヤネル長を有するMOSトランジス
タのパンチスルー耐圧を高める構造に関するもの
である。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to MIS field effect transistors (hereinafter simply referred to as MOS transistors).
In particular, the present invention relates to a structure that increases the punch-through breakdown voltage of a MOS transistor having a short channel length.
(b) 技術の背景
大規模集積回路、特に大容量メモリには、チヤ
ネル長が1μｍ或いはそれ以下のMOSトランジス
タが用いられる。このような短チヤネルMOSト
ランジスタに於いては、従来の数μｍのチヤネル
長のMOSトランジスタには無かつた種々の不都
合が生じる。(b) Background of the Technology MOS transistors with a channel length of 1 μm or less are used in large-scale integrated circuits, especially large-capacity memories. Such short channel MOS transistors have various disadvantages that do not exist in conventional MOS transistors with a channel length of several μm.
それらの問題のうち大きなものは、微細パター
ンの実現に関するものを別にすると、シヨートチ
ヤネル効果の発生、ソース／ドレイン耐圧の低
下、ホツトエレクトロン効果の発生である。 The major problems among these problems, apart from those related to the realization of fine patterns, are the occurrence of a short channel effect, a decrease in source/drain breakdown voltage, and the occurrence of a hot electron effect.
一方、本発明に利用される技術として、SOI技
術が存在する。該技術の代表例は、二酸化珪素等
の絶縁物層上に非晶質シリコン層或いは多結晶シ
リコン層を被着し、それを単結晶化するものであ
つて、このようにして得た単結晶シリコン層に素
子が形成され、集積回路が形成される。この場合
の基板構成が一般的に、Semiconductor on
Insulatorと表現されることから、SOIと呼ばれる
のである。 On the other hand, SOI technology exists as a technology utilized in the present invention. A typical example of this technology is to deposit an amorphous silicon layer or a polycrystalline silicon layer on an insulating layer such as silicon dioxide, and convert it into a single crystal. Devices are formed in the silicon layer to form an integrated circuit. In this case, the board configuration is generally made by Semiconductor on
It is called an SOI because it is expressed as an insulator.
(c) 従来技術の問題点
本発明は、先に前記の諸問題を解決するMOS
トランジスタを発明し、特許出願を行つた。該発
明の詳細は特開昭55−130171号公報に記されてい
るので、此処ではその要点だけを紹介する。(c) Problems with the prior art The present invention first solves the above-mentioned problems using a MOS
Invented the transistor and filed a patent application. The details of this invention are described in Japanese Patent Application Laid-Open No. 130171/1982, so only the main points thereof will be introduced here.
該先願発明は第１図に示す構造を有する。該
MOSトランジスタに於ては、まず、基板１の不
純物濃度は、ソース（Ｓ）或いはドレイン(D)であ
るｎ＋領域２，３との接合耐圧を十分なものと
し、且つ空乏層の無用の伸びを抑制し得る濃度に
設定されている。ｐ＋領域４の存在によつて、ド
レイン空乏層がソース領域に伸びてパンチスルー
が生じるのが阻止され、更に、ｐ−領域５，５′
の存在により電界が緩和されてホツトエレクトロ
ンの発生が抑えられると共に、チヤネル両端に生
ずるエツジ効果が抑制されて、Vthに及ぼすチヤ
ネル長の影響（シヨートチヤネル効果）を無くし
ている。無効的チヤネル長を定める領域６の不純
物濃度は所定のVthを得る値に設定されている。
前記ｐ−領域領域５，５′及び前記ｐ領域６上に
絶縁膜７を介してゲート電極８が設けられてい
る。尚、９はフイールド絶縁膜を示している。 The prior invention has the structure shown in FIG. Applicable
In a MOS transistor, first, the impurity concentration of the substrate 1 is set to have a sufficient junction breakdown voltage with the n+ regions 2 and 3, which are the source (S) or drain (D), and to prevent unnecessary elongation of the depletion layer. The concentration is set at a level that can be suppressed. The presence of the p+ region 4 prevents the drain depletion layer from extending into the source region and causing punch-through, and furthermore, the presence of the p- regions 5, 5'
Due to the presence of , the electric field is relaxed and the generation of hot electrons is suppressed, and the edge effect occurring at both ends of the channel is suppressed, thereby eliminating the influence of channel length (short channel effect) on V th . The impurity concentration in the region 6 that defines the effective channel length is set to a value that provides a predetermined V th .
A gate electrode 8 is provided on the p-region regions 5, 5' and the p-region 6 with an insulating film 7 interposed therebetween. Note that 9 indicates a field insulating film.
かかる構造のMOSトランジスタに於ては、前
記の問題点はほぼ解決されているのであるが、
MOSトランジスタが更に小型化した場合には、
空乏層が前記ｐ＋領域４の下を通つて拡がり、パ
ンチスルーが発生してしまう。即ち、第２図の矢
印に示す径路によるブレークダウンが起るのであ
るが、小型MOSトランジスタに於ては、実現し
得るｐ＋領域４の深さには限界があるので、前記
構造ではこの問題は解決されない。 In MOS transistors with such a structure, the above-mentioned problems are almost solved; however,
If MOS transistors become even smaller,
The depletion layer passes under the p+ region 4 and expands, resulting in punch-through. That is, breakdown occurs along the path shown by the arrow in FIG. 2, but since there is a limit to the depth of the p+ region 4 that can be realized in small MOS transistors, this problem cannot be solved with the above structure. Not resolved.
(d) 発明の目的
本発明の目的は、かかる径路によるブレークダ
ウンの発生することのない短チヤネルMOSトラ
ンジスタを提供することである。(d) Object of the Invention An object of the invention is to provide a short channel MOS transistor in which breakdown due to such a path does not occur.
(e) 発明の構成
この目的を達成する為、本発明のMOSトラン
ジスタは、絶縁基板上に形成された半導体層、前
記半導体層に、互いに離隔して配設された第一導
電型を有する第１の領域と第２の領域、前記第１
の領域と第２の領域との間に配設された第二の導
電型を有する第３の領域、前記第１の領域と第３
の領域との間に配設された第二導電型で低不純物
濃度を有する第４の領域、前記第２の領域と第３
の領域との間に配設された第二導電型で低不純物
濃度を有する第５の領域、前記第３の領域下に、
当該第３の領域と前記絶縁基板とに接して配置さ
れた第二導電型で高不純物濃度を有する第６の領
域、及び前記第３の領域上に絶縁膜を介して配設
されたゲート電極とを備えた構造を有する。(e) Structure of the Invention In order to achieve this object, the MOS transistor of the present invention includes a semiconductor layer formed on an insulating substrate, a semiconductor layer having a first conductivity type and arranged at a distance from each other. a first area and a second area, the first area
a third region having a second conductivity type disposed between the region and the second region;
a fourth region having a second conductivity type and a low impurity concentration disposed between the second region and the third region;
a fifth region having a second conductivity type and a low impurity concentration disposed between the region and the third region;
a sixth region of a second conductivity type and having a high impurity concentration, disposed in contact with the third region and the insulating substrate; and a gate electrode disposed on the third region via an insulating film. It has a structure equipped with.
(f) 発明の実施例
本発明のMOSトランジスタは前記SOI構造の
基板に構成される。該SOI構造の基板を得ること
は公知技術である。本発明の実施に適したSOI基
板の一例は、シリコン層の厚みが0.3〜1μｍ、不
純物濃度１×1015／cm3のｐ型のものである。(f) Embodiments of the Invention A MOS transistor of the present invention is constructed on the substrate having the SOI structure. Obtaining a substrate with the SOI structure is a known technique. An example of an SOI substrate suitable for carrying out the present invention is a p-type substrate with a silicon layer having a thickness of 0.3 to 1 μm and an impurity concentration of 1×10 15 /cm 3 .
第３図に本発明のｎチヤネルMOSトランジス
タの構造が示される。同図ａは平面図であり、ｂ
はそのＸ−X′断面図である。 FIG. 3 shows the structure of an n-channel MOS transistor of the present invention. Figure a is a plan view, and b
is a sectional view taken along line X-X'.
本発明のｎチヤネルMOSトランジスタに於て
も、前記先願発明のMOSトランジスタと同様、
ｐ＋領域１４が設けられており、ドレイン空乏層
がソース領域に伸びてパンチスルーが生じるのを
阻止している。更に、ｐ−領域１５，１５′がチ
ヤネル領域１６の両側に設けられて、シヨートチ
ヤネル効果とホツトエレクトロン効果の発生を防
止している。ｐ＋領域１４の形成はイオン注入に
よつて実施される。 In the n-channel MOS transistor of the present invention, as well as the MOS transistor of the prior invention,
A p+ region 14 is provided to prevent the drain depletion layer from extending into the source region and punch-through. Furthermore, p-regions 15, 15' are provided on both sides of channel region 16 to prevent short channel effects and hot electron effects from occurring. Formation of p+ region 14 is performed by ion implantation.
チヤネル領域１６の不純物濃度は所定のVthを
得るように設定されており、該領域の不純物濃度
調整はイオン注入によつて行われる。 The impurity concentration of the channel region 16 is set to obtain a predetermined V th , and the impurity concentration of this region is adjusted by ion implantation.
かかる構造を採ることによつて本発明のMOS
トランジスタは、前記先願発明のMOSトランジ
スタと同様、チヤネル長が小であるにもかかわら
ず、シヨートチヤネル効果の発生、ソース／ドレ
イン耐圧の低下、ホツトエレクトロン効果の発生
といつた問題を解決しているのであるが、更に、
前記先願発明のMOSトランジスタでは未解決で
あつた、ｐ＋領域の下を通る径路によるブレーク
ダウンの問題も解決されている。 By adopting such a structure, the MOS of the present invention
Similar to the MOS transistor of the prior invention, the transistor has a small channel length, but solves problems such as short channel effect, reduction in source/drain breakdown voltage, and hot electron effect. However, furthermore,
The problem of breakdown due to a path passing under the p+ region, which was unsolved in the MOS transistor of the prior invention, has also been solved.
即ち、本発明のMOSトランジスタはSOI基板
に形成され、ｐ＋領域１４の下は二酸化珪素の如
き絶縁体であることから、ｐ＋領域１４の下を通
る径路を存在せず、かかる径路のブレークダウン
は生じないのである。 That is, since the MOS transistor of the present invention is formed on an SOI substrate and an insulator such as silicon dioxide is formed under the p+ region 14, there is no path passing under the p+ region 14, and breakdown of such a path is prevented. It does not occur.
本発明のMOSトランジスタを構成する諸領域
はいずれもイオン注入によつて形成される。第３
図の１１は絶縁体、１２，１３はソース或いはド
レイン領域であるｎ＋領域、１７はゲート絶縁
膜、１８はゲート電極（ｎ＋型多結晶シリコン）、
１９はフイールド絶縁膜である。尚、第３図には
図示されていないが、ソース、ドレイン電極はｎ
＋領域１２，１３上に配設され、接続される。 The various regions constituting the MOS transistor of the present invention are all formed by ion implantation. Third
In the figure, 11 is an insulator, 12 and 13 are n+ regions that are source or drain regions, 17 is a gate insulating film, 18 is a gate electrode (n+ type polycrystalline silicon),
19 is a field insulating film. Although not shown in FIG. 3, the source and drain electrodes are n
+ regions 12 and 13 and are connected to each other.
(g) 発明の効果
以上説明した如く、本発明のMOSトランジス
タに於ては、トランジスタの小型化にともなつて
生じるシヨートチヤネル効果の発生、ソース／ド
レイン耐圧の低下、ホツトエレクトロン効果の発
生といつた問題を解決しているだけでなく、ｐ＋
領域１４の下を通る径路によるブレークダウンも
生じることがないので、MOSトランジスタをよ
り小型化し、集積回路を高集積化することが可能
となる。(g) Effects of the Invention As explained above, the MOS transistor of the present invention has problems such as short channel effect, decrease in source/drain breakdown voltage, and hot electron effect that occur as the transistor becomes smaller. Not only are we solving problems, but p+
Since breakdown due to the path passing under the region 14 does not occur, it becomes possible to further downsize the MOS transistor and increase the degree of integration of the integrated circuit.
第１図及び第２図は先行技術とその問題点を示
す図、第３図は本発明を示す図であつて、図に於
て、１はｐ型シリコン基板、２，１２，３，１３
はソース或いはドレイン領域、４，１４はｐ＋領
域、５，５，１５，１５′はｐ−領域、６，１６
はチヤネル領域、７，１７はゲート絶縁膜、８，
１８はゲート電極、９，１９はフイールド絶縁
膜、１１は絶縁体基板である。
1 and 2 are diagrams showing the prior art and its problems, and FIG. 3 is a diagram showing the present invention, in which 1 is a p-type silicon substrate, 2, 12, 3, 13
is a source or drain region, 4, 14 are p+ regions, 5, 5, 15, 15' are p- regions, 6, 16
is a channel region, 7, 17 is a gate insulating film, 8,
18 is a gate electrode, 9 and 19 are field insulating films, and 11 is an insulating substrate.
Claims (1)
体層に、互いに離隔して配設された第一導電型を
有する第１の領域と第２の領域、前記第１の領域
と第２の領域との間に配設された第二の導電型を
有する第３の領域、前記第１の領域と第３の領域
との間に配設された第二導電型で低不純物濃度を
有する第４の領域、前記第２の領域と第３の領域
との間に配設された第二導電型で低不純物濃度を
有する第５の領域、前記第３の領域下に、当該第
３の領域と前記絶縁基板とに接して配置された第
二導電型で高不純物濃度を有する第６の領域、及
び前記第３の領域上に絶縁膜を介して配設された
ゲート電極とを備えてなることを特徴とするMIS
電界効果トランジスタ。1. A semiconductor layer formed on an insulating substrate, a first region and a second region having a first conductivity type that are spaced apart from each other in the semiconductor layer, and the first region and the second region. a third region having a second conductivity type disposed between the first region and the third region; and a fourth region having a second conductivity type and having a low impurity concentration disposed between the first region and the third region. a fifth region having a second conductivity type and a low impurity concentration disposed between the second region and the third region; a fifth region below the third region; A sixth region of a second conductivity type and having a high impurity concentration is disposed in contact with the insulating substrate, and a gate electrode is disposed on the third region with an insulating film interposed therebetween. MIS featuring
Field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2236382A JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2236382A JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58139471A JPS58139471A (en) | 1983-08-18 |
| JPH0424877B2 true JPH0424877B2 (en) | 1992-04-28 |
Family
ID=12080538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2236382A Granted JPS58139471A (en) | 1982-02-15 | 1982-02-15 | Mis field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58139471A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2782781B2 (en) * | 1989-05-20 | 1998-08-06 | 富士通株式会社 | Method for manufacturing semiconductor device |
| US5238857A (en) * | 1989-05-20 | 1993-08-24 | Fujitsu Limited | Method of fabricating a metal-oxide-semiconductor device having a semiconductor on insulator (SOI) structure |
| JP2007214495A (en) * | 2006-02-13 | 2007-08-23 | Oki Electric Ind Co Ltd | Semiconductor device and method for fabrication thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103778A (en) * | 1975-03-10 | 1976-09-13 | Nippon Telegraph & Telephone | Handotaisochito sonoseizohoho |
| JPS55130171A (en) * | 1979-03-29 | 1980-10-08 | Fujitsu Ltd | Mos field effect transistor |
-
1982
- 1982-02-15 JP JP2236382A patent/JPS58139471A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51103778A (en) * | 1975-03-10 | 1976-09-13 | Nippon Telegraph & Telephone | Handotaisochito sonoseizohoho |
| JPS55130171A (en) * | 1979-03-29 | 1980-10-08 | Fujitsu Ltd | Mos field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58139471A (en) | 1983-08-18 |
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