JP3143102B2 - MIS type transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an MIS (metal-insulator-semiconductor).
More specifically, the present invention relates to a thin film transistor formed using a polycrystalline silicon film, and more particularly to a transistor capable of forming an active matrix circuit such as a liquid crystal display.

[Summary of the Invention] The present invention is an MIS transistor formed on an insulating substrate, wherein the MIS transistor has a source region and a drain region formed by introducing impurities into a polycrystalline thin film; A channel region formed between the source region and the drain region, and a sheet formed at least between the drain region and the channel region and having an impurity concentration of 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ . 20k resistance
By having a low-concentration impurity region in which the band gap does not decrease and does not degenerate in the range of Ω / □ or less, the leak current is reduced, and a circuit configuration for a liquid crystal display or the like is made possible.

[Prior Art] Conventionally, as this type of MIS transistor, as shown in FIG. 4, a polycrystalline silicon thin film 2 is formed on an insulating substrate 1, and both ends of the polycrystalline silicon thin film 2 Predicting that the resistance will be high because the thin film 2 is extremely thin, a predetermined n-type impurity is doped at a high concentration of about 4 × 10 ²⁰ cm ⁻³ to form the source and drain regions 2a and 2b having low resistance. I have. During operation of the transistor, a portion between the source region 2a and the drain region 2b in the polycrystalline silicon thin film 2 is a channel region 2c where a channel is formed. Also, on the polycrystalline silicon thin film 2, Si
A gate insulating layer 3 made of O ₂ is formed, and an impurity-doped polycrystalline silicon (DOPO) is formed on the gate insulating layer 3.
A gate electrode 4 made of S) is formed. further,
On the polycrystalline silicon thin film 2 and the gate electrode 4, Si
An insulating layer 5 made of O ₂ is formed. Openings 5a and 5b are formed in the insulating layer 5, and lead electrodes 6 and 7 made of aluminum for the source region 2a and the drain region 2b are formed through these openings 5a and 5b, respectively.

[Problems to be Solved by the Invention] However, such a conventional MIS transistor, especially a thin film transistor (TF
In T), as shown in FIG. 5, there is a leak current (indicated by an arrow A in the figure) which depends exponentially on the gate voltage (V _G ). Until now, the cause of the flow of such a leak current has not been evident, and no means has been taken to reduce it. For this reason, integrated circuits using such thin film transistors are limited to those in which a significant reverse bias (OFF direction) is not applied to the gate due to the circuit configuration. It is difficult to apply the present invention to a configuration of an active matrix circuit.

FIG. 6 is a circuit diagram of one pixel of the liquid crystal display, in which 8 denotes liquid crystal, 9 denotes a thin film transistor (drive transistor), 10 denotes a video signal line, and 11 denotes a drive signal line. I have. Further, the video signal line 10, as the video signal Vsig as shown in the graph of FIG. 7, captures the video signal to the point C by opening and closing by a drive signal V _G of thin film transistors at a predetermined period, the liquid crystal 8 Apply voltage. Since the response of the liquid crystal 8 must be increased to some extent, the amplitude of the video signal Vsig needs to be constant. At this time, transistor leakage is most problematic when Vsig = 5V at point A, off-gate bias at point B = OV, and signal stored at point C = 10V (FIG. 8A). Note that this is equivalent to that shown in FIG. 8B, and therefore, there is a problem that the problem of leakage cannot be solved only by reducing the negative gate bias.

The present invention has been made in view of such conventional problems, and has as its object to obtain an MIS transistor having a small leak current and enabling a more free circuit configuration.

Means for Solving the Problems Accordingly, the present invention is directed to a MIS transistor formed on an insulating substrate, wherein the MIS transistor is formed by introducing impurities into a polycrystalline thin film. A region and a drain region, a channel region formed between the source region row and the drain region, and at least a region formed between the drain region and the channel region and having an impurity concentration of 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ^-3 , having a low-concentration impurity region in which the band gap does not decrease and does not degenerate when the sheet resistance is in the range of 20 kΩ / □ or less,
This is the solution.

[Operation] The impurity concentration in at least the semiconductor layer on the drain side adjacent to the channel region is set to 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ^−3.
By reducing the dose, at least degeneration of the semiconductor in the drain region is prevented, the height of the potential barrier through which carriers are to be tunneled is increased, and the leakage current of the transistor is reduced. Also, at least when the impurity concentration of the drain region is excessively lowered, the resistance becomes high. Therefore, with the lower limit of the concentration of 5 × 10 ¹⁶ cm ⁻³ , such a high resistance can be prevented.

EXAMPLES Hereinafter, details of the MIS type semiconductor transistor according to the present invention will be described based on examples shown in the drawings. The same parts as those in the related art will be described with the same reference numerals.

As shown in FIG. 1, a polycrystalline silicon thin film 2 having a thickness of 500 .mu.m is formed on an insulating substrate 1 as a semiconductor layer. The impurity concentration at both ends of the polycrystalline silicon thin film 2 is 5 × 10 ¹⁶ cm ⁻³ (dose amount 2.5 × 10 ¹¹ cm ⁻² ) to 5 × 10 ¹⁹ cm.
^The source region 2a and the drain region 2b are formed by doping n-type impurities such as phosphorus (P) so as to have a dose of 2.5 × 10 ¹⁴ cm ⁻² .

A channel region 2c is formed between the source region 2a and the drain region 2b, and a gate electrode 4 having a gate length of 5 μm is formed on the channel region 2c via a gate insulating layer 3. I have. The distance between the gate electrode 4 and the drain region 2b is set to 0.5 μm or less.

Further, an insulating layer 5 made of SiO ₂ is formed on the polycrystalline silicon thin film 2 and the gate electrode 4. Openings 5a and 5b are formed in the insulating layer 5, and these openings 5a and 5b are formed.
Extraction electrodes 6 and 7 made of aluminum for the source region 2a and the drain region 2b are respectively formed via a and 5b.

As described above, the leakage current can be reduced by setting the impurity concentration of the source region 2a and the drain region 2b to 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ .

Note that the leak current depends on the gate voltage (V _G ), V _D (source-drain voltage) dependency, temperature characteristics, etc., and the cause is the band-to-band tunnel phenomenon through a trap in polycrystalline silicon. It has been found that the causes of the tunnel phenomenon are (1) the presence of a large number of traps in polycrystalline silicon, (2) a strong electric field near the drain, and (3) the band gap Eg near the drain. Decrease, is considered. The present invention has been made focusing on (3).

Currently, in the manufacturing process of thin film transistors and ultra thin film transistors, two
Impurities are implanted at a dose of × 10 ¹⁵ / cm ² .
Therefore, the concentration of the source region and the drain region is 4 × 10
^It is considered that the concentration becomes as high as about ²⁰ / cm ³ and the band gap Eg is considerably reduced due to complete degeneracy. However, as a result of examining the relationship between the sheet resistance of polycrystalline silicon and the implantation dose, it was found that a dose of 2 × 10 ¹⁵ / cm ² was not necessarily required, and a smaller dose was sufficient. Therefore, by suppressing the concentration of the source / drain to about 10 ¹⁹ / cm ³ , it is possible to prevent the narrow gap effect as shown in FIG. 3 and maintain the original Eg. Here, the tunnel probability T is the height of the potential barrier Eg / 2
(Assuming the trap is at the center of the forbidden zone)
Exp (− (Eg / 2) ^3/2 ), which has a dependency, and enables a reduction in leakage current.

The Narrow Gap effect is due to the formation of an impurity band due to an increase in the impurity concentration and the band edge tailing effect, and the following Slotboom equation is known.

V ₁ , N _O , and C are constants.

Since the ON resistance of the thin film transistor is about 20 KΩ, if the channel width (W) / channel length (L) = 1, the sheet resistance needs to be 20 KΩ / □ or less. At 20 KΩ / □, an impurity concentration of about 5 × 10 ¹⁶ cm ⁻³ or more is required as a polycrystalline silicon thin film 800 °. If the impurity concentration is higher than 5 × 10 ¹⁹ cm ⁻³ , the non-degenerate semiconductor becomes a degenerate semiconductor, which is not appropriate.

Next, FIG. 2 shows another embodiment of the present invention. In this embodiment, the source region 2a adjacent to the channel region 2c and the vicinity of the channel region 2c of the drain region 2b are set to have an impurity concentration of 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and an n ⁻ layer.
2d and 2e are formed.

Although the embodiment has been described above, various other design changes are possible. For example, in the above embodiment, the impurity concentration of the source region is also set to 5 × 10 ¹⁶ cm ⁻³ × 10 ¹⁹ cm ⁻³ . However, a configuration in which the concentration is set only in the drain region may be adopted.

[Effects of the Invention] As is apparent from the above description, in the MIS transistor according to the present invention, the MIS transistor formed on the insulating substrate
Type transistor, wherein the MIS type transistor is
A source region and a drain region formed by introducing impurities into the polycrystalline thin film, a channel region formed between the source region and the drain region, and at least a region formed between the drain region and the channel region. By having a low-concentration impurity region in which the band gap does not decrease and the band gap does not decrease in the range of impurity concentration of 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and sheet resistance of 20 kΩ / □ or less, This has the effect of preventing the degeneration of the semiconductor in the drain region, increasing the height of the potential barrier through which carriers tunnel, and reducing the leakage current of the transistor.

In addition, this makes it possible to freely configure a circuit, and has an effect that it can be applied to an IC that has characteristics of a polycrystalline silicon thin film transistor such as a liquid crystal display.

[Brief description of the drawings]

1 is a sectional view showing an embodiment of an MIS transistor according to the present invention, FIG. 2 is a sectional view showing another embodiment, FIG. 3 is an energy diagram showing a narrow gap effect, FIG. Is a cross-sectional view showing a conventional example, FIG. 5 is a graph showing a leak current, FIG. 6 is a circuit diagram showing one pixel of a liquid crystal display, FIG. 7 is a graph showing a relationship between a video signal Vsig and time t, 8A and 8B are equivalent circuits showing voltage states. 1 ... insulating substrate, 2 ... polycrystalline silicon thin film (semiconductor layer), 2b ... drain region, 2c ... channel region.

Claims (1)

(57) [Claims] An MIS transistor formed on an insulating substrate, said MIS transistor comprising: a source region and a drain region formed by introducing impurities into a polycrystalline thin film; A channel region formed between the drain region and at least an impurity concentration formed between the drain region and the channel region, the impurity concentration being 5 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ ;
An MIS transistor having a low-concentration impurity region in which a band gap is not reduced and a non-degenerate impurity does not occur in a sheet resistance range of 20 kΩ / □ or less.