JPH03191448A - Vector data buffer circuit - Google Patents

Abstract

PURPOSE:To attain a vector operand buffer guaranteeing the ordering property of reading array data by storing data inputted from respective banks of a storage device in positions indicated by data counter devices in the corresponding banks of the vector data buffer. CONSTITUTION:When data are sent from the respective data terminals 1 to 4 of banks 0 to 3 in a main storage device reached to a cross bus switch 6 of the vector operand buffer, the switch 6 is driven by a control signal outputted from a logical circuit 5 storing a leading address and an increment value and the input data are distributed to respective banks 7 to 10 divided into respective blocks. The input data are stored in the buffer memories 71 to 101 of respective banks 7 to 10 which are specified by counters 11 to 14. Simultaneously, the contents of the counters 11 to 14 are increased by '1' through '+1' computing elements 92 to 102. Since four bands are independently driven for the data read out from the main storage device and then stored in the buffer memories, the vector operand buffer guaranteeing the ordering property of reading array data can be obtained.

Description

Detailed Description of the Invention [Field of Industrial Application] Data transfer between the main memory and a buffer memory that stores a copy of data in the main memory is usually performed in units of one block (one block is, for example, 64 bytes). ), and data transfer is performed between the same columns. The buffer memory is also separately provided with a digitizer called an address address (index array, data directory), which stores the number of the block stored at a corresponding location in the buffer memory. Since sequentially numbered blocks belong to different columns, the load on each column is usually averaged, resulting in
The probability that the required block exists in the buffer memory is 90
It is about %.

On the other hand, in the main memory, when the storage device is divided into multiple modules and sequential addresses are handled, a memory interleaving method is adopted so that all modules can operate in parallel and data can be transferred at high speed by a multiple of the number of modules. are doing.

By the way, in recent storage control devices, in order to improve the performance of the entire system, multiple instruction processors and input/output processors are connected, and in order to improve the processing throughput of the main storage device, each of them can operate independently. It has many memory banks. For example, in a vector computer, multiple processors are connected to one common main memory, and by processing these processors in parallel, each processor can access the shared main memory and read data at high speed. It needs to be read out.

However, if, for example, four instruction processors are connected to the main memory, the main memory is divided into four boats to improve throughput, and each boat operates independently. There is no guarantee that data will be returned in the order of requests issued. That is, it is completely unknown which of the ports 0 and 1 reads data faster. When vector calculations and the like are shared and processed by a plurality of instruction processors, if the data read order for array data read request sequences issued by the instruction processors is different, this will cause problems in operation.

As a conventional device for storing read data from such a storage device in an operand buffer in the order in which requests are issued, there is a method described in, for example, Japanese Patent Laid-Open No. 136849/1983. In the method described in the above publication, when issuing a request, the storage address information of the buffer memory is added and issued, and when the data is read from the storage device and sent back to the buffer memory, that information is added and sent back. Accordingly, the data is stored in the buffer memory based on the address information.

Problems to be Solved by the Invention In the method described in the above publication, storage buffer address information is added when a quest is issued, and this information is returned together when reading data. Since it is necessary to hold logic for the number of connected instruction processors on the storage device side, the amount of hardware increases enormously. In other words, it is necessary to circulate buffer storage position information within the storage device for the number of processors connected to the storage device, so in recent storage devices with a large number of connected processors, the amount of hardware required is enormous. Therefore, it becomes impossible to realize.

SUMMARY OF THE INVENTION An object of the present invention is to provide a vector data buffer device that can solve the above-mentioned conventional problems and guarantee the order of read array data with almost no increase in the amount of hardware.

[Means to solve the problem]

In order to achieve the above object, (a) the vector data buffer device of the present invention has the following features: , the number of banks on the vector data buffer side is determined, a switch means connects the corresponding banks of both the storage device and the vector data buffer, and a plurality of operand buffers that store input data are controlled by the connection control of the switch means. bank memories and data counting means for each bank to count the number of data stored in each bank memory, and the data counting means for each bank counts the data input from each bank of the storage device to the data counting means of the corresponding bank of the vector data buffer. The feature is that it is stored in the position indicated by the means. Furthermore, the switch device of the present invention utilizes the fact that the correspondence between the bank of the storage device and each array data has a repeatability when there is a constant interval between multiple pieces of array data. The feature is that the data path switch from each bank of the storage device is selectively controlled so as to be connected to the corresponding bank of the vector data buffer. Furthermore, (c) the vector arithmetic device of the present invention stores array data from the main memory in a vector data buffer, and then sequentially retrieves the array data stored in the vector data buffer and outputs it to the arithmetic unit; The arithmetic unit is characterized in that it performs arithmetic operations on input array data and stores the results of the arithmetic operations in vector registers. Furthermore, (d) the vector register of the present invention uses a vector data buffer device as a vector register, and the vector data buffer stores the array data from the main memory in the corresponding bank under selection control of the switch means, and then stores the array data in the corresponding bank. is extracted and output to a computing unit, the computing unit performs arithmetic operations on the input array data, and stores the result of the arithmetic operation in a specified bank of the vector data buffer device under selection control of the switch means. There is.

[For production]

In the present invention, a counter is provided on the operand buffer side to store the start address and data interval of the array data, and also to count the number of data for each bank of the operand buffer, and this information is used to read data from the storage device. The storage buffer location of the array data is quickly determined. That is, the operand buffer is divided in advance into banks that are repeated at a constant period corresponding to the banks, and the bank in which the input data is to be stored can be determined from the data start address on the main memory and the increment value.

As a result, buffer data with guaranteed order can be obtained even if the order of data is not guaranteed between storage banks. In addition, since all the increase in hardware is provided on the operand buffer side, there is almost no increase in the amount of hardware on the storage device side.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of main parts of a system including a vector data buffer device to which the present invention is applied.

In FIG. 2, 15 is a storage device with four banks, 17 is a vector operand buffer with banks associated with the banks of the storage device, and 18 is a vector operand buffer. The arithmetic unit 16 is a vector register that stores the result of the arithmetic operation by the arithmetic unit 18 and provides input data to the arithmetic unit 18 .

A crossbar (see FIG. 1) provided in the vector operand buffer space associates the banks of the storage device I5 with the banks of the buffer 17. The data taken out from the storage device 15 is rearranged by the arithmetic units in the vector operand buffer 17 and then sent to the arithmetic units 18.

By the way, when accessing the storage device 5 to obtain data arranged at regular intervals such as array data,
The correspondence between the request issuing order and the banks of the storage device 15 has a property that it is repeated at a certain period. Therefore, if the operand buffer 17 is divided into banks corresponding to this repetition period, data to entries in the same bank of the operand buffer 17 will come from the same storage bank.

In the operand buffer 17, the main memory 111
5, each bank of the operand buffer 17 is connected to a storage bank determined from the data start address and increment value on the main storage device 15. When the data arrives at the operand buffer 17,
Stored sequentially in banks of connected buffers. A counter for counting the number of arriving data is provided for each bank of the buffer 17, and input data is stored at the position indicated by these counters. As a result, between memory banks,
Even if the data does not arrive in the requested order, the operand buffer 17 stores data whose order is guaranteed.

FIG. 1 is a diagram showing the entire configuration of a vector operand buffer showing one embodiment of the present invention, and FIG. 3 is a diagram showing an 8-byte data arrangement and bank assignment in a secure storage device.

In FIG. 1, 1 to 4 are data terminals in each bank of the storage device, 5 is an incomplete crossbar selector signal generation logic circuit, 6 is a crossbar switch that is turned on and off under the control of the logic circuit 5, and 7 to lO is a bank of the vector operand buffer, 11 to 14 are counters in the vector operand buffer, 71, 81, 91, and 101 are buffer memories in each bank, and 72, 82, 92, and 102 are +
This is an adder that adds 1.

Data is sent from each data terminal 1 to 4 of banks O to 3 of the main storage device, and when it arrives at the crossbar switch 6 of the vector operand buffer, control from the logic circuit 5 that stores the start address and increment value is performed. The crossbar switch 6 is operated by the signal, and the input data is distributed to one bank 7 to 10 divided into blocks.

In banks 7-10, input data is stored in buffer memories 71-101 designated by counters 11-14. At the same time, the counters 11 to 14 are +1 to the computing unit 9.
It is incremented from 2 to +02. In addition, the counter l
] to 14 designate the memory number in the bank in which the data is to be stored. As a result, data arriving from the main memory is simultaneously stored in the buffer memory by the four banks operating independently.

FIG. 3 shows an 8-byte data array allocated to each bank on the main memory side. The main memory is divided at 32-byte boundaries and further divided into four 8-byte areas, each corresponding to bank 0, bank 1, bank 2, and bank 3 from the beginning. That is,
In FIG. 3, byte O (8-16) is placed in bank 1 by a request from the instruction processor, and byte 1 (
32 to 40) to bank O, byte 2 (56 to 64) to bank 3, byte 3 (80 to 88) to bank 2, and byte 4 (104 to 112) to bank 1, respectively. As is clear from this, the first address is address 8, and from the first address 8, the first 3 of the next bank assignment.
The increment value (period) up to address 2 is 3×8 bytes=24 bytes.

Under the allocation in the main memory, the correspondence between data having a fixed increment value and banks has a certain repeatability. In the case of FIG. 1, the crossbar logic circuit 5 has a starting address of 8 and an increment value of 2.
By storing 4 bytes, byte O is assigned to bank 1, byte 1 is assigned to bank 0, byte 2 is assigned to bank 3, byte 3 is assigned to bank 2, and so on. Since byte 4 is assigned to each bank l, even though the ordering of the byte data read is not guaranteed - each byte data is input independently from that bank to the corresponding bank of the same numbered operand buffer; It will be stored in buffer memory.

Now, the vector elements are numbered 1°0.2 from the beginning.
,3. ..., the start address of the vector (number 0 element address) is set as A, and the increment value is set as INC.

In order for the main memory addresses accessed by the 0th and nth vector elements to match modulo 32, the following (1
) and (2) should hold true.

A+INCXn=A+32Xm-(1)TNCXn=3
2Xm HHHHH+ H+ (2) where m is any integer. In the above formulas (1) and (2), if the vector element is 8 bytes, the increment value INC
If we set INCmi8×△(Δ=0.±1.±2..), the following equation holds true.

ΔXn==4Xm ・ ・ ・ ・ ・ ・ ・
・ ・ ・ ・(3) When Δ is an arbitrary integer, the minimum value of n that satisfies the above formula (3) is 4. Therefore, the bank access pattern repeats every four elements.

That is, the vector elements are +0.4, 8. l 2゜...
・l, (+, 5, 9, 13. ...).

(2,6,10,14,...), (3,7°11,
+5. ...), the elements in each set will receive data from the same bank. In this way, when the data boundary of the storage device is 32 bytes and the vector element is 8 bytes, by dividing it into 4 banks, 8 banks, 12 banks, etc., data bytes at regular intervals can be input from the same bank. do.

In this case, since the order of data is guaranteed within one bank, the arriving data may be stored in the buffer memory in order.

FIG. 4 is a diagram showing the correspondence between banks and vector operand buffers in the case of 8-byte data.

In FIG. 4, 23-26 are banks 0-3 of the storage device.
19 to 22 are vector operand buffer banks, 27 to 30 are counters in each bank, and 31 to 34 are buffer memories in each bank.

The data relationships in FIG. 4 correspond to those in FIG. 3, and from bank O on the storage device side, byte data 1,5°9, . . .
However, bank l has byte data 0°4.8.・・・・・・
However, bank 2 is full of bite pigs 3, 7 . l 1,15.
...but bank 3 contains byte data 2, 6,
10,14. ... are sent respectively. On the other hand, in the case of FIG. 4, on the vector operand buffer side, bank O of the storage device is set to operand buffer bank 20, and bank 1 is set to operand buffer bank 19.
, bank 2 is connected to operand buffer bank 22, and bank 3 is connected to operand buffer bank 21, respectively. In this way, the operand buffer banks 19 to 22, which are divided into banks, correspond to the banks 0 to 3 of the storage device.

Therefore, the operand buffers 31 to 34 are 0°4.8
．． . . . Bang 19 consisting of the buffer memory 31
．． 1, 5, 9. . . . Banks 20.2, 6, 10°, . . . , banks 21.3, 7, 11 .
...th buffer memory 34 is also divided into banks 22. In this way, each bank 19~
22 is connected to one specific bank terminal 23 to 26 on the storage device side prior to data reading.

In this way, after being connected to specific bank terminals 23 to 26, banks 19 to 26 of the vector operand buffer are connected to specific bank terminals 23 to 26.
Arrived data may be stored in the position indicated by the counters 27 to 30 provided for each 22. When one bank terminal 23 to 26 of the storage device is connected to two or more vector operand buffer banks 19 to 22, elements are sequentially transferred one element at a time from the lowest numbered bank to the highest numbered bank. Just store it.

FIG. 5 is a data arrangement diagram on the main memory device showing another embodiment of the present invention, and shows an example of arrangement of 4-byte data on the main memory device. Further, FIG. 6 is a connection diagram between the storage device and the vector operand buffer in the case of FIG. 5.

Here, consider the optimal number of banks in the case of 4-byte data. We use both equations (2) again.

INCXn=32Xm HHHHH+ ' ・(2)
In the above equation (2), INC is an increment value, which is vector element x Δ, n is the sequence number of accessing the storage device, and m is an arbitrary integer. Here, if the vector element is 4 bytes, INC=4XΔ, so the above equation (2) becomes the following equation.

△xn=8Xm (△=0. ±1. ±2. ・ -
)・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
- (4) The minimum value of n that satisfies the above formula (4) is 8. Therefore, for 4-byte data, banks on the storage device are repeated every eight.

If the storage device has 4 banks, as shown in Figure 5, by connecting two buffer banks per j banks, the vector operand buffer can be stored by storing the start address 8 and the increment value 12 bytes in the crossbar logic circuit. Data to entries within the same bank of will arrive from the same bank of storage.

In FIG. 6, the vector operand buffer is divided into eight banks 43-50. The correspondence between banks is shown in the case of the data arrangement shown in FIG. Here, as the bank arrangement of the vector operand buffer, bank numbers are arranged vertically from the upper left and sequentially to the right. That is, bank 43 is assigned to bank number 0, bank 47 is assigned to bank number 1, bank 44 is assigned to bank number 2, bank 48 is assigned to bank number 3, etc., respectively.

Therefore, as shown in FIG. 5, bank number 2 (that is, bank 44) of the vector operand buffer is assigned to the terminal 35 of the upper 4 bytes of bank 0 of the storage device, and the buffer number is assigned to the terminal 36 of the lower 4 bytes of the storage device. Set bank number 5 (that is, bank 49) to terminal 3 of the upper 4 bytes of bank 1.
7 is the buffer bank number 0 (i.e. bank 43)
Similarly, buffer bank number 3 (that is, bank 48) is sequentially connected to the terminal 38 of the lower 4 bytes.

In this way, the data stored in the vector operand buffer is transferred to the buffer memory V when the operation is started.
OBOO to VOB5F are sequentially taken out and sent to the arithmetic unit.

In addition, in this embodiment, a vector operand buffer was described that retrieves 8-byte data and 4-byte data from a storage device with an 8-byte width and 4-bank configuration, but the storage device configuration and the data width to be retrieved may be different from other dimensions. It is possible to apply the present invention in exactly the same way.

FIG. 7 is an explanatory diagram of a method of using a vector operand buffer showing another embodiment of the present invention.

In FIG. 7, vector operand buffer 17a
In addition to using it as an original functional circuit, it is also used as a vector register.

Therefore, the vector register 16 in FIG. 2 is removed, the output data line of the arithmetic unit 18 is connected to the input side of the vector operand buffer +7a, and the input data line input to the arithmetic unit 18 is also connected to the vector operand buffer 17a.
Connect to the output side of the

Note that the number of banks n of the vector operand buffer 17a
Of these, m are used as vector operand buffers, and the remaining (n-m) are used as vector registers.

As described above, the present invention is extremely effective when applied to a device composed of a plurality of independently operable memory banks, and a system that extracts continuous data at regular intervals and stores it in a high-speed buffer. In other words, by taking advantage of the repeatability of the correspondence between data request numbers and banks, the start address and increment value are stored and the crossbar switch is used to store the storage device without adding information such as the request number to the request. Banks and buffer banks are associated and connected. As a result, the four banks of the storage device independently and simultaneously write data to the operand buffer, so that the data order can be guaranteed.

[Effect of the Invention J As described above, according to the present invention, a vector operand buffer that guarantees the order of read array data can be realized without increasing the hardware on the storage device side.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a vector operand buffer showing an embodiment of the present invention, FIG. 2 is a blog diagram of a system using the vector operand buffer of the present invention, and FIG. Byte data layout diagram, 4th
The figure shows the correspondence arrangement between banks and vector operand buffers in Fig. 3, Fig. 5 shows the bank allocation and 4-byte data arrangement of the main memory, and Fig. 6 shows the correspondence arrangement between banks and vector operand buffers in Fig. 5. The corresponding layout diagram, FIG. 7, is a connection diagram of a vector operand buffer showing another embodiment of the present invention. 1-4.23-26.35-42. Data terminal of bank of storage device, 5: Crossbar selection signal generation logic circuit, 6
:Crossbar switch, 7~10°19~22.43~5
0: Bank of vector operand buffer, 11-1.
4.27-30: Counter in vector operand buffer, 15: Main memory, 17: Vector operand buffer, 16, Vector register, 18: Arithmetic unit, 31
~34.71,81,91,101: Vector operand buffer memory, ? 2,82,92. ] Ding P2 storage device 64 Figure leap 8 Figure Bank O Bank 1 Bank 2 Bank 3

Claims (1)

[Scope of Claims] 1. In a vector data buffer device that receives a plurality of array data from a storage device configured with a plurality of memory banks that perform independent operations and stores the array data, the array data on the storage device The number of banks on the vector data buffer side is calculated based on the data width of the array data, the first address among the plurality of array data, and the data interval between the array data, and the number of banks on the vector data buffer side is calculated. a plurality of operand buffer bank memories for storing input data through connection control of the switch means; and counting the number of data stored in each of the bank memories. A vector data buffer comprising data counting means for each bank, and storing data input from each bank of the storage device at a position indicated by the data counting means in a corresponding bank of the vector data buffer. Device. 2. In a vector data buffer device that receives a plurality of array data from a storage device composed of a plurality of memory banks that perform independent operations and stores the array data, the intervals between the plurality of array data are constant. In this case, the switch of the data path from each bank of the storage device is connected to the corresponding bank of the vector data buffer by utilizing the repeatability of the correspondence between the bank of the storage device and each array data. A switch device characterized in that the switch device performs selection control such that the 3. Using the vector data buffer device according to claim 1, store the array data from the main memory in the vector data buffer, and then sequentially retrieve the array data stored in the vector data buffer and perform calculations. 1. A vector arithmetic device, wherein the arithmetic unit performs an arithmetic operation on input array data, and stores the result of the arithmetic operation in a vector register. 4. In the vector arithmetic device according to claim 3, the vector data buffer device according to claim 1 is used as a vector register, and the vector data buffer device corresponds to the array data from the main storage device by selection control of the switch means. After storing the array data in the bank, the array data is taken out and output to the arithmetic unit, the arithmetic unit performs an operation on the input array data, and the result of the operation is transferred to the vector data buffer by selection control of the switch means. A vector register characterized in that it stores in a designated bank of the device.