JP2944108B2 - Access device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an access device that generates an address in response to an instruction from an instruction control unit that issues an instruction including a plurality of elements and accesses a storage device. In order to raise the address, an access device that generates an address in response to an instruction from the instruction control unit that issues an instruction composed of multiple elements and accesses the storage device corresponds to the address corresponding to its own system or another system A plurality of address generators for generating an address corresponding to one instruction and a plurality of address generators for generating an address of an element corresponding to the own system and an address of an element corresponding to the other system by the plurality of address generators. Is supplied to each of the plurality of address generators, and the address of the element corresponding to the other system is supplied. When generating the addresses for all elements corresponding to the self-system is in place less of occurrence,
Switching means for supplying a plurality of elements for a plurality of instructions to each of the plurality of address generation units.

[Industrial applications]

The present invention relates to an access device that generates an address in response to an instruction from an instruction control unit that issues an instruction including a plurality of elements in a vector processing system, and accesses a storage device.

[Conventional technology]

Generally, in a pipeline-type vector computer, the speed is increased by increasing the number of pipelines, that is, by increasing the number of elements that can execute operations simultaneously.

Further, in the main storage device, the memory can be accessed in parallel as the number of interleaves increases, so that the speed can be increased.

By the way, in the memory access control, priority control is performed because there is a contention check of a memory use condition and a contention for access to the same bank or a contention for access to another access device such as a scalar unit or a channel (I / O processing device). is necessary.

However, by increasing the number of elements that can be processed in parallel or by increasing the interleaving, the checking of the memory use state and the priority control become complicated, and the number of logic stages becomes large. Increases, which hinders speeding up.

FIG. 4 shows an example of the configuration of a conventional vector processing system.

In FIG. 4, reference numerals 411 and 413 denote main storage units (MSU),
1 is a vector instruction control unit, 431 is a 0-system vector unit, 441 is a 1-system vector unit, 433 and 443 are vector address generation units, 435 and 445 are main memory access processing units, and 437 and 447 are vector access processing units. , 439 and 449 indicate vector registers (VR), respectively. Other elements shown in each block will be referred to as needed in the following description of functions.

The main storage devices 411 and 413 each include two memory units (MU-0, MU-1) and (MU-2, MU-3), and are in a state where they can be accessed in parallel by the vector units 431 and 441 of each system. .

Here, up to four elements can be accessed at the same time. In this case, the 0-system vector unit 431 processes the elements of element numbers 4n, 4n + 1 (n = 0, 1,...) And the 1-system vector unit 441. 4n + 2,4n
The element of +3 is to be processed.

From the vector instruction control unit 421, the vector address generation unit 43 of each system is
3,443, and control information such as an activation signal, an operation code (OPC), a start address (LA), a distance (D), and a vector length (L) are transmitted to the vector access processing units 437 and 447. The following description is for the case of loading vector data.

The 0-system vector address generator 433 generates a vector address for each of the 0 element and 1 element (4n + 0, 4n + 1 elements). These generated addresses are set in the respective registers RQA and RQB, and the registers RQRA and RQRB of the main memory access control unit 435 are set.
Is transferred as an access request.

The priority control circuit in the main memory access control unit 435 may determine that the vector address of the register RQRA or RQRB indicates the same memory unit or the same main storage device depending on the size of the distance (D). Which access is output to the main storage device is determined by priority control.

Here, if access is such that the vector addresses of the registers RQRA and RQRB point to different main storage devices, memory access can be performed simultaneously by the vector addresses of RQRA and RQRB.
It is sent to the main storage devices 411 and 413 via B.

Thus, the access request accepted by the priority control circuit is sent to the main storage devices 411 and 413, and activation is performed.
For example, on the main storage device 411 side, it is impossible to simultaneously receive access requests from the 0-system and the 1-system for a certain memory unit.

Therefore, the main memory access control units 435 and 445 of each system can issue an access request only at a certain prescribed timing. Also, since the 0-system and the 1-system access independently, the priority control circuit of the own system is recognized by recognizing the state of the priority control circuit of the other system in order to guarantee the order of the elements between the respective systems. , Complicated control is performed.

FIG. 5 shows an example of the access permission timing defined in the vector units 431 and 441 of the 0-system and the 1-system, respectively. As shown in the figure, the system 0 and the system 1 are connected to the memory unit MU-
MU-0 and MU-2, MU-1 and MU-
The access permission timings are assigned alternately so that they do not overlap with each other.

The vector data read from the main storage devices 411 and 413 are sent to the vector access processing units 437 and 447 of the access-source 0-system or 1-system vector units 431 and 441 for each element, and read elements for requests at the same time are prepared. Vector register in stages
Stored in 439,449.

The vector access processing units 437 and 447 return an end signal to the vector instruction control unit 421 when the transfer of the data corresponding to the vector length (L) is completed in the vector data access.

[Problems to be solved by the invention]

In a conventional vector processing system in which a plurality of vector units can independently control access to a plurality of main storage devices, an access request from each system vector unit is generated simultaneously for one memory unit. In order to avoid this, there is a problem that the timing of permitting access from each system is shifted so that the apparent access time becomes longer. Further, there is a drawback that complicated control for controlling the order with another system priority control circuit is required to guarantee the order of the elements.

In order to solve these disadvantages, the present applicant has already proposed Japanese Patent Application No. 63-280997, "Vector Processing System". According to this vector processing system, the vector units of each system manage the state of the banks (memory units) of all the main storage devices, and perform access checks including access requests of vector units of other systems. An access request can always be transmitted at the timing when it is detected that the bank containing the access address of the own system is vacant, and during the period in which each system is allocated so as not to overlap each other as in the conventional system described above. The access processing time can be greatly reduced as compared with the case where only access was possible.

FIG. 6 shows a schematic configuration of this vector processing system. Note that a vector access processing unit, a vector register, and the like that are not directly related to the description are omitted.

In the figure, a vector address generation unit 621 in a 0-system vector unit 611 includes two address calculation units (AD) 631 and 633 for calculating addresses relating to accesses from the 0-system vector unit 611 to the main storage devices 691 and 693, and a 1-system Address calculators for calculating addresses related to accesses from the vector unit 651 to the main storage devices 691 and 693
635,637.

Similarly, a vector address generator 661 in the vector unit 651 of the first system includes two address calculators 671 and 673 for calculating an address corresponding to the system 0 and two address calculators 675 and 677 for calculating an address corresponding to the first system. And

The two address operation units 635 and 637 corresponding to the first system in the 0-system vector address generation unit 621 operate in synchronization with the two address operation units 675 and 677 corresponding to the first system in the 1-system vector address generation unit 661. Thus, the same operation result (address) can be obtained.

Accordingly, the priority control circuit 643 in the 0-system main memory access control unit 641
The priority control of the two main storage devices 691 and 693 can be performed only by the addresses output from the two address calculation units 631 to 637, and the device for shifting the timing as shown in FIG. 5 is not required. At this time, the addresses output from the address calculation units 635 and 637 corresponding to the first system are simply used for priority control and are not used for actual access. The same applies to the priority control in the vector unit 651 of the first system.

By the way, the configuration shown in FIG. 6 realizes a processing capability of four elements by operating two vector units 611 and 651 capable of processing two elements in parallel. Therefore, in the case where the vector unit 611 or 651 is used alone when the processing capability of two elements is required, there is a problem that the address operation unit corresponding to another system is not used and waste occurs. was there.

In particular, when a large distance access is performed by such a vector unit, the address calculation is performed using all the address calculation units corresponding to the own system, and there is an unused address calculation unit corresponding to another system. Nevertheless, only one large distance access can be performed at the same time. Therefore, there has been a demand for a vector processing system capable of simultaneously performing a plurality of distance large accesses by using an unused address operation unit and improving access efficiency.

The present invention has been made in view of such a point, and an object of the present invention is to provide an access device that can effectively use an address generation unit and increase access efficiency.

[Means for solving the problem]

 FIG. 1 is a principle diagram of an access device of the present invention.

In the figure, an access device according to the present invention generates an address in response to an instruction from an instruction control unit 121 that issues an instruction composed of a plurality of elements, generates an address, and accesses the storage device 111. A plurality of address generators 141a and 141b for generating an address or an address corresponding to another system, and the plurality of address generators 141a and 141b determine an address of an element corresponding to the own system and an address of an element corresponding to the other system. In the case of generating, the plurality of elements for one instruction are supplied to each of the plurality of address generation units, and the addresses of the elements corresponding to the own system are all replaced with the addresses of the elements corresponding to the other system. When generating, a plurality of elements for a plurality of instructions are supplied to each of the plurality of address generators. It is configured to include a selection means for the 131.

(Operation)

The selection means 131 receives a command from the command control unit 121,
The head address, distance, and the like of the vector data are supplied to the plurality of address generators 141a and 141b.

At this time, when a plurality of elements a for one instruction are supplied from the selection unit 131, the address generation unit 141a
Generates the address of the element corresponding to the own system, and the address generator 141b generates the address of the element corresponding to the other system.

On the other hand, when a plurality of elements b for a plurality of instructions are supplied from the selecting unit 131, the address generation unit 141a generates an address of an element corresponding to the own system, and the address generation unit 141b also supports the own system. Generates the address of the element.

That is, since the address generation unit for the other system can be switched and used for the own system, the access efficiency can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows the configuration of a vector processing system according to one embodiment of the present invention.

In FIG. 2, reference numerals 211 and 212 denote main storage units (MSUs).
3 is the vector instruction control unit, 215 is the vector unit,
221 is a vector address generation unit, 231 is a main memory access control unit, 233 is a priority control circuit, 235 and 237 are access pipelines, 241 is a vector access processing unit, 243 is a vector access control circuit, and 245 is an element. Reference numeral 247 denotes an indirect address read control unit, and reference numeral 251 denotes a vector register (VR).

It is assumed that memory access by this vector processing system can be performed up to two elements at the same time.

When executing the vector access instruction, the vector instruction control unit 213 supplies an activation signal, an OP code, a head address (LA), a distance (D), a vector length (L) of vector data, and the like to the vector unit 215. I do.

Vector address generator 221 of vector unit 215
Calculates the address of each element based on the head address (LA) and the distance (D) supplied from the vector instruction control unit 213. The calculated address is a priority control circuit in the main memory access control unit 231. Sent to 233.

Assuming that each of the main storage devices 211 and 212 has a plurality of memory units (banks), a priority control circuit
At 233, the use state of each bank of the main storage devices 211 and 212 is constantly managed, and it is checked whether or not the corresponding bank can be accessed in a free state for each address given from the vector address generation unit 221. If possible, the use state management is updated to "in use", and an access request addressed to the corresponding bank is sent to the main storage device 211 or 212.

This access request is sent to one of the access pipelines 235 and 237 in the main memory access control unit 231 together with the transmission to the main storage devices 211 and 212, and after a predetermined time, the vector access control circuit 243 of the vector access processing unit 241.
Then, notification of acceptance of the corresponding data is made.

The vector access control circuit 243 transfers the read data from the main storage device 211 or 212 to the element order alignment circuit 2 at the timing when the data reception notification is input.
At step 45, the elements are ordered and loaded into the vector register 251.

FIG. 3 shows a detailed configuration of the vector address generator 221.

In FIG. 3, 311,313,315,317 are adders, and 361,3
63, 365, 367 indicate address conversion tables, respectively. Also, 321-328,341-347,371-377,381-387,395,
Reference numeral 397 denotes a register (R), and reference numerals 331 to 338, 351 to 357, 391, and 393 denote selectors.

The vector processing system according to the embodiment can continuously generate vector addresses by a normal method of performing an address operation based on a head address and a distance for all elements of vector data, and can directly access the elements.

The adders 311 and 313 are for calculating the respective addresses of the two elements. To one input terminal of the adder 311, a start address (LA) supplied from the vector instruction control unit 213 via the selector 331 and the register 321.
The selector 332 and the register
The distance (D) supplied from the vector instruction control unit 213 is input via 322. The adder 311 calculates the address of the element with the element number 2n by adding the input start address and the distance, and the calculated address is converted by the address conversion table 361.
The data is sent to the priority control circuit 233 in the main memory access control unit 231 via the register 381. The address output from the adder 311 is sent to the address conversion table 361 and stored in the register 321 via the selector 331. The next address calculation is performed by adding a distance to the value stored in the register 321. .

Similarly, the adder 313 calculates the address of the element having the element number 2n + 1 by adding the input start address and the distance, and outputs the calculated address via the address conversion table 363 and the register 383 to the priority control circuit 233.
Sent to

Further, in the adders 315 and 317, similarly to the adders 311 and 313, the addresses of the elements having the element numbers 2n and 2n + 1 are calculated, and the calculated addresses are respectively transferred to the priority control circuit 233 via the address conversion table 365 or 367.
Sent to

The four selectors 351 to 357 correspond to the four adders 31 described above.
This is for supplying the head address and the distance from the vector instruction control unit 213 to 1 to 317. The four registers 341 to 347 are provided in the vector instruction control unit 21.
This is for temporarily storing the head address (LA) and the distance (D) output from 3. The connection relationship between the four registers 341 to 347 and the two instruction output ports of the vector instruction control unit 213 is as follows.

As shown in FIG. 2, when there is one vector unit 215, one of the two instruction output ports of the vector instruction control unit 213 is connected to the registers 341 and 343 or the registers 345 and 347. For example, suppose that it is connected to the registers 341 and 343.

At this time, when there is one instruction from the vector instruction control unit 213, the selectors 351 and 353 select the registers 341 and 343, and the selectors 355 and 357 do not perform the selecting operation. Therefore, the adders 311 and 313 generate addresses for the own system, and the adders 315 and 317 are not used.

When there are two instructions from the vector instruction control unit 213, in addition to the selectors 351 and 353, the selectors 355 and 357 also perform the operation of selecting the registers 341 and 343. As a result, the head address output from the vector instruction control unit 213 is temporarily stored in the register 341 and then supplied to the adders 311 and 313 via the selector 351 and supplied to the adders 315 and 317 via the selector 355. .

The distance (D) output from the vector instruction control unit 213 is temporarily held in the register 343, and then stored in the selector 353.
Are supplied to adders 311 and 313 via
It is supplied to adders 315 and 317 via 57.

The priority control circuit 233 is connected to the vector address generator 221
Priority control is performed based on the four addresses sent through the three registers 381 to 387.
The access request corresponding to the address sent from 3 is sent to the main storage device 211 and also supplied to the access pipeline 235. The access request corresponding to the address sent from the registers 385 and 387 is sent to the main storage device 212 and is also sent to the access pipeline 237.

Therefore, two independent large distance accesses can be executed in parallel.

When two vector units 215 are provided, the vector instruction control units 213
One of the two instruction output ports (own output port)
For example, it is connected to registers 341 and 343, and the other (other system output port) is connected to registers 345 and 347.

At this time, if the number of instructions output from the two ports of the vector instruction control unit 213 is one, the selector 351,
353 selects registers 341 and 343, and selectors 355 and 357
Select the registers 345 and 347. Therefore, adders 311 and 3
13 generates an address for the own system, and adders 315 and 317 generate addresses for the other system. Thereby, a processing capability of four elements can be realized (corresponding to the case shown in FIG. 6).

When the instructions output from the two ports of the vector instruction control unit 213 are both two, in one vector unit 215, the selectors 351 to 357 select the registers 341 and 343, and in the other vector unit 215, 351-
357 selects registers 345 and 347. As a result, in one vector unit 215, all of the adders 311 to 317 are connected to the own system output port of the vector instruction control unit 213, and in the other vector unit 215, all of the adders 311 to 317 are controlled by the vector instruction control. Unit 213 is connected to another system output port.

In the other vector unit 215, the head address input from the other output port of the vector instruction control unit 213 is temporarily stored in the register 345, and then stored in the selector 351 or 355.
Are supplied to the adders 311, 313, 315, and 317 via. Also,
The distance is temporarily stored in the register 347 and then supplied to the adders 311, 313, 315, 317.

When the address operation of the own system and the address operation of the other system are performed in this manner, the access request corresponding to the address of the other system is used only for contention control in the priority control circuit 233, and the main storage devices 211 and 212 and the access Pipeline 235,2
Do not send to 37.

Further, the vector processing system of the embodiment includes an indirect address mechanism for processing discrete elements. When performing access using an indirect address, the vector register 251 is loaded in advance with vector data indicating the address of each element of the vector data to be accessed, and the indirect address read control unit 247.
, And sequentially read out two elements at a time, and supply them to the vector address generator 221. The vector addresses of the two elements read from the vector register 251 are given to the register 322 corresponding to the adder 311 and the register 324 corresponding to the adder 313 in the vector address generator 221 and transferred to the priority control circuit 233. You.

In the configuration of the vector address generator 221 shown in FIG. 3, the vector data from the vector register 251 is supplied only to the adders 311 and 313, so that the adders 315 and 317 are used at the same time. Although it is not possible to generate an indirect address, if access by indirect address is performed in parallel using all the adders, the access to the vector register 251 via a selector (not shown) is performed in the same manner as the access by direct address described above. What is necessary is just to supply the vector data to all the adders.

The change of the contents of the address conversion tables 361 to 367 in the vector address generation unit 221 is performed by two selectors 391,
The selection state of 393 is appropriately switched. For example, the register 395 is for reading output data of the element order alignment circuit 245 of the own system, and the read data is supplied to each address conversion table via the selector 391 or 393. The register 397 is for reading output data of an element order alignment circuit (not shown) of another system, and the read data is supplied to each address conversion table via the selector 391 or 393.

As described above, when the vector unit 215 is used alone, the adders 315 and 317 for performing the address calculation in synchronization with the other system are used for the address calculation of the own system. Therefore, the address can be calculated in parallel with the adders 311 and 313 originally provided for the own system, and two large distance accesses can be performed, so that the access efficiency of the main storage devices 211 and 212 can be improved.

The above-described embodiment is described in the earlier application (Japanese Patent Application No. 63-2809).
No. 97), the present invention can be similarly applied to the conventional apparatus shown in FIG. 4 for mutually adjusting the timing when two vector units are operated in parallel.

〔The invention's effect〕

As described above, according to the present invention, each of the vector address generators corresponding to a plurality of systems generates a vector address of the own system in parallel, sends a corresponding access request to the main storage device, and By inputting data to each of the access pipelines, a plurality of distance large accesses can be performed in parallel, and the access efficiency can be increased. Therefore, it is extremely useful in practice.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of an access device according to the present invention, FIG. 2 is a block diagram of a vector processing system according to an embodiment of the present invention, FIG. FIG. 5 is a configuration diagram of a conventional vector processing system, FIG. 5 is an explanatory diagram of access permission timing in the conventional system, and FIG. 6 is a configuration diagram of a conventional vector processing system. In the figure, 111 is a storage device, 121 is an instruction control unit, 131 is a selection unit, 141a and 141b are address generation units, 211 is a main storage device (MSU), 213 is a vector instruction control unit, 215 is a vector unit, and 221 is Vector address generation unit, 231 is a main memory access control unit, 233 is a priority control circuit, 235 and 237 are access pipelines, 241 is a vector access processing unit, 243 is a vector access control circuit, 245 is an element order alignment circuit, and 247 is an indirect address A read control unit, 251 is a vector register, 311, 313, 315, 317 are adders, and 361, 363, 365, 367 are address conversion tables.

Claims (1)

(57) [Claims] An access device for generating an address in response to an instruction from an instruction control unit for issuing an instruction composed of a plurality of elements and for accessing a storage device, wherein an address corresponding to its own system or an address corresponding to another system is provided. A plurality of address generators for generating addresses; and a plurality of address generators for generating a plurality of address generators for generating an address of an element corresponding to the own system and an address of an element corresponding to another system by the plurality of address generators. In the case where an element is supplied to each of the plurality of address generators and an address of an element corresponding to the own system is generated instead of generation of an address of an element corresponding to another system, a plurality of instructions for a plurality of instructions are provided. Selecting means for supplying an element to each of the plurality of address generators. Seth apparatus.