JPS626373A - Vector control system - Google Patents

Abstract

PURPOSE:To attain the application of a vector processing at a high speed in a wider range of operations by converting array data which are continuous in order of rows and columns into an adverse array (columns and rows). CONSTITUTION:A multiplexer C3 contains a table showing the correspondence between the input order of vector elements and the storing positions of these elements in a work vector register. The next column of the table is referred to every time the vector element is read out of a main storage M1. Then the storing numbers of the vector elements set when they are converted into the order of the column direction are sent to a distributor D1. The distributor D1 stores a single vector element in its storing position of a work vector register V1 in response to an indication given from a signal line l12. The contents of the register V1 are written to a designated vector register through a signal line l13 and a distributor D2 after all data are sent to the register V1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a control method for a program-controlled digital computer, particularly a digital computer suitable for executing vector operations at high speed (hereinafter referred to as a vector processor).

[Background of the invention]

Vector processors have been devised for high-speed calculation layers such as large matrix calculations that frequently occur in scientific and technical calculations. A vector processor can perform vector processing such as the one shown in the following FORTRAN statement at high speed.

DOloJ-1,N DO1Q　A-1,N 1o C' (L, J) - C (L, J) + A (↓.

J) * B (J, ↓) ・・・・・・(
1) In other words, with A(L, J) as vector A, B(J, shi) as vector B, and C(L, J) as vector C, perform calculations for each vector element and store the results in vector C. do. A vector processor can process such operations between vector elements at high speed using vector processing techniques. However, with conventional vector processors, Hitachi Review, No. 8, VOL, 65 (
Table 2 on page 16 of the document entitled "Supercomputer HITACS-8jo Array Processor System 1" by Toshihiko Odaka and Shigeo Nagashima et al. (1983).
As in the example shown in FIG. 5, the array (matrix data developed on a storage device) that can be vectorized is limited to one dimension (for example, A(A), etc.). That is, in equation (1), if arrays A, B, and C are stored in main memory in row order, vector elements are stored in main memory address order as A (' + 1) l A (' + 2 )
...They are arranged like A(1,N). However, when array B is multiplied by array A, array B becomes B(1,1),
The order of B(2,1)... (referred to as column order) is used for calculations. However, on the main memory, array B is arranged in row order.

Therefore, even if you try to read vector B stored in main memory and store it in another storage device that can be read at high speed and perform vector operations using this, the necessary vector elements will be stored discontinuously. It was impossible because For this reason, operations such as (()) were performed by reading each element of array B one by one by issuing a command. That is, vector processing means could not be used.

[Purpose of the invention]

An object of the present invention is to perform a conversion process in a vector processor in which data arranged in the main memory in the order of rows or columns of a Luxru matrix is successively arranged in the opposite arrangement (in the order of columns or rows). The object of the present invention is to provide a vector control method including the following.

[Summary of the invention]

Reads the row-wise ordered array (column-wise ordered array) of a certain matrix from the main memory, converts the order according to the information indicating the correspondence between the position in the array prepared according to the type of matrix and the position after conversion, and arranges it in the column-wise ordered array. Create (row-direction ordered array).

[Embodiments of the invention]

FIG. 4 shows a matrix with N rows and M columns. Each square represents one vector element. When stored in the main memory, they are stored in row order.

In the following embodiments, calculations are performed on triangular vectors surrounded by dotted lines.

Matrix B is stored in the main memory in the arrangement shown on the left side of FIG. In the present invention, this is read out in address order and converted to create the column-wise array shown on the right side of Figure 1.
Perform vector operations using this array.

FIG. 3 shows an embodiment of the present invention. Vector register V
Ro ”= V Rn-t has 256 columns from 0 to 255, and each column can store one vector element.
The contents of the columns are read out one by one in each calculation cycle. In this vector register VR, an array used in an operation is stored prior to the operation, and an array resulting from the operation is temporarily stored before being transferred to the main memory. In FIG. 3, register R1 is an instruction register and is divided into four fields. The OP field indicates an instruction code, which is sent to the arithmetic control unit C1 via the signal line 11 to control execution of the instruction.

The L field specifies the vector register number in which the result vector is stored, and is input to the distributor D2 through the signal line L2, and in D2, the data of the work vector register V1 input from the signal line 114 is used as the result vector, and the vector register is V Ra = V Ra is used to control which register of VR knee 1 is stored. The j field specifies the number of the scalar register 5Ra=SR□-1 in which the first address of the array in the main memory M1 is stored, and is input to the selector S1 by the signal 11A15, and the scalar register SRo''-S Rn-+ It is used to select which register in the list.The selected contents are placed on the signal @J-6.The 4th field indicates the number of the scalar register 5Ro=SRn-+ in which the array length is stored. specified, is input to selector S2 by signal !!14,
It is used to select which register among the scalar registers S Ro''-S Rn -+.The selected contents are placed on the signal line 17.Register R3 is a register that holds the array length; Register R2 is a register that holds the address of the array on main memory M1, arithmetic unit C2 is an arithmetic unit that calculates addresses, etc., signal @J, 8 is a data line carrying the data of register R3, and signal I! ' 9 is a data line carrying the data of the register R2, a signal [210 is an address line that sends the result of the arithmetic unit C2 to the main memory M1, and a signal line 111 is a line that transfers the contents of the main memory M1 to the distributor D1 for address calculation. The data line sent to the multiplexer C3 and the address calculation multiplexer C3 are multiplexers that calculate where in the work vector register V1 the vector element read from the main memory M1 is stored.This multiplexer is shown in FIG. 2, for example. Like a 4x4 matrix, the element numbers of the work vector register v1 to be stored are held in order.The signal line 112 transmits the element numbers of the work vector register v1 to be stored to the distributor D1.
The distributor D1 is a distributor that stores the vector elements in the work vector register V1 according to the multiplexer C3.The work vector register V1 is a through vector register that temporarily holds the vector elements of the main memory M1, and the signal IjI215. c. Work vector register V
This is a data line that transmits the contents of 1 to the distributor D2.

The arithmetic unit C4 performs arithmetic operations between vector elements.

Next, this operation will be explained in detail. In this example, a row-wise sequential array B of 4 rows and 4 columns of triangular vectors is read out from the main memory and converted into a column-wise sequential array. Scalar register S Ro ”-
The first address of array B to be read out is stored in one of S un -1, and the value indicating the length of the array is stored in the other one.

When an instruction specifying the execution of this operation is input to the instruction register R1, the contents of each field of OP e L= / * ' are sent to the arithmetic control unit C1 and the distribution unit through signals 1j[fl, J2, 23, and 24, respectively. device D2, selectors S1 and S2. distributor D2, selector S1,
S2 sets the distribution route and the selection route, respectively, as indicated by 'tit'. The arithmetic control unit C1 sends a read or write instruction to a necessary vector register or scalar register using a signal 11Ai5. At the same time, multiplexer C3 for address calculation
give instructions for calculation. Accordingly, the contents are read from the scalar register designated by j, 4 to registers R2, R5 through signal $1!26.27. First, the contents of the register R3 are input to the address calculation multiplexer C3 through the signal @113, the arithmetic unit C2, the signal line J-10, and the signal 1i[jll.

The address calculation multiplexer C3 converts the storage position of the vector element in the work vector register V1 based on the contents, and passes the signal 5J-12 to the distributor D1.
send instructions to. The multiplexer C3 is provided with tables that indicate the correspondence between the input order of vector elements and the storage positions in the work vector register, which differ depending on the type of matrix (size, full matrix, triangular, etc.). The example shown in FIG. 2 is a triangular vector with 4 rows and 4 columns, and the array length is 10. FIG. 5 shows another table, which is for a full matrix with 4 rows and 4 columns, and the array length is 16. Now, since an array length of 10 is given from the arithmetic unit C2, the table shown in FIG. 2 is selected.

Every time a vector element is read out from the main memory M1, the next column of the table is referred to and the storage number when converted into column order is sent to the distributor D1. Next, the contents of register R2 are signal! It is input to the computing unit C2 through 119 and becomes the signal as it is! 1110 to the main memory M1. In the main memory M1, data vectors are sequentially sent from the corresponding address to the distributor D1 through the signal fgJ-11. The distributor D1 stores one vector element in the storage position of the work vector register v1 according to the instruction input from the signal 1s212. After all the data in the corresponding main memory M1 is sent to the work register v1, the signal Ij
! 113, the contents of the work vector register v1 are written to the vector register specified by L through the distributor D2.

In this way, array B converted in column direction is obtained on the vector register VR as shown in FIG.

Vector operations between the row-direction array of vectors A read separately from the main memory M1 and the column-direction array of vector B obtained in this way are performed in the same vector register VR that stores the respective arrays. It is sufficient to read out the columns in the order of column numbers and apply them to different inputs of the arithmetic unit C4 for calculation. In other words, calculations can be performed using high-speed vector processing based only on hardware control.

In the present invention, conversion from row-direction sequential array to column-direction sequential array is performed by hardware processing, so it is fast. Note that a similar method can be used when converting a column-direction sequential arrangement into a row-direction sequential arrangement.

〔Effect of the invention〕

According to the present invention, it is possible to convert array data that exists consecutively in the order of rows or columns to the reverse array (in the order of columns or rows), so high-speed vector processing can be applied to wider calculations. It becomes possible to apply.

[Brief explanation of drawings]

FIG. 1 shows an example of the processing performed by the present invention.
This figure shows an outline of an address calculation multiplexer, and FIG. 6 shows an embodiment of the present invention. Fourth
The figure shows an example of a matrix, and FIG. 5 shows an example of a change table. R1 is an instruction register, R2 is an address register, R3 is a register that holds the array length, C1 is an arithmetic control unit,
C2 is an arithmetic unit, C3 is a multiplexer for address calculation,
Ml is main memory, vl is work vector register, VRO
~V Rn-+ 'i vector register, S Ro =
S Rn-+ is a scalar register. Representative Patent Attorney Katsuo Ogawa - Figure 1 Figure 2 Figure 3 Figure 4 Prisoner 1

Claims (1)

[Claims] In an electronic computer system where a row-wise (column-wise) array of matrices is stored in main memory and is read out to perform vector processing, there is a difference between the row-wise and column-wise arrays according to the type of matrix. Conversion information indicating the correspondence of positions is prepared, and the row-order (column-order) array read from the main memory is converted into a column-order (row-direction) array using the conversion information. A vector control method characterized by performing vector processing using arrays.