JPH03188422A - Production of thin-film transistor array - Google Patents
Production of thin-film transistor arrayInfo
- Publication number
- JPH03188422A JPH03188422A JP1327733A JP32773389A JPH03188422A JP H03188422 A JPH03188422 A JP H03188422A JP 1327733 A JP1327733 A JP 1327733A JP 32773389 A JP32773389 A JP 32773389A JP H03188422 A JPH03188422 A JP H03188422A
- Authority
- JP
- Japan
- Prior art keywords
- tantalum
- electrodes
- electrode
- semiconductor layer
- transistor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052715 tantalum Inorganic materials 0.000 claims abstract description 27
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims abstract description 27
- 238000007743 anodising Methods 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011521 glass Substances 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 abstract description 9
- 238000002834 transmittance Methods 0.000 abstract description 9
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 229910004205 SiNX Inorganic materials 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えば液晶表示装置のスイッチング素子等に
用いられるfil!)ランジスタアレイに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applicable to fil! used, for example, in switching elements of liquid crystal display devices. ) relates to transistor arrays.
液晶表示素子等の駆動に用いられる薄膜トランジスタは
、ラップトツブパソコン、ワードプロセッサ等の液晶表
示のOA機器、液晶テレビの普及に伴い、低コスト化、
低欠陥化、大面積化、高密度化へ向けて、活発な開発が
行われている。Thin film transistors used to drive liquid crystal display elements, etc., have become cheaper and cheaper due to the spread of liquid crystal display office equipment such as laptop computers and word processors, and liquid crystal televisions.
Active development is underway to reduce defects, increase surface area, and increase density.
薄膜トランジスタアレイは、十数刃側の画素を駆動する
為に、ゲート電極及びソース電極をX−Yマトリクス状
に配線する。この為、ゲート電極とソース電極との交差
部でのショートが大きな問題となる。In the thin film transistor array, gate electrodes and source electrodes are wired in an XY matrix to drive pixels on the edge side. Therefore, a short circuit at the intersection between the gate electrode and the source electrode becomes a major problem.
また、液晶表示装置の駆動に余裕を与える為に、付加容
量用電極を設けた構造の薄膜トランジスタが考えられて
いるが、付加容量用電極と配線電極、画素用電極との交
差部は、−船釣にはプラズマ−化学的気相蒸着法(以下
P−CVD法という)による5iNT4膜あるいはSt
O,膜−層のみである、この場合、P−CVD法による
チャンバー内のゴミや、異常成長によるピンホールが、
ショートの原因となり、欠陥を引き起こす。In addition, in order to provide a margin for driving a liquid crystal display device, a thin film transistor having a structure in which an additional capacitance electrode is provided has been considered, but the intersection of the additional capacitance electrode, wiring electrode, and pixel electrode is For fishing, 5iNT4 film or St
In this case, dust in the chamber due to the P-CVD method and pinholes due to abnormal growth are
This can cause short circuits and lead to defects.
そこで本発明者らは特願平1−289186号に第2図
に示すような、ゲート電極をパターニングした後、アレ
イ全面にタンタルを成膜し、この膜を陽極酸化すること
によりピンホールの無い透明絶縁膜を形成し、SiNx
膜あるいはSiO□膜との二層構造の絶縁膜にすること
により電極間のショート等による欠陥を防止する構造を
提唱した。Therefore, the inventors of the present invention disclosed in Japanese Patent Application No. 1-289186 that after patterning a gate electrode as shown in FIG. A transparent insulating film is formed, and SiNx
They proposed a structure that prevents defects due to short circuits between electrodes by forming an insulating film with a two-layer structure with a film or a SiO□ film.
しかし、従来の付加容量用透明電極及び画素用透明電極
間の絶縁膜に陽極酸化タンタルを用いる構造の薄膜トラ
ンジスタアレイの製造方法においては、ゲート電極と陽
極酸化後に絶縁層となるタンタル膜を形成したガラス基
板の非画素部分のタンタル膜に電源を接続し、画素部分
を溶液に浸し、陽極酸化を行なっていた。しかし、陽極
酸化の際、溶液界面近傍のタンタルが先に完全に陽極酸
化してしまい、その部分が絶縁状態となり、界面近傍よ
り溶液側では電流の供給が止まるため、完全にタンタル
を陽極酸化するのは困難であり、第4図に示すように、
未酸化のタンタル13が薄くムラとなって残り、この為
、画素の透過率を著しく低くしていた。However, in the conventional manufacturing method of a thin film transistor array that uses anodized tantalum as an insulating film between transparent electrodes for additional capacitance and transparent electrodes for pixels, a tantalum film that becomes an insulating layer after anodization is formed on the gate electrode. A power source was connected to the tantalum film on the non-pixel portion of the substrate, and the pixel portion was immersed in a solution to perform anodic oxidation. However, during anodic oxidation, the tantalum near the solution interface is completely anodized first, and that part becomes insulated, and the supply of current stops on the solution side near the interface, so tantalum cannot be completely anodized. As shown in Figure 4, it is difficult to
Unoxidized tantalum 13 remained thin and uneven, which significantly lowered the transmittance of the pixel.
本発明は、上記の課題に鑑み、透過率の高い陽極酸化タ
ンタル膜を用いた薄膜トランジスタアレイの製造方法を
提供する目的でなされたものである。In view of the above-mentioned problems, the present invention has been made for the purpose of providing a method for manufacturing a thin film transistor array using an anodized tantalum film having high transmittance.
すなわち、本発明は、付加容量用透明電極及び画素用透
明電極間に陽極酸化タンタル膜から成る絶縁膜を介した
薄膜トランジスタアレイの製造方法に於て、
(a)ガラス基板上にタンタルでゲート電極とゲート電
極を共通に結線した補助電極を形成する工程、
(b)前記ゲート電極及び補助電極を形成したガラス基
板上全面にタンタル膜を形成する工程、(c)前記補助
電極上のタンタル膜を陽極酸化用電極とし、タンタルを
陽極酸化し絶縁膜とする工程、
少な(とも以上の工程を具備する薄膜トランジスタアレ
イの製造方法により上記の課題を解決した。That is, the present invention provides a method for manufacturing a thin film transistor array in which an insulating film made of an anodized tantalum film is interposed between a transparent electrode for an additional capacitor and a transparent electrode for a pixel. (b) forming a tantalum film on the entire surface of the glass substrate on which the gate electrode and the auxiliary electrode are formed; (c) using the tantalum film on the auxiliary electrode as an anode; The above problems were solved by a method for manufacturing a thin film transistor array that includes the steps of using an oxidizing electrode and anodizing tantalum to form an insulating film.
本発明ではゲート電極とゲート電極と結線した補助電極
上のタンタルを陽極酸化用電極として用いるので、電流
が絶縁膜形成部分にゲート電極を通しまんべんなく流れ
るため、絶縁層の陽極酸化が完全に行える。よって、画
素部分の透過率が高く、且つ、ショート等による欠陥の
非常に少ない薄膜トランジスタアレイが製造できる。In the present invention, since the tantalum on the gate electrode and the auxiliary electrode connected to the gate electrode is used as the anodizing electrode, the current flows evenly through the gate electrode in the insulating film formation area, so that the insulating layer can be completely anodized. Therefore, it is possible to manufacture a thin film transistor array with high transmittance in the pixel portion and with very few defects such as short circuits.
本発明の実施例を図面を用いて詳述する。第1図は本発
明による薄膜トランジスタアレイのゲート電極パターン
を示す平面図であり、第2図は薄膜トランジスタアレイ
の構成例を示す断面図、第3図は従来法による薄膜トラ
ンジスタアレイのゲート電極パターンを示す平面図であ
る。Embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a plan view showing a gate electrode pattern of a thin film transistor array according to the present invention, FIG. 2 is a cross-sectional view showing a configuration example of the thin film transistor array, and FIG. 3 is a plan view showing a gate electrode pattern of a thin film transistor array according to a conventional method. It is a diagram.
ガラス基板1上にITOによる付加容量用透明電極2(
厚さ1500人)をパターニングした後、スパッタ法に
よりタンタルを2000人成膜しゲート電極3に加工す
る。このときゲート電極パターンは第3図に示す独立し
たものではなく、第1図に示す各々のゲート電極を共通
結線した補助電極4を有するパターンとする0次に同様
の方法にてタンタルを1000人成膜する。A transparent electrode 2 for additional capacitance made of ITO is placed on a glass substrate 1 (
After patterning to a thickness of 1,500 layers, a tantalum film of 2,000 layers is formed by sputtering and processed into the gate electrode 3. At this time, the gate electrode pattern is not the independent one shown in FIG. 3, but a pattern having an auxiliary electrode 4 that connects each gate electrode in common as shown in FIG. Form a film.
前記補助電極上のタンクル膜に電源を接続し、陽極酸化
用電極とし、0.1重量%クエン酸溶液中で180Vま
で化成することにより、全面透明な陽極酸化タンタルで
ある第一絶縁膜5を形成した。なお、この値より低い化
成電圧でも陽極酸化は充分行えるが、未酸化のタンタル
が残りムラとなり、透過率を低下させるため、少し過剰
気味にすると良い、前記の電圧では、2000人の膜厚
のゲート電極3及び補助電極4表面も一部酸化されるが
、完全に酸化されることはない。A power source is connected to the tankle film on the auxiliary electrode, used as an anodizing electrode, and anodized to 180 V in a 0.1% by weight citric acid solution to form a first insulating film 5 made of anodized tantalum that is completely transparent. Formed. Although anodic oxidation can be performed satisfactorily at an anodizing voltage lower than this value, unoxidized tantalum remains and causes unevenness, reducing the transmittance. The surfaces of the gate electrode 3 and the auxiliary electrode 4 are also partially oxidized, but not completely.
次にP−CVD法により、第二絶縁膜6であるSiN、
を3000人、アモルファスシリコン膜による半導体層
7を2000人、リンドープアモルファスシリコンによ
るオーミック接触用半導体層8を500人連続的に成膜
した0次に半導体層7及びオーミック接触用半導体層8
を島状に加工し、さらに、ITOを1500人積層し、
画素用透明電極9を形成し、Crを2000人積層し、
ドレイン電極lO及びソース電極11を作製した。最後
に、P−CVD法によりパッシベーション膜12である
SiNxを3000人成膜して、薄膜トランジスタアレ
イを完成した。Next, by P-CVD method, SiN, which is the second insulating film 6,
3,000 people formed the semiconductor layer 7 made of amorphous silicon film, 2000 people formed the semiconductor layer 7 made of an amorphous silicon film, and 500 people formed the semiconductor layer 8 for ohmic contact made of phosphorous-doped amorphous silicon.
processed into an island shape, and then laminated with 1500 layers of ITO.
A transparent electrode 9 for the pixel is formed, 2000 Cr layers are laminated,
A drain electrode IO and a source electrode 11 were produced. Finally, 3,000 SiNx layers, which are the passivation film 12, were deposited using the P-CVD method to complete the thin film transistor array.
なお、補助電極はパネル化後に切り離す。Note that the auxiliary electrodes are separated after the panel is formed.
前記実施例の同様な製造方法によりゲート電極パターン
を形成する。このときのゲートパターンは第3図に示す
一本一本独立したパターンである。A gate electrode pattern is formed by a manufacturing method similar to that of the previous embodiment. The gate pattern at this time is an independent pattern one by one as shown in FIG.
次に、タンタルをスパッタ法により1000人成膜する
。この膜に電極を接続し、陽極酸化を行うと、溶液界面
近傍は完全に酸化され透明になるが、界面近傍より溶液
側では電流が行き届かなくなり未酸化のタンタルがムラ
となって残る。また、電流を流すために化成電圧を上げ
ることは、この場合界面近傍で、絶縁破壊が生じるため
好ましくない。Next, 1000 tantalum films are formed by sputtering. When an electrode is connected to this film and anodic oxidation is performed, the area near the solution interface is completely oxidized and becomes transparent, but the current does not reach the solution side near the interface and unoxidized tantalum remains in spots. In addition, it is not preferable to increase the formation voltage in order to cause current to flow because dielectric breakdown occurs near the interface in this case.
この後実施例と同様な製造工程で薄膜トランジスタアレ
イを完成させても第4図の様になるため分光器による可
視領域での画素部分の透過率が加工前のガラス基板の透
過率を100%としたものに対し、40%と低くなる。Even if the thin film transistor array is then completed using the same manufacturing process as in the example, it will look like the one shown in Figure 4, so the transmittance of the pixel portion in the visible region measured by a spectrometer will be 100% of the transmittance of the glass substrate before processing. This is 40% lower than that of the previous year.
本発明により、従来の薄膜トランジスタアレイは分光器
による可視領域での画素部分の透過率が加工前のガラス
基板を100%としたものに対し、40%であったもの
に比べ、90%と非常に高い薄膜トランジスタアレイが
作製でき、画質が向上した。又、ショート等による欠陥
が非常に少なく歩留まりが向上した。Thanks to the present invention, the transmittance of the pixel portion of the conventional thin film transistor array in the visible region measured by a spectrometer is 90%, compared to 40% when the unprocessed glass substrate is 100%. A high-performance thin film transistor array can be fabricated, and image quality has improved. In addition, there were very few defects due to short circuits, etc., and the yield was improved.
第1図は、本発明の薄膜トランジスタアレイのゲート電
極と補助電極パターンの一実施例を示す平面図であり、
第2図は、本発明の薄膜トランジスタアレイの構成の一
実施例を示す断面図である。
第3図は、従来の薄膜トランジスタアレイのゲート電極
パターンの一例を示す平面図であり、第4図は、従来薄
膜トランジスタアレイの構成の一例を示す断面図である
。
1・・・ガラス基板
2・・・付加容量用透明電極
3・・・ゲート電極
4・・・補助電極
5・・・第一絶縁膜
6・・・第二絶縁膜
7・・・半導体層
8・・・オーミック接触用半導体層
9・・・画素用透明電極
10・・・ドレイン電極
11・・・ソース電極
12・・・パッシベーション膜
13・・・未酸化のタンタル
特 許 出 願 人
凸版印刷株式会社
代表者 鈴木和夫
第2図FIG. 1 is a plan view showing an example of a gate electrode and auxiliary electrode pattern of a thin film transistor array of the present invention;
FIG. 2 is a sectional view showing one embodiment of the structure of a thin film transistor array according to the present invention. FIG. 3 is a plan view showing an example of a gate electrode pattern of a conventional thin film transistor array, and FIG. 4 is a sectional view showing an example of the configuration of a conventional thin film transistor array. 1...Glass substrate 2...Transparent electrode for additional capacitance 3...Gate electrode 4...Auxiliary electrode 5...First insulating film 6...Second insulating film 7...Semiconductor layer 8 ...Semiconductor layer for ohmic contact 9...Transparent electrode for pixel 10...Drain electrode 11...Source electrode 12...Passivation film 13...Unoxidized tantalum Patent application Hitotoppan Printing Co., Ltd. Company representative Kazuo Suzuki Figure 2
Claims (1)
酸化タンタル膜から成る絶縁膜を介した薄膜トランジス
タアレイの製造方法に於て、 (a)ガラス基板上にタンタルでゲート電極とゲート電
極を共通に結線した補助電極を形成する工程、 (b)前記ゲート電極及び補助電極を形成したガラス基
板上全面にタンタル膜を形成する工程、(c)前記補助
電極上のタンタル膜を陽極酸化用電極とし、タンタルを
陽極酸化し絶縁膜とする工程、 少なくとも以上の工程を具備する薄膜トランジスタアレ
イの製造方法。(1) In the method for manufacturing a thin film transistor array in which an insulating film made of an anodized tantalum film is interposed between a transparent electrode for additional capacitance and a transparent electrode for pixels, (a) gate electrodes are formed using tantalum on a glass substrate; (b) forming a tantalum film on the entire surface of the glass substrate on which the gate electrode and the auxiliary electrode are formed; (c) forming a tantalum film on the auxiliary electrode as an anodizing electrode; and a step of anodizing tantalum to form an insulating film, a method for manufacturing a thin film transistor array comprising at least the above steps.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1327733A JPH03188422A (en) | 1989-12-18 | 1989-12-18 | Production of thin-film transistor array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1327733A JPH03188422A (en) | 1989-12-18 | 1989-12-18 | Production of thin-film transistor array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03188422A true JPH03188422A (en) | 1991-08-16 |
Family
ID=18202378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1327733A Pending JPH03188422A (en) | 1989-12-18 | 1989-12-18 | Production of thin-film transistor array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03188422A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0695142A (en) * | 1992-09-10 | 1994-04-08 | Rohm Co Ltd | Liquid crystal display device |
-
1989
- 1989-12-18 JP JP1327733A patent/JPH03188422A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0695142A (en) * | 1992-09-10 | 1994-04-08 | Rohm Co Ltd | Liquid crystal display device |
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