JPH09203912A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lower the occupying area rate of an additive capacitor part within one pixel by using the oxide of tantalum (Ta) having a large dielectric constant in the additive capacitor part. SOLUTION: An SiO2 ground surface film 20 for protecting a transparent glass substrate 14 is deposited on the glass substrate. Next, metal Ta is deposited thereon by a sputtering method and is patterned to desired gate wirings by a photoetching method. An anodically oxidized film of Ta (Ta2 O5 ) is formed to completely cover the gate wirings of Ta. Namely, the Ta2 O5 film 24 is a gate insulating film of a first layer of a TFT on the Ta gate electrode 22 of the a-SiTFT and is the dielectric film of the additive capacitor on the adjacent Ta gate wirings 23. Next, a transparent electrode of ITO is deposited by a sputtering method and pixel electrode patterns 9 are formed by a photoetching method using an aq. HC1 soln. At this time, the pixel electrodes 9 are patterned so as to overlap on the adjacent Ta gate wirings 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a structure capable of increasing an additional capacitance without reducing an aperture ratio of a pixel.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. 59-119329 and Japanese Patent Application Laid-Open No. 60-8 are known as prior arts for providing an additional capacitance between a pixel corresponding to a certain gate line and a gate line at the next stage.
7393, JP-A-62-152157 and the like.

FIG. 2 is a diagram showing one pixel of an active matrix liquid crystal display panel having an additional capacitance according to the prior art, (a) is a plan view thereof, (b) is a sectional view thereof, and (c) is equivalent. It is a circuit diagram. The thin film transistor (hereinafter abbreviated as TFT) 4 for selecting one pixel is shown in FIG.
As shown in (b), the gate line 2, the gate insulating film 11,
It is composed of an a-Si: H (i), a-Si: H (n ⁺ ) layer 15, a signal line 1, a source electrode 5, and a pixel electrode 9. Further, the additional capacitance (7 in FIG. 2C) is formed by overlapping the pixel electrode 9 and the gate line 3 of the next stage as shown in FIG. 2A. As shown in FIG. 2B, the same material as the gate insulating film 11 is used for the dielectric layer as it is. here,
Reference numeral 13 is a low resistance metal wiring for reducing the resistance of the gate wiring, and 12 is a protective film.

The purpose of providing the additional capacitance 7 will be outlined below. Since there is a parasitic capacitance (6 in FIG. 2A) due to the overlapping portion of the gate line and the source electrode 5 in the TFT, the scanning pulse of the gate line 2 leaks through the parasitic capacitance 6 and the pixel electrode 9 The potential Vs of is changed. Since the leak voltage component is a pulse having a duty ratio (1 / the number of gate lines) of the scanning pulse and an asymmetric pulse in the positive and negative directions, the leak voltage component has a form in which a DC component is added to the pixel potential. This DC component deteriorates image sticking and afterimage characteristics of the liquid crystal panel.

Further, when the OFF resistance of the TFT is lowered, or when the specific resistance value of the liquid crystal is reduced, the pixel capacitance formed by the pixel electrode 9 and the counter electrode 17 via the liquid crystal (FIG. 2C). 16) is not sufficiently large, there arises a problem that the pixel potential Vs once written via the TFT 4 cannot be held within the period until the next writing. This causes image defects such as black spots, white spots, and black spots on the liquid crystal panel. At this time, additional capacity 7
Has the effect of increasing the pixel capacity 16, so that the above defects in image quality are less likely to occur.

As described above, setting the additional capacitor is an effective method for improving the image quality in an active matrix liquid crystal panel in which pixels are selected by TFTs.

As the additional capacitance, in addition to the one using the gate line as shown in FIG. 2 as one electrode of the additional capacitance, one of the additional capacitances is provided separately from the gate line as shown in JP-A-62-148929. There is also an electrode provided with, and both of them perform the same function in that they hold the signal voltage of the pixel electrode.

[0008]

In the above prior art, as the dielectric film of the additional capacitance, as shown in FIG.
The same material as the gate insulating film 11 of T is used. a
When using -SiTFT, SiN is usually used as a gate insulating film. SiN gate insulating film thickness 0.32
μm approximately, when the relative dielectric constant is 6.9, the area occupied by the additional capacitor becomes 5000μm ² / 1pF. For example, if the pixel area is 200 × 250 μm ² , the additional capacitance of 1 pF occupies 10% of the area of one pixel. However, in order to accelerate the response characteristic of the liquid crystal cell and improve the viewing angle characteristic, it is necessary to narrow the gap interval of the liquid crystal cell as much as possible, and it is necessary to increase the additional capacitance accordingly. I got the knowledge. As a result of various studies by the inventors of the present application, it was found that the required additional capacitance is about 2 pF to 3 pF at a gap interval of about 5 μm. In this case, since the occupation ratio of the additional capacitance in one pixel reaches 20% to 30%, it becomes difficult to absorb the additional capacitance in the black matrix region in one pixel. Indicates a light-shielded region outside the red, green, and blue color filter patterns provided on the counter electrode substrate side in one-to-one correspondence with ITO (Indium Tin Oxide) pixel electrodes. Normally, the additional capacitance of about 10% occupied area in one pixel is arranged so as to fit within this black matrix region,
It is possible to prevent the aperture ratio from decreasing,
When the area occupied by the additional capacitance is 20 to 30%, it becomes difficult to dispose the additional capacitance without lowering the aperture ratio per pixel.

An object of the present invention is to provide a liquid crystal display panel in which the occupied area ratio does not increase even if the size of the additional capacitance is increased, and therefore the aperture ratio is not lowered.

A known example in which the anodic oxide film of one electrode of the additional capacitance is used as the dielectric film of the additional capacitance is disclosed in JP-A-58-58.
There is Japanese Patent Laid-Open No. 93092 (Prior Art 1). However, the above-mentioned Prior Art 1 does not describe the structure of the present invention in which the dielectric film of the additional capacitance is formed of a composite film of a tantalum oxide film and a silicon nitride film.

Japanese Patent Application Laid-Open No. 1-217325 (Prior Art 2) is a prior application of a structure in which a dielectric film for additional capacitance is formed of a composite film of a tantalum oxide film and a silicon nitride film.
It was also found that there is JP-A-1-267618 (Prior Art 3). However, in the above-mentioned Prior Art 2 and Prior Art 3, there is no description of the constitution of the present invention in which the signal electrode is composed of a multi-layered conductive film.

Therefore, the techniques disclosed in the prior art 2 and the prior art 3 have a problem that the signal electrode and the source and drain electrodes are disconnected due to the step formed by the anodic oxide film of the gate electrode and the gate line.

[0013]

The above object can be achieved by using a material containing at least a metal oxide containing Ta as a main component as the dielectric film of the overlapping portion which constitutes the above-mentioned additional capacitance.

That is, a first substrate having a pixel formed of a thin film transistor, an additional capacitor and a pixel electrode in a region formed by two adjacent gate lines and two adjacent signal electrodes, a counter substrate and a liquid crystal. A liquid crystal display device in which the gate line and one electrode of the additional capacitance are provided on the first substrate by a metal film containing tantalum as a main component, and one of the gate line and the additional capacitance is provided. A tantalum oxide film is provided on the surface of the electrode, a silicon nitride film is provided on the gate line and one electrode of the additional capacitor, a semiconductor film is provided on the silicon nitride film, and a channel is provided on the semiconductor film. A protective film is provided, a semiconductor film doped with impurities is provided on the semiconductor film and the channel protective film, and a source electrode and the signal electrode are provided on the semiconductor film doped with impurities. A pixel electrode made of a bright conductive film and electrically connected to the source electrode is provided, and the other electrode that overlaps with the one electrode is provided by sandwiching the tantalum oxide film and the silicon nitride film therebetween. The liquid crystal display device is characterized in that the other electrode of the additional capacitor, which constitutes a capacitor, is electrically connected to the pixel electrode, and the signal electrode is formed of a multilayer conductive film.

The tantalum oxide film is a liquid crystal display device characterized in that it is a self-oxidation film formed by oxidizing the surfaces of the gate line and one electrode of the additional capacitor.

Further, in the liquid crystal display device, the tantalum oxide film is an oxide film formed by anodizing the surfaces of the gate line and one electrode of the additional capacitor.

Further, the above-mentioned signal electrode is a liquid crystal display device characterized by comprising a multilayer film of a transparent conductive film and a metal film.

Further, the above-mentioned signal electrode is a liquid crystal display device characterized by comprising a multilayer film of aluminum and a conductive film different from aluminum.

As a more specific example, FIGS.
This can be achieved by providing an additional capacitor as shown in the sectional view of the main part of one pixel portion of the liquid crystal display in FIG. 4, FIG. 8, FIG. 9 or FIG.

That is, the additional capacitance of the conventional example shown by 7 in FIG. 2A is made of Si, which is a gate insulating film of an a-Si TFT, as a dielectric film, as is apparent from the sectional view of FIG. 2B. Although the nitride or the oxide 11 is used, the Ta-based metal oxide having a larger relative dielectric constant is used as the main dielectric film in the additional capacitance of the present invention. Examples of the Ta-based metal oxide include metal T as a gate electrode and gate wiring material.
It is possible to use a Ta ₂ O ₅ film obtained by using a and anodizing this.

In the embodiment shown in FIG. 1, the additional capacitance is composed of the Ta gate line 23 / the oxide (Ta ₂ O ₅ ) 24 of Ta / pixel electrode 9. Further, in the embodiment shown in FIG. 3, the additional capacitance is the oxide (Ta) of the Ta gate line 23 / Ta.
₂ O ₅ ) 24 / metal electrode 2 electrically connected to the pixel electrode
6. In addition, in the embodiment shown in FIG. 4, the additional capacitance is the oxide (Ta ₂ O) of the Ta gate line 23 / Ta.
₅ ) 24 / Very thin Si nitride or oxide 21 /
It is composed of the pixel electrode 9.

The relative permittivity of Ta oxide (Ta ₂ O ₅ ) is about 26, and the relative permittivity of the SiN film is 6.9, 3.8.
This is about 6.2 times the relative dielectric constant 4.2 of the SiO ₂ film.

In the liquid crystal display panel with the additional capacitance, the SiN film of the plasma CVD method having a relatively large dielectric constant is used as the gate insulating film of the a-SiTFT for pixel selection. In order to obtain an additional capacitance of 3 pF with a film thickness of 0.32 μm by using the same for the additional capacitance section, 1500 μm ² (one pixel 200 × 250 μm ²
In this case, the occupation area of 30%) is required. Here, if the dielectric film is replaced with a Ta ₂ O ₅ film having the same film thickness, the occupied area of the additional capacitance can be reduced to 1 / 3.8.
At this time, since the additional capacitance of 3 pF is 10% or less of the area of one pixel, it is possible to arrange the additional capacitance pattern so as to be absorbed by the black matrix region in one pixel. Therefore, it is possible to prevent the decrease in the brightness of the liquid crystal display panel due to the decrease in the aperture ratio of one pixel.

The Ta ₂ O ₅ film is usually obtained by using metal Ta as a gate electrode and anodizing it. The anodic oxidation voltage and the film thickness of the formed Ta ₂ O ₅ anodic oxide film have a linear relationship as shown in FIG. 7. Ta ₂
The O ₅ anodic oxide film is a film having excellent withstand voltage and insulating properties. This is because the anodic oxidation reaction selectively progresses from the electrically leaky portion of the Ta ₂ O ₅ film (called the self-healing effect). Therefore, the Ta ₂ O ₅ anodic oxide film can be used not only in the additional capacitance portion but also in the intersection portion of the gate wiring and the signal line and the gate insulating film portion of the TFT, which is preferable. This makes it possible to significantly reduce the electrical short circuit between the gate wiring and the signal line and the electrical short circuit between the gate electrode and the source / drain electrodes.

Further, when only the anodized Ta ₂ O ₅ film is used as the gate insulating film of the a-Si TFT and the a-Si: H (i) layer is directly deposited on the Ta ₂ O ₅ , the effective TFT is obtained. Mobility is significantly reduced. Therefore, as the gate insulating film of the a-SiTFT, the second layer of the gate insulating film made of the SiN film deposited by the plasma CVD method is stacked on the first layer of Ta ₂ O ₅ gate insulating film. It is desirable to use a layer film.

Also, at the intersection of the gate wiring and the signal line, a Ta ₂ O ₅ / SiN bilayer film is formed in order to reduce the capacitance between the gate line and the signal line and to reduce the short circuit rate between the lines. It is desirable to use.

The Ta ₂ O ₅ anodic oxide film has a thickness of 32.
If the thickness is more than 00Å, the film thickness combined with the gate wiring normally formed to a thickness of about 1800 to 2000Å is 5000Å
This is about the above level, and the probability of step breakage at the signal line crossover portion at the gate line / signal line crossing portion increases.
The film thickness of ₂ O ₅ is preferably 3200 Å or less.

In addition, the Ta ₂ O ₅ film of the additional capacitance portion is 80
If the film thickness is less than 0Å, the leak current increases and the insulation deteriorates. This thin Ta ₂ O ₅ film is SiN or Si
By forming a double layer with the O ₂ film, the leak current can be suppressed. However, reliability deteriorates in terms of a long life as an additional capacity. Therefore, the film thickness of the Ta ₂ O ₅ film is 80
It is desirable to set it to 0Å or more.

In the additional capacitance portion, by setting the optimum film thickness condition as described below, Ta ₂ O ₅ /
A bilayer structuring of SiN or Ta ₂ O ₅ / SiO ₂ can be performed. FIG. 6 shows Ta _{2 on} the dielectric film of the additional capacitance part.
O ₅ / SiN composite film (a) and Ta ₂ O ₅ / SiO ₂
It is the figure which showed the combination of the film thickness when using a composite film (b). 6 (a) and 6 (b), as described above, Ta
It is desirable to select the film thickness of ₂ O ₅ in the range of 800 Å to 3200 Å. When the area is constant, the line segment a ₁ -b ₁ is ₁ pF, the line segment a ₂ -b ₂ is ₂ pF, and the line segment a ₂ -b ₂ is ₂ pF. The portion a ₃ −b ₃ corresponds to the film thickness of the composite film when the additional capacitance of ₃ pF is set.

Line segment a ₁ -of ₁ pF in FIGS. 6 (a) and 6 (b)
The region on the left side of b ₁ is a region in which the capacitance per unit area is larger than the additional capacitance formed by the conventional SiN film.
When a value of 2 pF or more is required as the additional capacitance, the combination of film thicknesses included in the shaded region on the left side of the ₂ pF line segment a ₂ -b ₂ is particularly effective.

From FIG. 6, it is particularly effective that the SiN film thickness of the Ta ₂ O ₅ / SiN composite film (a) is 1000 Å, and that of the Ta ₂ O ₅ / SiO ₂ composite film (b) is S.
It is particularly effective that the iO ₂ film thickness is 600 Å or less.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to embodiments.

Embodiment 1 Example 1 will be described with reference to FIG. Si for protecting the glass substrate on the transparent glass substrate 14
The O ₂ base film 20 is deposited to a film thickness of about 3000Å. Next, metal Ta is sputtered to a film thickness of 3000 Å
Then, a desired gate wiring pattern is formed by a photoetching method. In order to taper the step at the end of the Ta pattern, a dry etching method using a C—Cl—F gas is used for etching. Next, the substrate coated with a photoresist except the portion to be anodized is 0.1% H ₃
When immersed in a PO ₄ aqueous solution and anodized with a platinum electrode as a cathode and a Ta gate wiring pattern as an anode at an anodic oxidation voltage (compound voltage) of 180 V, a Ta gate wiring of about 3000 Å is completely covered. A Ta anodic oxide film (Ta ₂ O ₅ ) having a film thickness is formed. That is, in FIG.
The a ₂ O ₅ film 24 is the Ta gate electrode 22 of the a-Si TFT.
The upper part serves as a gate insulating film of the first layer of the TFT, and the adjacent Ta gate line 23 serves as a dielectric film of additional capacitance.
The formation voltage and the film thickness of the formed Ta ₂ O ₅ film have a linear relationship as shown in FIG. 7, and the gradient is 16.5Å / V.
Therefore, at a formation voltage of 180 V, Ta ₂ O ₅ having a film thickness of 3000 Å can be obtained from FIG. 7. First anodization is 0.5m
Ta ₂ O ₅ having high reliability is obtained by performing constant current formation at a constant current density of A / cm ² and performing constant voltage formation at 180 V (= constant) for 30 minutes from the time when the formation voltage reaches 180 _V.
A film is obtained. Since Ta ₂ O ₅ having a film thickness of 3000 Å is formed, Ta having a film thickness of about 1/3 of that is consumed, so that the Ta gate electrode 22 and the additional capacitance portion 23 of the adjacent Ta gate wiring are The remaining Ta film thickness is about 2000 Å.

Next, an ITO (Indium Tin Oxide) transparent electrode is deposited to a film thickness of 1200Å by a sputtering method, and a pixel electrode pattern 9 is formed by a photoetching method using an HCl-based aqueous solution. At this time, the pixel electrode 9 is patterned so as to overlap the adjacent Ta gate line 23. The area of the overlapping portion was 170 × 25 μm ² and the additional capacitance was 3 pF. Here, the width of the additional capacitance of 25 μm is easily absorbed in the black matrix region of one pixel size of 250 μm (V) × 200 μm (H), and the aperture ratio of one pixel is not lowered.

Next, the SiN gate insulating film (second layer gate insulating film) 21 and a-SiH are formed by the plasma CVD method.
(I) The film 8 and the SiN channel protective film 25 are each formed in three layers.
It is continuously deposited to a film thickness of 000Å, 250Å, 2000Å. Next, the SiN channel protective film 25 is formed by a photoetching method using an HF—NH ₄ F based etching solution.
Is formed.

Then, a-Si: is formed by the plasma CVD method.
The H (n ⁺ ) film thickness is deposited to 400 Å.

Next, a-Si: H (n ⁺ ) 15 and a
-Si: H (i) 8 island pattern is formed. This time,
For the photoresist pattern, a pattern in which the source portion and the drain portion are divided into two is used, and a-Si: H (n ⁺ ),
(I) When the island pattern is formed, the a-Si: H (n ⁺ ) film on the SiN channel protective film 25 is separated between the source and the drain, and the SiN channel protective film pattern 25 is formed.
The a-Si: H (i) film below the SiN channel protective film remains as an etching stopper.

Next, SiN which is the second layer gate insulating film
The ITO pixel electrode 9 and the source electrode 5 are formed on the gate insulating film 21.
A contact hole and a pattern for taking out a terminal of the gate wiring are formed by a photoetching method.

Next, metal Al is deposited to a film thickness of 3000Å, and the signal line pattern 1 and the source electrode pattern 5 are formed by the photoetching method.

Finally, the protective film 12 is formed so as to cover the entire screen area of the TFT substrate, and the TFT substrate for a liquid crystal display panel is completed. A liquid crystal display panel is completed by combining this TFT substrate with an ordinary counter substrate, liquid crystal and the like.

Embodiment 2 FIG. Example 2 will be described with reference to FIG. a-Si: H (n ⁺ ) 15 and a-Si: H
(I) Fabrication is performed in the same manner as in Example 1 up to the 8-island patterning step. However, Ta deposited by the sputtering method
Film thickness of 2700Å and formation voltage of 120V is used. Ta ₂ O ₅ film thickness formed is 2000Å from FIG. 7.
And the remaining film thickness of Ta gate line after formation is about 2000Å
It has become. Further, the pixel electrode pattern 9 composed of the ITO transparent electrode does not overlap the adjacent gate wiring 23. Similar to Example 1, SiN was formed by plasma CVD method.
Gate insulating film (second layer gate insulating film) 21, aS
i: H (i) 8 and SiN channel protective film 25 are continuously deposited to a film thickness of 2000 Å, 200 Å, 1800 Å, respectively, followed by formation of SiN island pattern 25 and plasma C
A-Si: H (n ⁺ ) film formation by VD (film thickness 300
Å), a-Si: H (n ⁺ ) 15, (i) 8 island-shaped pattern is formed by a source / drain two-divided photolithography pattern.

Next, on the SiN gate insulating film (second layer gate insulating film) 21, the Ta ₂ O ₅ dielectric film 2 for additional capacitance formed on the ITO pixel electrode 9 and the next-stage gate wiring 23 is formed.
Photoetching is performed so that 4 is exposed. At this time, as in the first embodiment, photoetching for extracting terminals is also performed at the same time.

Next, metal Al is deposited to a film thickness of 3000 Å, and the signal line pattern 1, the source electrode pattern 5, and the additional capacitor upper electrode pattern 2 are formed by photoetching.
6 is formed. In the first embodiment, the additional capacitance is provided so that the ITO pixel electrode 9 and the next-stage gate wiring 23 directly form a superposed portion via the Ta ₂ O ₅ 24, but in the present embodiment, the additional capacitance is I.
The Al electrode 26 electrically connected to the TO pixel electrode 9 becomes the upper electrode for the additional capacitance. Compared with the structure using ITO of Example 1, the structure of the additional capacitance of this example is Ta ₂ O ₅
This has the advantage that disconnection is unlikely to occur at the step at the end of the dielectric pattern 24. However, since it is necessary to form a contact with the metal Al on the ITO pixel electrode 9, there is a slight problem that the aperture ratio tends to decrease. But T
By reducing the thickness of the a ₂ O ₅ anodic oxide film to 2000 Å, the area of the overlapped portion is 200 even with an additional capacitance of 3 pF.
It is possible to reduce the occupied area to × 14 μm ² .
Therefore, the overlap of the contact with the ITO pixel electrode 9 is 6μ.
If the Al electrode pattern 26 of 200 × 25 μm ² is formed with the gap between the pixel electrode 9 and the gate wiring 23 being 5 μm, it can be accommodated in the black matrix region of one pixel, and the aperture ratio of one pixel is lowered. There is no such thing.

Finally, the protective film 12 is formed so as to cover the entire screen area of the TFT substrate, and the TFT substrate for a liquid crystal display panel is completed.

Embodiment 3 FIG. A third embodiment will be described with reference to FIG. Using the same process as in Example 1, T having a film thickness of 2300Å
a Gate wiring patterning process is performed.

Next, after a formation photoresist is applied, a constant current and a constant voltage formation are carried out at a formation voltage of 50V. The formed film thickness of Ta ₂ O ₅ is 800 Å according to FIG. 7.
The anodization conditions are the same as in Example 1 except that the formation voltage is set to 50V. The remaining film thickness of the Ta gate after formation is about 2000Å.

Next, unlike the first and second embodiments, the SiN gate insulating film (second layer gate insulating film) 21, a is formed by the plasma CVD method without performing the ITO transparent electrode deposition and processing steps.
-Si: H (i) 8 and SiN channel protective film 25 are continuously deposited to a film thickness of 600Å, 250Å and 1500Å, respectively. Next, using a HF-NH ₄ F etchant, to form an island-shaped pattern of the SiN channel protection film 25.

Next, a-Si is formed by the plasma CVD method.
An H (n ⁺ ) film is deposited to a film thickness of 400Å.

Next, a-Si: H (n ⁺ ) 15 and a
-Si: H (i) 8 island-shaped pattern was formed in the same manner as in Example 1.
If the source / drain portion is formed by using a two-divided photolithography pattern, the a-Si: H (n ⁺ ) film is
The a-Si: H (i) film under the SiN channel protective film 25, which is separated between the drains, is left when the a-Si ₂ : H (i) island pattern 8 is completed.

Next, the SiN gate insulating film is photo-etched for taking out terminals, but S is entirely formed in the screen area.
The iN gate insulating film is left.

Next, metal Al is deposited to a film thickness of 2000 Å, and the signal line pattern 1 and the source electrode pattern 5 are formed by photoetching.

Next, an ITO transparent electrode is deposited by a sputtering method to a film thickness of 1200 Å, and the pixel electrode pattern 9 and the Al signal line covering pattern electrode 5 are covered by a photo-etching method using an HCl-based aqueous solution and adjacent to each other. The gate wiring 23 is patterned so as to overlap with the Ta gate wiring 23. At this time, the superposed dielectric film is made of Ta _{2 having} a film thickness of 800 Å.
It is composed of a composite film of an O ₅ film 24 and a SiN film 21 having a film thickness of 600 Å. The area of the overlapping portion is 170 × 25 μm ² and the additional capacitance is 3 pF. Where the width of the additional capacity is 2
5 μm is the size of one pixel 250 μm (H) × 200 μm
It is absorbed in the black matrix region of (H) and the aperture ratio of one pixel is not lowered.

Since the ITO transparent electrode is deposited after the plasma CVD process, it is exposed to reducing plasma during deposition of the SiN gate insulating film 21 using SiH ₄ —NH ₃ —N ₂ -based source gas. ITO is not reduced and deteriorated. For the step break of the ITO pixel electrode at the end of the Al source electrode pattern 5 and the Ta ₂ O ₅ dielectric film pattern 24, the film thicknesses of Al and Ta ₂ O ₅ are 2000Å, respectively.
And it can be taken as a thin film with 800 Å.

At this time, when the Ta ₂ O ₅ single-layer film had a film thickness of less than 800 Å, the insulating property deteriorated. FIG.
Curve a is a diagram showing the voltage-current characteristics of the Ta ₂ O ₅ anodic oxide film having a film thickness of 800 Å. However, when the maximum voltage condition of 21 V applied to the additional capacitance is applied, it corresponds to the area of the additional capacitance. , ¹⁰ at point C ^- leakage current flows close to ^{1 1} a. The composite film of Ta ₂ O ₅ (800 Å) / SiN (600 Å) has the voltage-current characteristics as shown by the curve b.
Even when 1V is applied, 5 × ^{10 -} it was ^{1 4} A sufficiently low leakage current below. However, with a Ta ₂ O ₅ monolayer film, 2
1V applied when the leakage current point C - In (10 ^{1 1 A)} across the membrane, as a composite film overlapping the SiN or SiO _2, reliability has been found to slightly decrease in terms of long-term service life . Therefore, the thickness of the Ta ₂ O ₅ anodic oxide film is 800
Å or more is preferable, and the formation voltage is 50V from FIG.
It is preferable to make the above. On the other hand, in order to prevent the aperture ratio from being lowered, an additional capacitance of 3 pF should be provided, and in order to prevent the step breakage at the gate line crossover portion of the signal line, Ta is required.
It is desirable that the film thickness of ₂ O ₅ be 3200 Å or less.

As described above, FIG. 6 shows a film thickness of 3000.
Ta ₂ O ₅ / SiN composite film (a) and Ta required to realize a capacity equal to that of the Ta ₂ O ₅ single layer film of Å
Is a diagram showing the ₂ O ₅ / SiO ₂ composite film (b) a combination of film thickness. For example, Ta ₂ O ₅ / SiN shown in FIG.
Considering the condition that the film thickness of the Ta ₂ O ₅ film is 800 Å or more in the composite film, the point on the line segment a ₃ -b ₃ shown by the solid line is a preferable range as the combination of the film thicknesses of the composite film,
It can be seen that the thickness range of the SiN film is about 600 Å or less. Similarly, in the case of the Ta ₂ O ₅ / SiO ₂ composite film of FIG. 6B, the line segment a ₃ -b ₃ is in the preferable range, and Si
The thickness range of the O ₂ film is about 350 Å or less.

Finally, the protective film 12 is formed so as to cover the entire screen area of the TFT substrate to complete the liquid crystal display panel TFT substrate.

According to the embodiment shown in FIG. 4, the dielectric film of the additional capacitance is formed of a multilayer film of Ta ₂ O ₅ film and SiN film, so that the Ta ₂ O ₅ film is thinned in order to increase the capacitance. Even if formed, since the SiN film suppresses the leak current, the leak current does not increase between the upper electrode and the lower electrode of the additional capacitor, and the signal voltage holding characteristic of the pixel electrode can be perfected. I can.

Further, by forming the signal line with a multilayer film of a transparent electrode and a metal film which are simultaneously formed with the pixel electrode, it is possible to prevent the signal line from breaking and lower the resistance of the signal line with a simple structure. I can.

Therefore, according to the embodiment shown in FIG. 4, even if a liquid crystal display device having a large display screen is constructed, the screen brightness does not differ between the power supply side and the opposite side of the signal line.

Particularly, in the liquid crystal display device in which the additional capacitance is provided in the pixel electrode, the power supply to the pixel electrode becomes a problem as the capacitance of the additional capacitance is increased.

However, even if the capacitance of the additional capacitance is increased by forming the signal line with a multilayer film to reduce the resistance as in this embodiment, the pixel electrode on the side opposite to the power supply side of the signal line is connected to the pixel electrode. There is no problem that power supply will not be in time.

Further, in a liquid crystal display device having a structure in which the surface of the gate electrode and the gate line is oxidized to provide a surface oxide film, the amount of deposition increases by the amount of oxidation of the metal film. There is a possibility that the step formed at the end becomes tight and the signal line, the source electrode, and the drain electrode formed on the step are disconnected.

However, even if the surface oxide film is provided on the gate electrode and the gate line by forming the signal line and the source and drain electrodes with a multi-layered conductive film as in this embodiment,
The signal line and the source and drain electrodes are not broken.

Embodiment 4 FIG. Example 4 will be described with reference to FIG.

After coating the SiO ₂ underlayer film 20 in the same manner as in Example 1, the Cr gate wiring patterns 32 and 33 are formed.
To form Next, a TaCl ₅ —O ₂ -based source gas is irradiated with a mercury lamp at a substrate temperature of 400 ° C. to perform photo-CVD to deposit a Ta ₂ O ₅ film 28 having a film thickness of 800 Å. At this time, the Ta ₂ O ₅ film 28 may be deposited by a plasma CVD method using a TaCl ₅ —O ₂ based source gas.

Next, the steps subsequent to the step of continuously forming the SiN gate insulating film 21, the a-Si: H (i) film 8 and the SiN channel protective film by the plasma CVD method are similar to those of the third embodiment, A TFT substrate for a liquid crystal display panel as shown in 8 is manufactured. In the embodiment of FIG. 8, a metal other than Ta can be used for the gate wiring, and Ta ₂ O
_{Since the 5th} film does not use the anodic oxide film of the Ta gate wiring, the entire screen of the liquid crystal display panel is Ta ₂ O ₅ 28 /
It has a two-layer structure of the SiN gate insulating film 21.

Example 5. A fifth embodiment will be described with reference to FIG.

A film thickness of 2000 was obtained by the same method as in Example 4.
A Ta ₂ O ₅ CVD film 28 of Å is deposited, and then an a-Si: H (i) film 8 having a film thickness of 250 Å and a SiN channel protective film 25 having a film thickness of 2000 Å are continuously deposited without breaking the vacuum. To do.

Next, the same steps as those in Example 3 were carried out, and then the process shown in FIG.
TFT for liquid crystal display panel with sectional view as shown in
Make a substrate.

In the TFT substrate as shown in FIG. 9, the TFT
_Ta 2 _O 5 directly on the gate insulating film 28 made of CVD film parts a-Si: Although H (i) 8 is deposited, different from the case described in the section of the _action, Ta ₂ O 5 CVD Since the plasma CVD of the a-Si: H (i) film is continuously performed without breaking the vacuum of the film, deterioration of the mobility of the a-Si: H (i) film can be controlled.

Example 6. A sixth embodiment will be described with reference to FIG.

Using the same method as in Example 2, a film thickness of 20
The steps up to 27 steps of the Ta ₂ O ₅ anodized film of 00Å are performed.

Next, in the steps subsequent to the Ta ₂ O ₅ CVD film 28 deposition step, the TFT substrate for a liquid crystal display panel having the sectional view as shown in FIG. 10 is actuated by using the same method as in the fifth embodiment. Here, the film thickness of the Ta ₂ O ₅ CVD film is 10
00 °.

The TFT substrate as shown in FIG. 10 has an advantage that there are few short-circuit defects between the signal line 1 and the gate wirings 22 and 23.

[0075]

According to the present invention, since the oxide of Ta having a large dielectric constant is used for the additional capacitance portion, the area occupied in one pixel of the additional capacitance portion can be reduced, and the aperture ratio of one pixel can be reduced. It is possible to obtain a liquid crystal display panel having high (and therefore high brightness). In addition, since a sufficient amount of additional capacitance can be installed, the retention characteristics of the signal voltage written in one pixel are good, and the image sticking and afterimage characteristics are good, and image defects such as black spots, white spots, and black spots appear in the image. A liquid crystal display panel without is obtained.

Further, when the dielectric film is made to have a double structure of Ta ₂ O ₅ / SiN or Ta ₂ O ₅ / SiO ₂ , the insulating property and the reliability are improved without increasing the area occupation rate of the additional capacitance. It is possible to install an excellent additional capacity.

Further, by forming a multilayer film of Ta ₂ O ₅ and SiN, the leakage of the upper electrode and the lower electrode of the additional capacitance is increased as compared with the case where the dielectric film is formed of a single layer film of Ta ₂ O _5. Can be reduced, and the retention characteristic of the signal voltage written in the pixel electrode can be perfected.

Further, by forming the signal electrode with a multilayer film of a transparent conductive film and a metal film, it is possible to prevent disconnection of the signal electrode and reduce the resistance, and even if the capacitance of the additional capacitance is increased, On the side opposite to the power supply side of the line, the power supply failure of the pixel electrode does not occur.

Further, by forming the signal electrode with a multilayer film including a metal film containing aluminum, the resistance of the signal electrode can be further reduced, and even if a liquid crystal display device having a large display screen is constructed, There is no difference in screen brightness between the power supply side and the opposite side.

Further, the problem that the signal line is disconnected due to the step formed by oxidizing the surfaces of the gate line and the gate electrode can be solved by forming the signal line with a multi-layer conductive film.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main portion of one pixel of a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 2A is a plan view showing a pixel portion of an active matrix liquid crystal display panel according to a conventional technique. (B) is a sectional view taken along the _A 2 -A ₂ 'in (a). (C) is an equivalent circuit diagram of one pixel portion shown in (a).

FIG. 3 is a cross-sectional view of a main portion of one pixel of a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of a main portion of one pixel of a liquid crystal display panel according to a third embodiment of the present invention.

FIG. 5 is a diagram showing voltage dependence of leakage current of additional capacitance.

FIG. 6 Ta ₂ O ₅ / SiN or Ta ₂ O ₅ / SiO
It is a figure showing the conditions of the film thickness of the ₂ composite dielectric film.

FIG. 7 is a diagram showing the dependence of the film thickness of a Ta ₂ O ₅ anodic oxide film on the anodic oxidation voltage.

FIG. 8 is a sectional view of a main portion of one pixel of a liquid crystal display panel according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a main portion of one pixel of a liquid crystal display panel according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a main portion of one pixel of a liquid crystal display panel according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... Signal line, 2, 32 ... Gate line, 3, 33 ... Adjacent gate line, 4 ... TFT, 5 ... Source electrode, 6 ... Gate
Source capacitance, 7 ... Additional capacitance, 8 ... a-Si: H
(I), 9 ... Pixel electrode, 10 ... Signal line cover ITO, 1
1 ... Gate insulating film, 12 ... Protective film, 13 ... Low resistance metal,
14 ... Translucent glass substrate, 15 ... a-Si: H (n ⁺ ).
Layer, 16 ... Pixel capacitance, 17 ... Common electrode terminal, 20 ... Underlayer film, 21 ... Si nitride or oxide, 22 ... Ta gate line, 23 ... Adjacent Ta gate line, 24 ... Ta oxide, 25 ... Channel protective film, 26 ... Metal upper electrode for additional capacitance, 27 ... Ta ₂ O ₅ anodic oxide film, 28 ... Ta ₂ O
₅ CVD film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideaki Yamamoto 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Haruo Matsumaru 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Ken Tsutsui 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. A first substrate in which a pixel including a thin film transistor, an additional capacitor and a pixel electrode is formed in a region formed by two adjacent gate lines and two adjacent signal electrodes.
A liquid crystal display device comprising a combination of a counter substrate and a liquid crystal, wherein the gate line and one electrode of the additional capacitor are provided on the first substrate by a metal film containing tantalum as a main component, and the gate line is provided. And a tantalum oxide film is provided on the surface of one electrode of the additional capacitance, a silicon nitride film is provided on the gate line and one electrode of the additional capacitance, and a semiconductor film is provided on the silicon nitride film. A channel protective film is provided on the semiconductor film, an impurity-doped semiconductor film is provided on the semiconductor film and the channel protective film, and a source electrode and a signal electrode are provided on the impurity-doped semiconductor film. A pixel electrode made of a film and electrically connected to the source electrode is provided, and the other electrode is overlapped with the one electrode with the tantalum oxide film and the silicon nitride film interposed therebetween. Is provided to configure the additional capacitance, the other electrode of the additional capacitance is electrically connected to the pixel electrode, and the signal electrode is formed of a multi-layer conductive film. 2. The liquid crystal display device according to claim 1, wherein the tantalum oxide film is a self-oxidation film formed by oxidizing the surfaces of the gate line and one electrode of the additional capacitance. 3. The liquid crystal display device according to claim 1, wherein the tantalum oxide film is an oxide film formed by anodizing the surfaces of the gate line and one electrode of the additional capacitor. 4. The liquid crystal display device according to claim 1, wherein the signal electrode is composed of a multilayer film of a transparent conductive film and a metal film. 5. The liquid crystal display device according to claim 1, wherein the signal electrode is composed of a multilayer film of aluminum and a conductive film different from aluminum.