JP2000216403A - Active matrix circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase aperture ratio of a pixel by covering the surface of wiring with a metallic oxide film mainly composed of anodized aluminum, and providing a coating film which is mainly composed of silicon nitride having a specified ratio of nitrogen/silicon and containing oxygen or the like between the wiring and the pixel electrode as a dielectric member. SOLUTION: A coating film mainly composed of silicon nitride to be used as a dielectric member, i.e., a second interlayer insulator 610, is prepared by means of a plasma CVD method, wherein the film is mainly composed of silicon nitride, has a nitrogen/silicon ratio in a range preferably between 1-1.34, and may contain 10 atomic% or less of hydrogen, oxygen or carbon. Use of the silicon nitride for the second interlayer insulator 610 is effective in suppressing generation of hillocks (surface ruggedness due to anomalous growth of crystal) on the underlying aluminum film, because generation of hillocks is suppressed by covering the aluminum film surface with the silicon nitride.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix circuit used for an electrostatic display device such as a liquid crystal display device. In particular, the present invention relates to a device using a thin film transistor whose active layer is a crystalline semiconductor thin film as a switching element of an active matrix circuit.

[0002]

2. Description of the Related Art A system using an active matrix circuit for driving a liquid crystal display has attracted attention. In the active matrix circuit, a capacitor having a liquid crystal interposed between a pixel electrode and a counter electrode is formed, and electric charges entering and exiting the capacitor are controlled by a thin film transistor (TFT). In order to display images stably, it was required that the voltage between the two poles of the capacitor be kept constant, but there were difficulties for several reasons.

The biggest problem is that charge leaks from the capacitor even when the TFT is off. In addition, there was also a leak inside the capacitor, but generally the former leak from the TFT was about one digit larger. When the leak is remarkable, a phenomenon called flicker occurs in which the brightness of the image changes at the same cycle as the frame frequency. In particular, in a TFT in which the active layer is formed of a crystalline semiconductor film, the leak current is extremely large, and a countermeasure is required.

To solve this problem, an auxiliary capacitor (also called an additional capacitor) has been provided in parallel with the pixel capacitor. This is shown in a circuit diagram of FIG. That is, with such an auxiliary capacitance, the time constant of the discharge of the charge of the pixel capacitance was increased, and the decrease of the charge from the capacitor of the pixel electrode could be suppressed. Strictly speaking, the auxiliary capacitance C does not necessarily need to be kept at the same potential as the counter electrode, and may be a constant potential for many hours.
Actually, as shown in FIG. 1B, a dedicated wiring _Xn is provided for the auxiliary capacitance, and this is maintained at a specific potential.
As shown in (C), a method is used in which the electrode of the storage capacitor is kept at the same potential as the gate wiring _{Xn + 1} (or _Xn-1 ) of the next stage.

[0005]

For example, in order to fabricate the circuit shown in FIG. 1B, conventionally, as shown in FIG. 2, an auxiliary capacitor 201 is formed simultaneously with a gate wiring 205 (X _n ). A wiring 20 dedicated to an auxiliary capacitor substantially parallel to the gate wiring
2 (X _n ′) and the pixel electrode 203, an interlayer insulating film 2
04 as a dielectric.

However, when the interlayer insulating material 204 is made of a dielectric material, the thickness of the interlayer insulating material 204 is as large as 5,000 ° or more, so that the distance between the electrode plates is widened and the capacitance is reduced. The interlayer insulator 204 is formed by the gate wirings 202 and 20.
Since it is provided for the purpose of reducing the parasitic capacitance between the wiring 5 and the source wiring 206, it is necessary to increase the thickness as described above. Further, when silicon oxide is used as the interlayer insulator 204, the dielectric constant is as small as about 4, which also causes a reduction in capacitance.

For the above reasons, in order to obtain a sufficient capacity for displaying a high quality image, the gate wiring 20 is required.
Although it was necessary to increase the area of No. 2, many parts of the pixel were taken up for the capacity, which caused a problem that the aperture ratio of the pixel was reduced and the screen became dark. The present invention has been made in view of such a problem, and proposes a new configuration as an auxiliary capacitor.

[0008]

According to the present invention, a capacitance formed between a wiring formed simultaneously with a source wiring and a pixel electrode is used as an auxiliary capacitance. As the wiring material, a film whose surface is at least covered with a metal film whose main component is aluminum whose surface is anodized is used, and silicon nitride is used as a main component between the wiring and the pixel electrode. (Hereinafter, referred to as a second interlayer insulator), and this is used as a dielectric.

The metal film containing aluminum as a main component may contain a small amount of silicon, copper, or scandium (Sc). Unless otherwise specified, hereinafter, aluminum means one containing 10% by weight or less of impurities. In the present invention, not only a single-layer film of aluminum but also a multilayer film of aluminum with titanium or another metal is used as a wiring material. For example, in order to obtain ohmic contact with silicon used for the active layer of the TFT and aluminum of other wiring, 50 to 3 layers are formed under the aluminum film.
It is preferable to form 00 nm of titanium or titanium nitride.

[0010] In particular, in the present invention, the aluminum film is anodized. However, in order to avoid hillocks (surface irregularities due to abnormal crystal growth) during the anodization, the above-mentioned additive is added in an amount of 5% by weight or less. It is preferable to mix at a concentration of 0.1 to 0.5% by weight of scandium, for example. Furthermore, the lower the oxygen concentration in the aluminum film, the more the effect of suppressing hillocks was produced. In the present invention, it was desired that hillocks be suppressed as much as possible. This is because the aluminum film is electrically connected to the pixel electrode thereon due to the unevenness of the aluminum film. In addition, the coating mainly composed of silicon nitride used as a dielectric,
It is preferably formed by a plasma CVD method and contains nitrogen and silicon as main components and has a nitrogen / silicon ratio in the range of 1 to 1.34, and contains hydrogen, oxygen, and carbon in an amount of 10 atomic% or less with respect to silicon. You can do it. In the present invention,
The use of silicon nitride as the second interlayer insulator is effective in suppressing the occurrence of hillocks in the underlying aluminum film. This is related to the fact that hillocks are likely to be generated particularly when oxygen is added to the aluminum film. When the surface of the aluminum film is covered with silicon nitride, the generation of hillocks was suppressed.

A typical configuration of the present invention is shown in FIG.
It is. Here, the gate wiring X_nApproximately vertical to the source
Wiring Y_mIs provided, and a gate wiring X is provided._nAnd source wiring Y_m
In the same manner as before, an interlayer insulator (hereinafter referred to as a first interlayer insulation)
Edge). This configuration itself is shown in FIG.
It is the same as the conventional one. In addition to this, the present invention
Source wiring Y_mA wiring Y dedicated to an auxiliary capacitor in parallel with_m’
Is provided. Wiring Y _m’Is the source line Y_mAt the same time
Formed in the same layer. Source wiring Y
_mAnd wiring Y_m′, A second interlayer insulator is formed,
The wiring Y is interposed via the second interlayer insulator._mPart of the pixel
Overlap with the pole, wiring Y_m’And the pixel electrode
Construct C. In FIG. 2, one source line corresponds to one source line.
In addition, a single wiring dedicated to the auxiliary capacitance is provided. I
However, adjacent pixels share the auxiliary capacitance wiring.
In this way, one auxiliary line is provided for two source lines.
It is also possible to assign dedicated capacity.

In the present invention, the thickness of the second interlayer insulator does not need to be as large as the conventional interlayer insulator (eg, 204 in FIG. 2). That is, the interlayer insulator 204 in FIG. 2 requires a sufficient thickness to reduce the parasitic capacitance between the gate wiring and the source wiring.
In the present invention, since the pixel electrode does not intersect with a wiring other than the wiring Y _m ′ (for example, the source wiring Y _m ), the larger the capacitance between the pixel electrode and the wiring Y _m ′, the more preferable. For this reason, it is preferable that the second interlayer insulator between the pixel electrode and the wiring Y _m ′ is thinner as long as the insulating property is maintained and the pixel electrode does not break at a portion where the pixel electrode crosses the wiring Y _m ′. Typically, 500 to 40
0 nm. In addition, since silicon nitride has a dielectric constant of about 9 which is higher than the dielectric constant of silicon oxide, the capacitance per area can be increased as compared with the example of FIG.

In the present invention, a sufficient capacitance can be obtained by reducing the thickness of the second interlayer insulator as described above. This is because the pixel electrode and the wiring Y _m ′ can be obtained.
This also means that sufficient insulation is required. Therefore, generation of pinholes or the like in the second interlayer insulator must be avoided. However, with a film formed by the plasma CVD method, it has been extremely difficult to obtain a thin film having sufficient insulating properties. In the present invention,
The anodization of the surface of the wiring Y _m ′ is also intended to prevent such conduction due to pinholes.

In the present invention, the anodic oxide has a thickness of 5 to 5.
A 200 nm barrier type anodic oxide is formed. Since the barrier type anodic oxide has high hardness and is dense, it is suitable for suppressing conduction between layers. In order to form a barrier-type anodic oxide, what is to be anodized is connected to the positive electrode in a substantially neutral and appropriate electrolytic solution, and a current is applied while increasing the voltage.

For example, as the electrolytic solution, a solution obtained by diluting L-tartaric acid with ethylene glycol at a concentration of 1 to 5% and adjusting the pH to about 7 using ammonia is used. The substrate is immersed in this solution, the + side of the constant current source is connected to the aluminum film or aluminum wiring on the substrate, and the electrode such as platinum is connected to the-side, and a voltage is applied in a constant current state. Oxidation is continued until a voltage of about 150 V is reached. Furthermore, after reaching a predetermined voltage, current may be applied in a constant voltage state, and oxidation may be continued until almost no current flows. As a result, an aluminum oxide film is obtained on the surface of the aluminum film. The thickness of the aluminum oxide film is almost proportional to the applied voltage, and the higher the voltage, the thicker the film.

Here, as the thickness of the aluminum oxide film increases, it functions as a better barrier, but in order to increase the thickness, it is necessary to increase the applied voltage. However, when the applied voltage is increased, the device may be destroyed. Therefore, it is preferable to set the voltage to a level that does not destroy the element.

In the present invention, the anodic oxidation of the wiring Y _m ′ may be performed after the etching of the aluminum film or in the state of the aluminum film before the etching. In the former case, the anodic oxide film is formed not only on the upper surface but also on the side surfaces of the wiring Y _m ′, so that the insulating property is improved. To implement the former method, at the end of the wire Y _m 'as shown in FIG. 3,
What is necessary is just to adopt the method of integrating and applying a current to this. In order to enhance the insulating property of the second interlayer insulator on the source line Y _m, it may be performed anodized similarly to the anodic oxidation of the wiring Y _m '. However, in that case it should be noted that the source line Y _m is in contact with the active layer of the TFT.

That is, as is apparent from FIG. 3, the wiring Y _m ′ has no contact with other wirings and elements,
Since the gate wiring _Xn is separated via the first interlayer insulator, if the first interlayer insulator has a sufficient thickness,
Even if a relatively high voltage (30 to 150 V) is applied during anodic oxidation, the possibility of adversely affecting other wirings and elements is extremely low. On the other hand, TFT as the source line Y _m
When it has the active layer and the contact is anodization voltage, the active layer of the TFT from the source line Y _m, further spans in the gate insulating film, leading to deterioration of the TFT characteristics.

[0019] When employing the latter method (performing the anodic oxidation state of the aluminum film), considering that the above source lines Y _m as well as the aluminum film is in contact with the active layer of the TFT It is necessary to keep the anodizing voltage relatively low (5 to 30 V). In addition, when the latter method is adopted, since the anodic oxide is not formed on the side surface of the wiring Y _m ′, the insulating property from the pixel electrode is slightly deteriorated. Therefore, it is desirable to make the second interlayer insulator thicker. Also in this case, since the silicon nitride film is formed so as to cover the exposed aluminum film on the side surfaces, the generation of hillocks in the lateral direction is sufficiently suppressed.

In the present invention, the above two methods are used.
They may be combined. For example, aluminum film
After anodizing at a low voltage, etch and
Line Y _mAnd wiring Y_m′, And then the wiring Y_m’High
In the method of anodizing at a low voltage, the wiring Y_m'upon
Since anodic oxide can be formed on the surface and side surface,
Insulation is improved, and thin
Since the anodic oxide is also formed, the second interlayer insulation
The insulation of the object can be improved.

When the active matrix circuit of the present invention is used for a device having a short distance between opposed electrodes, such as a liquid crystal display, not only the wiring Y _m ′ but also the second interlayer insulator on the source wiring Y _m Is also important. In a liquid crystal display device, the gap between the opposing substrate and the active matrix substrate is 5
This is because if the insulating property of the second interlayer insulating material is only about μm and the insulating property of the second interlayer insulating material is insufficient, there is a high possibility that the second interlayer insulating material is short-circuited to the counter substrate for some reason. Therefore, it is desirable that coated with anodic oxides upper surface of the source wiring Y _m in the present invention. In addition, since the conduction between the wiring and the counter electrode can be suppressed by doing so, the yield rate can be improved.

According to the present invention, a greater effect can be obtained by using the impurity semiconductor region extending from the active layer of the TFT. That is, as shown in FIG. 5A, a first interlayer insulator is used as a dielectric between the impurity semiconductor region kept at substantially the same potential as the pixel electrode and the wiring Y _m ′ of the present invention. A first capacitor C ₁ is provided between the wiring Y _m ′ and the pixel electrode, and a second interlayer insulator is used as a dielectric.
If the capacitance C ₂ is formed, C ₁ and C ₂ are parallel capacitances, and if C ₁ and C ₂ overlap as much as possible, a larger capacitance can be obtained without lowering the aperture ratio. Is possible.

It is more preferable that the first interlayer insulator is made of a film containing silicon nitride as a main component, like the second interlayer insulator, because it has a high dielectric constant. However, in that case, parasitic capacitance between the gate lines X _n and the source line Y _m increases. In order to make C ₁ a larger capacitance,
It is effective to remove the gate insulating film or the insulating film in the same layer as the gate insulating film and reduce the distance between the impurity semiconductor region and the wiring Y _m ′.

[0024]

[Embodiment 1] FIG. 3 is a schematic view of a circuit having an auxiliary capacitor manufactured in this embodiment as viewed from above (FIG. 3A).
And a circuit diagram (FIG. 3B). In the figure, X _n
Is a gate wiring. _Ym is a source wiring,
Y _m ′ is a dedicated wiring for the auxiliary capacitance. The wiring Y _m ′ is kept at an appropriate potential. C _LC indicates a pixel capacity (capacity between a pixel electrode and a counter electrode to be present thereon), and C is an auxiliary capacity formed by overlapping of Y _m ′ and the pixel electrode.
FIG. 6 shows the steps of this embodiment. 6 (A-1), (B-
1), (C-1) and (D-1) are sectional views, and (A-
2), (B-2), (C-2), and (D-2) are top views.

First, an underlying silicon oxide film 6 is formed on a substrate 601.
02 is 100 to 500 nm by a plasma CVD method,
For example, the film was formed to a thickness of 400 nm. This may be a multilayer film of silicon oxide and silicon nitride. Then, an amorphous silicon film for forming an active layer is formed by plasma CVD.
It was formed to have a thickness of 0 to 150 nm, for example, 50 nm, and was subjected to thermal annealing and laser annealing to be crystallized. Further, this silicon film was patterned to form an island region 603. Then, a silicon oxide film having a thickness of 100 nm was formed as the gate insulating film 604 by a plasma CVD method.

Then, a thickness of 100 nm to 3 μm, for example,
For example, a 500 nm polycrystalline silicon film is
The gate electrode and distribution
Line (X _n605) was formed. Polycrystalline silicon film
In order to improve conductivity, a small amount (1 × 10²⁰~
2 × 10^{twenty one}Atom / cm^Three) Was added. Then
Gate charge is applied to the island region 603 by the on-doping method.
Impurities were introduced in a self-aligned manner using the poles as a mask. here
Then, boron was introduced as an impurity. In this case, dose
1 × 10¹⁵Atom / cm^TwoAnd the acceleration voltage is 65 kV
Was. As a result, the P-type impurity region 606 (source / drain
In) was formed. Furthermore, KrF excimer laser
(Wavelength 248 nm, pulse width 20 nsec)
Thus, the impurity region 606 was activated. (FIG. 6
(A-1), (A-2))

Next, a silicon oxide film having a thickness of 600 nm was formed as the first interlayer insulating film 607 by a plasma CVD method. Here, although not shown in FIG.
The interlayer insulating film 607 is laminated on the entire surface. (FIG. 6 (B
-1), (B-2)) and the first interlayer insulating film 607
The gate insulating film 604 was etched to form a contact hole in the source region 606 of the TFT.

After that, scandium is added by 0.1 to 0.5% by weight, preferably 0.1 to 0.5% by sputtering.
An aluminum film containing 5 to 0.3% by weight, for example, 0.18% by weight was formed. Aluminum film thickness is 20
0-600 nm is preferred. In this embodiment, the thickness is set to 300 nm. Further, in order to obtain ohmic contact with silicon of the active layer of the TFT, a thickness of 50 to 300 nm is formed under the aluminum film.
May be formed.

Thereafter, the aluminum film was anodized to form an anodized film on the film surface. In this anodization, the substrate was immersed in an ethylene glycol solution of 1 to 3% tartaric acid adjusted to pH ア ン モ ニ ア 7 with ammonia, and anodization was performed using platinum as a cathode and the aluminum film as an anode. In the anodization, the current was first increased to 20 V at a constant current, and the oxidation was continued at a constant voltage of 20 V until the current became 0.1 mA or less. Thus, an anodic oxide having a thickness of about 30 nm was formed.

[0030] In this way, by etching the aluminum film anodic oxide film is formed on the surface, the source electrode and wiring (corresponding to Y _m) 608, and aluminum wiring to form a storage capacitance (corresponding to Y _m ') 609 was formed. Conventional capacitance wiring is formed simultaneously with the gate line,
Although the capacitor wiring is formed substantially parallel to the gate line as shown in FIG. 2, the capacitor wiring of this embodiment is formed at the same time as the source wiring 608, so that the capacitor wiring is formed substantially at right angles to the gate wiring. It is a feature. (FIG. 6 (C-1), (C-
2))

Then, as a second interlayer insulator 610,
A 200-nm-thick silicon nitride film was formed by a plasma CVD method. Here, a mixed gas of NH ₃ / SiH ₄ / H ₂ was used. The substrate temperature during film formation was 250 to 350 ° C.
Generally, when a silicon nitride film is formed directly on an aluminum film, hillocks are generated on the aluminum surface due to a rise in temperature during film formation. In this embodiment, however, an anodic oxide film is formed on the aluminum film. As a result, generation of hillocks was suppressed. The silicon nitride film thus formed was etched to form a contact hole in the drain of the TFT. Here, the second interlayer insulator 6 shown in FIG.
Although not shown, it is actually stacked below the pixel electrode 611. After that, the pixel electrode 611 was formed of ITO.

Through the above steps, the aluminum wiring 6
The storage capacitor C was formed in a portion where the pixel electrode 09 and the pixel electrode 611 overlapped. (FIG. 6 (D-1), (D-2)) The storage capacitor C formed in this way uses a silicon nitride film having a large dielectric constant as a dielectric, and the gap between the electrode plates is conventional. Since the capacitance was increased to about 1/3 of that of the pixel, the second layer aluminum wiring could be miniaturized, and the aperture ratio of the pixel could be increased.

[Embodiment 2] FIG. 4 is a schematic view (FIG. 4) of a circuit having an auxiliary capacitor manufactured in this embodiment as viewed from above.
(A)) and a circuit diagram (FIG. 4 (B)). In the figure, _Xn is a gate wiring. X _{n + 1} is a gate wiring in the next row. Y _m is a data line (source wiring)
It is. C _LC indicates a pixel capacity (capacity between the pixel electrode and a counter electrode to be present thereon), and C indicates an auxiliary capacity. In the present embodiment, unlike the first embodiment, one electrode of the auxiliary capacitance is connected to the gate wiring _{Xn + 1} of the next row without providing a wiring dedicated to the capacitance.

FIG. 7 shows the steps of this embodiment. FIG. 7 (A-
1), (B-1), (C-1), and (D-1) are cross-sectional views, and (A-2), (B-2), (C-2), and (D-
2) is a top view. First, an underlying silicon oxide film 702 was formed to a thickness of 300 nm over a substrate 701 by a plasma CVD method. Then, an amorphous silicon film for forming an active layer was formed to a thickness of 50 nm by a plasma CVD method, and was crystallized by performing thermal annealing or laser annealing. Further, this silicon film was patterned to form an island region 703. Then, a silicon oxide film having a thickness of 120 nm was formed as the gate insulating film 704 by a plasma CVD method.

Thereafter, 300 to 800 nm, for example, 6 nm
A 00 nm aluminum film was formed by a sputtering method, and this was patterned to form a gate electrode / wiring (corresponding to _Xn ) 705 and a gate wiring (corresponding to _{Xn + 1} ) 706 in the next row. After that, boron was introduced as an impurity into the island-shaped region 703 in a self-aligned manner by using the gate electrode 705 as a mask by an ion doping method. In this case, the dose is 1 × 10 ¹⁴ atoms / cm ² and the acceleration voltage is 7
0 kV. As a result, a P-type impurity region 707 (source / drain) was formed. Furthermore, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
To activate the impurity region 707.
(FIG. 7 (A-1), (A-2))

Then, as a first interlayer insulator 708,
A silicon oxide film was formed to a thickness of 600 nm by a plasma CVD method. (FIGS. 7B-1 and 7B-2) Then, the first interlayer insulator 708 and the gate insulating film 704 are formed.
Was etched to form a contact hole in the source region 707 of the TFT. Also, independently of or simultaneously with this etching step, in order to connect the aluminum wiring for forming the storage capacitor and the gate wiring 706 in the next row, the contact hole 7 is also formed in the gate wiring 706 in the next row.
13 was formed.

Thereafter, an aluminum film having a thickness of 300 nm containing scandium of 0.18% by weight was formed by a sputtering method. Then, anodic oxidation was performed in the same manner as in Example 1 to form anodic oxide on the surface of the aluminum film.
In this example, the anodic oxidation was first completed by increasing the current to 15 V at a constant current, and maintaining the state for one hour. Thus, an anodic oxide having a thickness of about 20 nm was formed. Thus the source electrode by etching the aluminum film to form an anode oxide on the surface (corresponding to Y _m) 709
Then, an aluminum wiring 710 forming an auxiliary capacitance was formed. (FIG. 7 (C-1), (C-2))

Then, as a second interlayer insulator 711,
A silicon nitride film was formed to a thickness of 100 nm by a plasma CVD method. Here, a mixed gas of NH ₃ / SiH ₄ / N ₂ O / H ₂ was used. This was etched to form a contact hole in the drain of the TFT. Further, the pixel electrode 71
2 was formed of ITO. Through the above steps, the auxiliary capacitance C was formed at the portion where the aluminum wiring 710 and the pixel electrode 712 overlapped. (FIG. 7 (D-1), (D
-2))

[Embodiment 3] FIG. 5 is a schematic view (FIG.
(A)) and a circuit diagram (FIG. 5 (B)). In the figure, _Xn is a gate wiring. Y _m is a data line (source wiring), and Y _m ′ is a dedicated wiring for an auxiliary capacitance. C _LC indicates a pixel capacity (capacity between the pixel electrode and a counter electrode to be present thereon), and C indicates an auxiliary capacity.
FIG. 8 shows the steps of this embodiment. 8 (A-1), (B-
1), (C-1) and (D-1) are sectional views, and (A-
2), (B-2), (C-2), and (D-2) are top views.

First, an underlying silicon oxide film 8 is formed on a substrate 801.
02 was formed to a thickness of 200 nm, and an island-shaped region (active layer) 803 of crystalline silicon was formed to a thickness of 50 nm. In the present embodiment, together with the island-like region 803 is an active layer of the TFT, are also used as an electrode of the storage capacitor C _1. For this reason, it is formed larger than those of the other examples, and
In accordance with the aluminum wiring Y _m 'is the other electrode of the storage capacitor C _1, and has a schematically L-shaped. A silicon oxide film having a thickness of 100 nm was formed as a gate insulating film 804 on the active layer by a plasma CVD method.

Thereafter, 300 to 800 nm, for example, 4
A 00 nm aluminum film was formed by a sputtering method, and this was patterned to form a gate electrode / wiring (corresponding to _Xn ) 805. The aluminum film contained 0.18% by weight of scandium. Next, the substrate was immersed in an ethylene glycol solution of 1 to 3% tartaric acid adjusted to pH ≒ 7 with ammonia, and anodic oxidation was performed using platinum as a cathode and the gate wiring 805 as an anode. The anodic oxidation was first completed by raising the voltage to 150 V at a constant current and maintaining the state for 1 hour. As a result, about 200 nm of anodic oxide was obtained around the gate wiring 805.

Thereafter, phosphorus was introduced as an impurity into the island region 803 in a self-aligned manner by using the gate electrode 805 and the anodic oxide on the side surface thereof as a mask by ion doping. In this case, the dose is 1 × 10 ¹⁵ atoms / c.
m ² , and the acceleration voltage was 80 kV. As a result, an N-type impurity region 806 (source / drain) was formed.
(FIG. 8 (A-1), (A-2))

After that, the gate insulating film was removed by etching while leaving the gate insulating film 804 under the gate electrode 805 to expose the island-shaped semiconductor region 803.
It is preferable to employ dry etching for this etching. In the dry etching method, the anodic oxide (aluminum oxide) is hardly etched, so that only the gate insulating film 804 can be etched without any damage to the gate electrode 805.

[0044] for etching in this manner the gate insulating film, when forming the auxiliary capacitor C ₁ after, in order to increase the capacity by narrowing the inter-electrode. Furthermore, a KrF excimer laser (wavelength 248 nm, pulse width 20 ns)
Irradiation c) was performed to activate the impurity region 806. After that, a 400-nm-thick silicon nitride film was formed as the first interlayer insulating film 807 by a plasma CVD method.
(FIGS. 8 (B-1) and 8 (B-2)) Then, the first interlayer insulating film 807 is etched to form the source region 80 of the TFT.
6, a contact hole was formed.

Thereafter, an aluminum film having a thickness of 300 nm and containing 0.18% by weight of scandium was formed by a sputtering method. Then, as in Example 1, anodic oxidation was performed to form an anodic oxide film on the film surface. In this example, the anodic oxidation was first completed by increasing the current to 20 V at a constant current, and maintaining the state for 10 minutes. Thus, an anodic oxide having a thickness of about 30 nm was formed. Thus etching the aluminum film anodic oxide is formed on the surface the source electrode and wiring (corresponding to Y _m) 80
8 and an aluminum wiring (Y _m '
809). (FIG. 8 (C-1), (C-
2))

As a second interlayer insulator 810, a silicon nitride film was formed to a thickness of 150 nm by a plasma CVD method, and this was etched to form a contact hole in the drain of the TFT. After that, the pixel electrode 811 was formed of ITO. (FIGS. 8D-1 and 8D-2) As a result, the aluminum wiring 809 and the island-shaped semiconductor region 803 are obtained.
Auxiliary capacitor C ₁ consisting the overlapping portions of the, and, the auxiliary capacitor C ₂ consisting of the overlapping portions of the aluminum wiring 809 and the pixel electrode 811 are formed. At this time, the two auxiliary capacitances were connected in parallel, and the auxiliary capacitance could be increased. Further, any of the auxiliary capacitance also a high silicon nitride film having a dielectric constant, particularly for C _1, a gate insulating film 80
By removing No. 4, a significant improvement in capacity was possible.

In this embodiment, the island-shaped region 803 is used.
Was formed in a substantially L-shape, the two auxiliary capacitors could be formed at substantially the same position, and the capacity per area could be improved. As a result, the capacity could be increased without lowering the aperture ratio. In the above example, the pixel electrode 811 and the aluminum wiring 80
9. The overlap of the semiconductor regions 803 is substantially L-shaped, but may be substantially T-shaped as shown in FIGS. 8 (A-3) and (D-3). In that case, FIG. 8 (A-3)
As shown in FIG. 7, after the semiconductor region 803 is formed in a substantially T-shape, an aluminum wiring 809 may be formed so as to overlap the semiconductor region 803. (FIG. 8D-3) Similarly, the pixel electrode 81 is formed.
1, the aluminum wiring 809, and the semiconductor region 803 may have a substantially cross shape.

[0048]

According to the present invention, a second interlayer insulator mainly composed of silicon nitride having a high dielectric constant is used as a dielectric, and an aluminum wiring and a pixel electrode having an anodic oxide film formed on the surface are used. By using the used capacitance as an auxiliary capacitance, it has become possible to improve the characteristics of the active matrix circuit or to improve the aperture ratio. In addition, the investment scale required to implement the present invention is small, and there is no generation of harmful substances. As described above, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 is a circuit diagram in which an auxiliary capacitance is added in parallel to a pixel capacitance.

FIG. 2 shows a cross-sectional view of a conventional TFT on which an auxiliary capacitance is formed.

FIG. 3 shows a schematic diagram and a circuit diagram of the active matrix circuit manufactured in Example 1 as viewed from above.

FIG. 4 shows a schematic diagram and a circuit diagram of the active matrix circuit manufactured in Example 2 as viewed from above.

FIG. 5 shows a schematic diagram and a circuit diagram of the active matrix circuit manufactured in Example 3 as viewed from above.

FIG. 6 shows a manufacturing process of the active matrix circuit of the first embodiment.

FIG. 7 illustrates a manufacturing process of the active matrix circuit according to the second embodiment.

FIG. 8 shows a manufacturing process of the active matrix circuit according to the third embodiment.

[Explanation of symbols]

 601 substrate 602 base film 603 island-shaped semiconductor region (active layer) 604 gate insulating film 605 gate electrode 606 impurity region (Source / drain) 607 ··· first interlayer insulator 608 ··· source electrode and wiring 609 ··· wiring forming auxiliary capacitance 610 ··· second interlayer insulator 611 ···・ Pixel electrode

Claims (25)

[Claims] 1. A thin film transistor which has a semiconductor layer provided with a source and a drain and a gate wiring and is formed over an insulating surface, wherein a wiring having a film containing aluminum as a main component is connected to the semiconductor layer. The thin film transistor is covered with a film mainly containing nitrogen and silicon provided on a wiring having a film mainly containing aluminum, and the film mainly containing oxygen and silicon has a nitrogen / silicon ratio. Is 1
To 1.34, which contains oxygen or hydrogen. 2. A thin film transistor which has a semiconductor layer provided with a source and a drain and a gate wiring, and is formed on an insulating surface, wherein the gate wiring and the semiconductor layer are covered with a silicon oxide film, Is connected to a wiring provided on the silicon oxide film and having a film containing aluminum as a main component. The thin film transistor mainly includes nitrogen and silicon provided on a wiring having a film containing aluminum as a main component. The film containing oxygen and silicon as main components has a nitrogen / silicon ratio of 1
To 1.34, which contains oxygen or hydrogen. 3. A thin film transistor having a semiconductor layer provided with a source and a drain and a gate wiring, and formed on an insulating surface, wherein the front semiconductor layer includes a multilayer of a film mainly composed of aluminum and a titanium film. A wiring having a film is connected; the thin film transistor is covered with a film mainly containing nitrogen and silicon provided on the wiring having the multilayer film; and the film mainly containing oxygen and silicon is nitrogen / silicon. Is 1
To 1.34, which contains oxygen or hydrogen. 4. A thin film transistor which has a semiconductor layer provided with a source and a drain and a gate wiring, and is formed on an insulating surface, wherein the gate wiring and the semiconductor layer are covered with a silicon oxide film; A wiring provided with a multilayer film of a film containing aluminum as a main component and a titanium film provided on the silicon oxide film is connected; and the thin film transistor is provided with nitrogen and silicon provided on the wiring having the multilayer film. The film containing oxygen and silicon as main components has a nitrogen / silicon ratio of 1
To 1.34, which contains oxygen or hydrogen. 5. The thin film transistor according to claim 3, wherein a titanium film of the wiring having the multilayer film is in contact with the semiconductor layer. 6. A thin film transistor having a semiconductor layer provided with a source and a drain and a gate wiring and formed on an insulating surface, wherein the semiconductor layer comprises a film mainly composed of aluminum and a titanium nitride film. A wiring having a multilayer film is connected, the thin film transistor is covered with a film mainly containing nitrogen and silicon provided on the wiring having the multilayer film, and the film mainly containing oxygen and silicon is nitrogen / Silicon ratio is 1
To 1.34, which contains oxygen or hydrogen. 7. A thin film transistor including a semiconductor layer formed on an insulating surface and provided with a source and a drain, and a gate wiring, wherein the gate wiring and the semiconductor layer are covered with a silicon oxide film, and the semiconductor layer includes A wiring having a multilayer film of a film containing aluminum as a main component and a titanium nitride film provided over a silicon oxide film is connected, and the thin film transistor mainly includes nitrogen and silicon provided over the wiring having the multilayer film. The film containing oxygen and silicon as main components has a nitrogen / silicon ratio of 1
To 1.34, which contains oxygen or hydrogen. 8. The thin film transistor according to claim 6, wherein a titanium nitride film of the wiring having the multilayer film is in contact with the semiconductor layer. 9. The method according to claim 1, wherein:
The thin film transistor, wherein the film containing nitrogen and silicon as main components is in contact with the film containing aluminum as a main component of the wiring. 10. The thin film transistor according to claim 1, wherein the film containing nitrogen and silicon as main components contains hydrogen at 10 atomic% or less with respect to silicon. 11. The thin film transistor according to claim 1, wherein the film containing nitrogen and silicon as main components contains oxygen at 10 atomic% or less with respect to silicon. 12. The film according to claim 1, wherein the film containing nitrogen and silicon as main components is a plasma CV.
A thin film transistor formed by a plasma CVD method using a mixed gas containing at least NH ₃ , SiH ₄ and N ₂ O by a method D. 13. An active matrix circuit having a plurality of thin film transistors provided on an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the semiconductor layer mainly contains aluminum. The thin film transistor is covered with a film having nitrogen and silicon as main components provided on the source wiring, and the film having oxygen and silicon as main components is formed of nitrogen / silicon. The ratio is 1
An active matrix circuit, which includes oxygen or hydrogen. 14. An active matrix circuit having a plurality of thin film transistors provided on an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the gate wiring and the semiconductor layer are silicon oxide. The semiconductor layer is connected to a source wiring having a film containing aluminum as a main component and provided on the silicon oxide film, and the semiconductor layer is formed of nitrogen and silicon provided on the source wiring. The film containing oxygen and silicon as main components has a nitrogen / silicon ratio of 1
An active matrix circuit, which includes oxygen or hydrogen. 15. An active matrix circuit having a plurality of thin film transistors provided on an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the front semiconductor layer mainly contains aluminum. A source wiring having a multilayer film of a film and a titanium film is connected, and the thin film transistor is covered with a film containing nitrogen and silicon as main components provided on the source wiring, and containing the oxygen and silicon as main components. The film to be used has a nitrogen / silicon ratio of 1
An active matrix circuit, which includes oxygen or hydrogen. 16. An active matrix circuit having a plurality of thin film transistors provided on an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the gate wiring and the semiconductor layer are silicon oxide. The semiconductor layer is covered with a film, and a source wiring having a multilayer film of a film containing aluminum as a main component and a titanium film provided on the silicon oxide film is connected to the semiconductor layer. The film containing nitrogen and silicon as main components is provided with a nitrogen / silicon ratio of 1
An active matrix circuit, which includes oxygen or hydrogen. 17. The active matrix circuit according to claim 15, wherein the titanium film of the source wiring is in contact with the semiconductor layer. 18. An active matrix circuit including a plurality of thin film transistors provided over an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the semiconductor layer mainly contains aluminum. A source wiring having a multilayer film of a film and a titanium nitride film is connected. The thin film transistor is covered with a film mainly containing nitrogen and silicon provided on the source wiring, and mainly includes the oxygen and silicon. The component film has a nitrogen / silicon ratio of 1
An active matrix circuit, which includes oxygen or hydrogen. 19. An active matrix circuit having a plurality of thin film transistors on an insulating surface, wherein the thin film transistor has a semiconductor layer provided with a source and a drain and a gate wiring, and the gate wiring and the semiconductor layer are covered with a silicon oxide film. The semiconductor layer is connected to a source wiring having a multilayer film of a film containing aluminum as a main component and a titanium nitride film provided on the silicon oxide film, and the thin film transistor is provided on the source wiring. The film containing oxygen and silicon as main components has a nitrogen / silicon ratio of 1
An active matrix circuit, which includes oxygen or hydrogen. 20. The active matrix circuit according to claim 18, wherein a titanium nitride film of the source wiring is in contact with the semiconductor layer. 21. The active matrix circuit according to claim 13, wherein the film mainly containing nitrogen and silicon is in contact with a film mainly containing aluminum of the wiring. . 22. The active matrix circuit according to claim 13, wherein the film containing nitrogen and silicon as main components contains 10 atomic% or less of hydrogen with respect to silicon. 23. The active matrix circuit according to claim 13, wherein the film containing nitrogen and silicon as main components contains oxygen at 10 atomic% or less with respect to silicon. 24. The film according to claim 13, wherein the film containing nitrogen and silicon as main components is plasma C.
An active matrix circuit characterized by being a film formed by a plasma CVD method using a mixed gas containing at least NH ₃ , SiH ₄ and N ₂ O by a VD method. A display device using the active matrix circuit according to any one of claims 13 to 24.