JP3265622B2 - Manufacturing method of liquid crystal display device - Google Patents
Manufacturing method of liquid crystal display deviceInfo
- Publication number
- JP3265622B2 JP3265622B2 JP17728892A JP17728892A JP3265622B2 JP 3265622 B2 JP3265622 B2 JP 3265622B2 JP 17728892 A JP17728892 A JP 17728892A JP 17728892 A JP17728892 A JP 17728892A JP 3265622 B2 JP3265622 B2 JP 3265622B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- forming
- auxiliary capacitance
- gate insulating
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は補助容量の製造工数を削
減したアクティブマトリックス形液晶表示装置およびそ
の製造方法に関する。The present invention relates to an active matrix type liquid crystal display device and its with reduced manufacturing steps of the storage capacitor
And a method for producing the same.
【0002】液晶表示装置には単純マトリックス形とア
クティブマトリックス形とがあり、用途によりそれぞれ
使い分けされているが、アクティブマトリックス形は薄
膜トランジスタを各画素に備えており、特定の画素を選
択する時にそのトランジスタをONさせ、それ以外はO
FFにしておくことから、走査線の数が多くてもクロス
トークを抑制することができ、高いコントラスト比を得
ることができる。A liquid crystal display device includes a simple matrix type and an active matrix type, which are selectively used depending on the application. The active matrix type includes a thin film transistor in each pixel, and the transistor is used when a specific pixel is selected. Is turned on, otherwise O
Since the FF is set, crosstalk can be suppressed even when the number of scanning lines is large, and a high contrast ratio can be obtained.
【0003】そのため、大面積表示用に適し、実用化が
進められている。[0003] Therefore, it is suitable for large-area display, and its practical use is being promoted.
【0004】[0004]
【従来の技術】図4はアクティブマトリックス形液晶表
示装置の等価回路を示しており、また、図5は薄膜トラ
ンジスタ(TFT)と画素および補助容量の配置を示す
正面図である。2. Description of the Related Art FIG. 4 shows an equivalent circuit of an active matrix type liquid crystal display device, and FIG. 5 is a front view showing the arrangement of thin film transistors (TFTs), pixels and auxiliary capacitors.
【0005】すなわち、複数のゲートバス1と複数のド
レインバス2とがそれぞれ直交し、その交差部に薄膜ト
ランジスタ(TFT)3があり、このTFT3のソース
電極4に容量5と補助容量6が並列に配列する構造をと
る。More specifically, a plurality of gate buses 1 and a plurality of drain buses 2 are orthogonal to each other, and a thin film transistor (TFT) 3 is provided at the intersection thereof. A capacity 5 and an auxiliary capacity 6 are connected in parallel to a source electrode 4 of the TFT 3. Take a structure to arrange.
【0006】すなわち、TFTのソース電極4は画素7
を構成する一方の透明電極8と回路接続しているが、画
素7は透明電極8を電極とし、他のガラス基板上に形成
した透明電極との間に液晶を介在させて構成されるの
で、静電容量を有しており、電気的に容量5として示す
ことができる。That is, the source electrode 4 of the TFT is connected to the pixel 7
However, since the pixel 7 is configured by using the transparent electrode 8 as an electrode and interposing a liquid crystal between the transparent electrode 8 and a transparent electrode formed on another glass substrate, It has a capacitance and can be electrically shown as a capacitance 5.
【0007】然し、この容量5だけでは静電容量が不足
し、TFT3のスイッチング動作に当たって画面のちら
つき(フリッカ)や残像(焼きつき)を生ずると云う問
題がある。However, there is a problem that the capacitance is insufficient only with the capacitance 5, and that the switching operation of the TFT 3 causes flicker (flicker) and afterimage (burn-in) of the screen.
【0008】そこで、補助容量5の付加が必要であり、
ガラス基板上に補助容量電極9を形成し、ガラス基板上
に形成してある絶縁膜を誘電体と、透明電極8と対向さ
せて補助容量6を構成している。Therefore, it is necessary to add an auxiliary capacitor 5.
A storage capacitor electrode 9 is formed on a glass substrate, and an auxiliary film 6 is formed by opposing an insulating film formed on the glass substrate to the dielectric and the transparent electrode 8.
【0009】図3は逆スタッガー型TFTと画素と補助
容量の従来構造を示す断面図であり、次の工程により作
られている。すなわち、硼珪酸ガラスなどよりなり、厚
さが約1mmのガラス基板11の上に、アルミニウム(Al)や
タンタル(Ta)のような金属を約100nm の厚さに形成した
後、写真蝕刻技術(フォトリソグラフィ) を用いて選択
エッチングを行い、ゲート電極12と補助容量電極13を形
成する。FIG. 3 is a cross-sectional view showing a conventional structure of an inverted staggered TFT, a pixel and an auxiliary capacitor, which is manufactured by the following steps. That is, a metal such as aluminum (Al) or tantalum (Ta) is formed to a thickness of about 100 nm on a glass substrate 11 made of borosilicate glass or the like and having a thickness of about 1 mm. The gate electrode 12 and the auxiliary capacitance electrode 13 are formed by performing selective etching using photolithography.
【0010】次に、プラズマCVD法により窒化シリコ
ン(Si3Nx ) のような絶縁物を約400nm の厚さに被覆し
てゲート絶縁膜14を形成する。次に、この上に先と同様
にプラズマCVD法などにより動作層15として働く非晶
質シリコン膜(以下a-Si膜)とSi3Nx 膜を形成し、Si3N
x 膜は写真蝕刻技術を用いてパターンニングし、チャネ
ル保護膜16を形成する。Next, a gate insulating film 14 is formed by coating an insulator such as silicon nitride (Si 3 N x ) to a thickness of about 400 nm by a plasma CVD method. Next, an amorphous silicon film (hereinafter referred to as an a-Si film) serving as the operation layer 15 and a Si 3 N x film are formed thereon by a plasma CVD method or the like, and a Si 3 N
The x film is patterned using a photolithography technique to form a channel protection film 16.
【0011】次に、プラズマCVD法によりn型不純物
を添加した非晶質シリコン膜(n+a-Si膜)17と密着を
助けるためのTi膜18とAl膜とを形成し、先と同様に写真
蝕刻技術を用いてパターンニングを行なうことにより図
示を省略したドレインバスラインに続くドレイン電極19
とソース電極20を形成する。Next, an amorphous silicon film (n + a-Si film) 17 to which an n-type impurity is added and a Ti film 18 and an Al film for assisting adhesion are formed by a plasma CVD method. The drain electrode 19 is connected to a drain bus line (not shown) by performing patterning using a photolithography technique.
Then, a source electrode 20 is formed.
【0012】次に、この上にプラズマCVD法により保
護膜21を形成した後、画素形成部の保護膜21をエッチン
グして窓開けし、酸化錫(SnO2) と酸化インジウム(In2
O3)の固溶体( 略称ITO)よりなる透明導電膜をスパ
ッタ法などで形成した後、写真蝕刻技術を用いてパター
ンニングを行い、透明電極8をパターン形成することに
より画素と補助容量が完成している。Next, after a protective film 21 is formed thereon by a plasma CVD method, the protective film 21 in the pixel formation portion is etched to open a window, and tin oxide (SnO 2 ) and indium oxide (In 2 oxide) are formed.
After a transparent conductive film made of a solid solution of O 3 ) (abbreviated as ITO) is formed by a sputtering method or the like, patterning is performed using a photolithography technique, and the transparent electrode 8 is patterned to complete a pixel and an auxiliary capacitor. ing.
【0013】このようにしてTFTは作られているが、
補助容量はガラス基板11の上にゲート電極12と同時に形
成した補助容量電極13を一方の電極とし、ゲート絶縁膜
14と保護膜21を誘電体とし、透明電極8を対極として構
成されている。Although a TFT is made in this way,
The auxiliary capacitance is formed on the glass substrate 11 at the same time as the gate electrode 12 by using the auxiliary capacitance electrode 13 as one electrode.
14 and the protective film 21 are made of a dielectric material, and the transparent electrode 8 is used as a counter electrode.
【0014】こゝで、先に記したように、画面のちらつ
きや残像を無くするためには補助容量は大きい方が望ま
しいが、補助容量電極は画素の下に形成してあるため
に、この電極はむしろ縮小することが好ましい。Here, as described above, it is desirable that the auxiliary capacitance is large in order to eliminate flickering and afterimages on the screen, but since the auxiliary capacitance electrode is formed below the pixel, Preferably, the electrodes are rather reduced.
【0015】[0015]
【発明が解決しようとする課題】TFTを使用するアク
ティブマトリックス形液晶表示装置においてはTFTの
スイッチング動作の際に画面のちらつきや残像を無くす
るために補助容量を画素の下に設けているが、電気的に
は静電容量は従来よりも大きいことが望ましく、一方、
画像表示の面からは補助容量電極の大きさを小さくして
有効表示面積(開口率)を向上することが必要である。In an active matrix type liquid crystal display device using a TFT, an auxiliary capacitor is provided below a pixel in order to eliminate flickering and an afterimage of a screen during a switching operation of the TFT. Electrically, it is desirable that the capacitance is larger than before, while
From the aspect of image display, it is necessary to reduce the size of the auxiliary capacitance electrode to improve the effective display area (aperture ratio).
【0016】[0016]
【課題を解決するための手段】上記の課題は、基板上に
薄膜トランジスタと画素電極および補助容量をマトリッ
クス状に形成してなる液晶表示装置の製造方法におい
て、該基板上に、該薄膜トランジスタのゲート電極と、
該補助容量の補助容量電極とを同時にパターン形成する
工程と、該ゲート電極および補助容量電極のパターンを
含む該基板上にゲート絶縁膜を形成する工程と、該薄膜
トランジスタの動作層およびソース電極/ドレイン電極
を形成する工程と、該薄膜トランジスタを覆う保護膜を
形成する工程と、該画素電極形成領域の該保護膜を除去
し、該ソース電極と該ゲート絶縁膜を露出させる工程
と、露出した該ソース電極および該ゲート絶縁膜に接す
る画素電極を形成し、該ゲート絶縁膜を誘電体とする該
補助容量を形成する工程とを含む液晶表示装置の製造方
法、または、該誘電体膜を該ゲート絶縁膜に代わって、
補助容量電極の表面を電解酸化した酸化膜を用いた液晶
表示装置の製造方法によって解決することができる。SUMMARY OF THE INVENTION The above problem is a thin film transistor and the pixel electrode and the auxiliary capacitance on a substrate Te manufacturing method smell <br/> of the liquid crystal display device obtained by forming a matrix shape, on a substrate, A gate electrode of the thin film transistor;
Simultaneously pattern the auxiliary capacitance electrode of the auxiliary capacitance
Process and the pattern of the gate electrode and the auxiliary capacitance electrode.
Forming a gate insulating film on the substrate, comprising:
Operating layer and source electrode / drain electrode of transistor
Forming a protective film covering the thin film transistor.
Forming and removing the protective film in the pixel electrode formation region
Exposing the source electrode and the gate insulating film
In contact with the exposed source electrode and the gate insulating film.
Forming a pixel electrode, and using the gate insulating film as a dielectric.
Manufacturing a liquid crystal display device including a step of forming an auxiliary capacitor
Method, or in place of the dielectric film in place of the gate insulating film,
Liquid crystal using oxide film obtained by electrolytic oxidation of auxiliary capacitor electrode surface
This can be solved by a method for manufacturing a display device .
【0017】[0017]
【作用】先に記したようにアクティブマトリックス形の
液晶表示においては高画質化のために補助容量の付加が
必要であり、必要とする静電容量はTFTのゲート容量
と画素容量から決められる。As described above, in the active matrix type liquid crystal display, it is necessary to add an auxiliary capacitance for improving the image quality, and the required capacitance is determined by the gate capacitance and the pixel capacitance of the TFT.
【0018】例えば、ゲート長が10μm ,ゲート幅20μ
m のTFTを用い、画素電極の大きさを255 ×90μm と
する場合、画素の下にパターン形成されている補助容量
電極として50×90μm 程度のものが用いられている。For example, the gate length is 10 μm and the gate width is 20 μm.
When the size of the pixel electrode is set to 255.times.90 .mu.m using an m.sup.m TFT, a storage capacitor electrode having a pattern of about 50.times.90 .mu.m is used under the pixel.
【0019】こゝで、従来の補助容量の誘電体は図3に
示すようにゲート絶縁膜14と保護膜21との二層構造をと
り、厚さが約700nm のSi3Nx を用いて形成されている。
そこで、発明者は誘電体の膜厚を減らすことにより補助
容量の小形大容量化を行なうものであり、次の何れかの
方法をとる。 補助容量の誘電体をゲート絶縁膜のみで形成する。 補助容量電極をAlで形成し、誘電体としてはAlを電
解酸化して得た酸化アルミニウム皮膜を使用する。Here, the conventional dielectric of the auxiliary capacitance has a two-layer structure of the gate insulating film 14 and the protective film 21 as shown in FIG. 3, and is made of Si 3 N x having a thickness of about 700 nm. Is formed.
Therefore, the inventor intends to make the auxiliary capacitor smaller and larger by reducing the thickness of the dielectric, and employs any of the following methods. The dielectric of the storage capacitor is formed only of the gate insulating film. An auxiliary capacitance electrode is formed of Al, and an aluminum oxide film obtained by electrolytically oxidizing Al is used as a dielectric.
【0020】本発明はTFTの駆動が低電圧で行なわれ
るために補助容量が必ずしも高い絶縁破壊電圧を必要と
しない点に着目してなされたもので、これにより補助容
量電極の大きさを減少することができる。The present invention has been made in view of the fact that the driving of the TFT is performed at a low voltage, and thus the auxiliary capacitance does not necessarily require a high breakdown voltage, thereby reducing the size of the auxiliary capacitance electrode. be able to.
【0021】[0021]
実施例1(請求項1関連,図1に対応) 図1は本発明の実施法を示す断面図である。 Embodiment 1 (Related to Claim 1, Corresponding to FIG. 1) FIG. 1 is a sectional view showing an embodiment of the present invention.
【0022】すなわち、ガラス基板11の上にスパッタ法
を用いてAlを100nm の厚さに形成した後、写真蝕刻技術
を用い、ゲート電極12はゲート長10μm , ゲート幅20μ
m の寸法で、また、補助容量電極13は幅25μm , 長さ90
μm の寸法にパターン形成した。That is, after Al is formed to a thickness of 100 nm on a glass substrate 11 by a sputtering method, a photolithography technique is used to form a gate electrode 12 having a gate length of 10 μm and a gate width of 20 μm.
m, and the auxiliary capacitance electrode 13 has a width of 25 μm and a length of 90 μm.
A pattern was formed to a size of μm.
【0023】次に、これらのパターンを含む基板上にゲ
ート絶縁膜14として、基板温度を350 ℃に保つ高温プラ
ズマCVD法によりSi3Nx を350nm の厚さに形成し、次
に従来と同様にa-Si膜よりなる動作層15, チャネル保護
膜16,n+a-Si膜17, Ti膜18,Al膜と順次に膜形成し、写
真蝕刻技術を用いてゲート絶縁膜14の上までドライエッ
チングを行い、ドレイン電極19, ソース電極20および、
図示していないバスラインをパターン形成する。Next, as a gate insulating film 14 on the substrate including these patterns, Si 3 N x is formed to a thickness of 350 nm by a high-temperature plasma CVD method keeping the substrate temperature at 350 ° C. An active layer 15 composed of an a-Si film, a channel protective film 16, an n + a-Si film 17, a Ti film 18, and an Al film are sequentially formed on the gate insulating film 14 using a photolithography technique. Perform dry etching, drain electrode 19, source electrode 20, and
A bus line (not shown) is patterned.
【0024】次に、基板上にSi3Nx を基板温度を200 ℃
に保つ低温プラズマCVD法により350nm の厚さに形成
して保護膜21を形成するが、これまでは従来の工程と変
わらない。Next, Si 3 N x was placed on the substrate at a substrate temperature of 200 ° C.
The protective film 21 is formed to have a thickness of 350 nm by a low-temperature plasma CVD method for keeping the thickness of the protective film 21, which is not different from the conventional process.
【0025】すなわち、画素形成部はガラス基板11の上
に補助容量電極13があり、この上にSi3Nx よりなるゲー
ト絶縁膜14と保護膜21が積層されている。次に、基板上
の全域にレジストを被覆した後、画素電極形成領域のみ
を窓開けし、次の条件でプラズマエッチングを行い、低
温で形成されており、エッチングされ易い保護膜21のみ
を除いた。That is, in the pixel forming portion, an auxiliary capacitance electrode 13 is provided on a glass substrate 11, on which a gate insulating film 14 made of Si 3 N x and a protective film 21 are laminated. Next, after coating the resist on the entire region on the substrate, only the pixel electrode formation region was opened, and plasma etching was performed under the following conditions to remove only the protective film 21 which was formed at a low temperature and was easily etched. .
【0026】エッチャント:CF4 とO2(構成比1:0.1) 総流量 :500 sccm ガス圧 :20 Pa μ波電力 :800 W 次に、スパッタ法によりITOを100nm の厚さに形成
し、写真蝕刻技術を用いて透明電極8を形成した。Etchant: CF 4 and O 2 (composition ratio 1: 0.1) Total flow rate: 500 sccm Gas pressure: 20 Pa Microwave power: 800 W Next, ITO was formed to a thickness of 100 nm by sputtering, and photographed. The transparent electrode 8 was formed using an etching technique.
【0027】すなわち、従来の補助容量の膜厚が700nm
であるため、補助容量電極13として50×90μm の面積が
必要であったが、膜厚を1/2 にすることにより面積を25
×90μm に小形化することができ、これにより開口率を
向上することができる。That is, the thickness of the conventional auxiliary capacitor is 700 nm.
Therefore, an area of 50 × 90 μm was necessary for the auxiliary capacitance electrode 13, but the area was reduced to 25% by halving the film thickness.
It is possible to reduce the size to 90 μm, thereby improving the aperture ratio.
【0028】なお、ゲート絶縁膜がこの例のように単一
膜で構成する代わりに複合膜例えばSi3N4/SiO2で形成さ
れている場合もあるが、この場合は保護膜21を除く際に
同時にゲート絶縁膜の上層を除くと効果的である。 実施例2:((請求項2関連,図2に対応) 図2は本発明の実施法を示す断面図である。The gate insulating film may be formed of a composite film, for example, Si 3 N 4 / SiO 2 instead of a single film as in this example. In this case, the protective film 21 is excluded. It is effective to remove the upper layer of the gate insulating film at the same time. Embodiment 2 (Related to Claim 2, Corresponding to FIG. 2) FIG. 2 is a sectional view showing an embodiment of the present invention.
【0029】すなわち、ガラス基板11の上にスパッタ法
を用いてAlを500nm の厚さに形成した後、写真蝕刻技術
を用い、ゲート電極12はゲート長10μm , ゲート幅20μ
m の寸法で、また、補助容量電極13は幅5μm , 長さ90
μm の寸法にパターン形成した。That is, after Al is formed to a thickness of 500 nm on a glass substrate 11 by a sputtering method, a photolithography technique is used to form a gate electrode 12 having a gate length of 10 μm and a gate width of 20 μm.
m, and the auxiliary capacitance electrode 13 has a width of 5 μm and a length of 90 μm.
A pattern was formed to a size of μm.
【0030】次に、これらのパターンを含む基板上にゲ
ート絶縁膜14として、基板温度を350 ℃に保つ高温プラ
ズマCVD法によりSi3Nx を350nm の厚さに形成し、次
に従来と同様にa-Si膜よりなる動作層15, チャネル保護
膜16,n+a-Si膜17, Ti膜18,Al 膜と順次に膜形成し、写
真蝕刻技術を用いてゲート絶縁膜14の上までドライエッ
チングを行い、ドレイン電極19, ソース電極20および、
図示していないバスラインをパターン形成する。Next, as a gate insulating film 14 on the substrate including these patterns, Si 3 N x is formed to a thickness of 350 nm by a high-temperature plasma CVD method keeping the substrate temperature at 350 ° C. An active layer 15 composed of an a-Si film, a channel protective film 16, an n + a-Si film 17, a Ti film 18, and an Al film are sequentially formed, and the gate insulating film 14 is formed by photolithography. Perform dry etching, drain electrode 19, source electrode 20, and
A bus line (not shown) is patterned.
【0031】次に、基板上にSi3Nx を基板温度を200 ℃
に保つ低温プラズマCVD法により350nm の厚さに形成
して保護膜21を形成するが、これまでは従来の工程と変
わらない。Next, Si 3 N x was placed on the substrate at a substrate temperature of 200 ° C.
The protective film 21 is formed to have a thickness of 350 nm by a low-temperature plasma CVD method for keeping the thickness of the protective film 21, which is not different from the conventional process.
【0032】すなわち、画素形成部はガラス基板11の上
に補助容量電極13があり、この上にSi3Nx よりなるゲー
ト絶縁膜14と保護膜21が積層されている。次に、基板上
の全域にレジストを被覆した後、画素電極形成領域のみ
を窓開けし、次の条件で反応性イオンエッチング( 略称
RIE)を行い、保護膜21とゲート絶縁膜14を除き、Al
よりなる補助容量電極13を露出させた。That is, in the pixel forming portion, an auxiliary capacitance electrode 13 is provided on a glass substrate 11, on which a gate insulating film 14 made of Si 3 N x and a protective film 21 are laminated. Next, after covering the entire area on the substrate with the resist, only the pixel electrode formation area is opened, and reactive ion etching (abbreviated as RIE) is performed under the following conditions, excluding the protective film 21 and the gate insulating film 14. Al
The auxiliary capacitance electrode 13 was exposed.
【0033】エッチャント:SF6 流量 :200 sccm ガス圧 :2.6 Pa 電力 :800 W 次に、硼酸アンモン[(NH4)3BO3] の3%水溶液を電解液
とし、露出しているAlを陽極とし、白金(Pt)板を陰極と
し、定電流化成を行なって150 Vまで電圧を上昇せし
め、10分間そのまゝの電圧に保持してAlよりなる補助容
量電極13の表面を酸化アルミニウム( γ´Al203)23に変
換させた。Etchant: SF 6 Flow rate: 200 sccm Gas pressure: 2.6 Pa Power: 800 W Next, a 3% aqueous solution of ammonium borate [(NH 4 ) 3 BO 3 ] is used as an electrolyte, and exposed Al is used as an anode. A platinum (Pt) plate was used as a cathode, constant current formation was performed to increase the voltage to 150 V, and the voltage was maintained at that voltage for 10 minutes, and the surface of the auxiliary capacitance electrode 13 made of Al was aluminum oxide (γ 'Al 2 O 3 ) 23.
【0034】こゝで、酸化アルミニウム23の成長速度は
約14Å/Vであるので、200nm の厚さのAl酸化膜が成長
しており、この比誘電率は約9であるために静電容量は
従来の厚さが700nm のSi3Nx を用い、補助容量電極の大
きさが50×90μm のものと等価となる。Here, since the growth rate of aluminum oxide 23 is about 14 ° / V, an Al oxide film having a thickness of 200 nm is grown, and since its relative dielectric constant is about 9, the capacitance is increased. Is equivalent to a conventional device using Si 3 N x having a thickness of 700 nm and a storage capacitor electrode having a size of 50 × 90 μm.
【0035】すなわち、補助容量電極の大きさを1/10に
小形化することができ、開口率を向上することができ
た。なお、最近開口率を向上する方法としてゲートバス
ラインの一部を補助容量電極として使用する提案もなさ
れているが、この場合にも同様にこの方法を適用するこ
とができる。That is, the size of the auxiliary capacitance electrode can be reduced to 1/10 and the aperture ratio can be improved. Recently, as a method of improving the aperture ratio, it has been proposed to use a part of a gate bus line as an auxiliary capacitance electrode. However, this method can be similarly applied to this case.
【0036】[0036]
【発明の効果】本発明の実施により補助容量の小形化を
実現することができ、これにより開口率の向上が可能と
なる。According to the present invention, the size of the auxiliary capacitance can be reduced, and the aperture ratio can be improved.
【図1】本発明に係る補助容量とTFTの断面図であ
る。FIG. 1 is a cross-sectional view of a storage capacitor and a TFT according to the present invention.
【図2】本発明に係る別の補助容量とTFTの断面図で
ある。FIG. 2 is a sectional view of another auxiliary capacitor and a TFT according to the present invention.
【図3】TFTと画素と補助容量の従来構造を示す断面
図である。FIG. 3 is a sectional view showing a conventional structure of a TFT, a pixel, and an auxiliary capacitor.
【図4】アクティブマトリックス形液晶表示装置の等価
回路である。FIG. 4 is an equivalent circuit of an active matrix liquid crystal display device.
【図5】TFTと画素および補助容量の配置を示す正面
図である。FIG. 5 is a front view showing an arrangement of TFTs, pixels, and auxiliary capacitors.
3 TFT 4 ソース電極 6 補助容量 7 画素 8 透明電極 9,13 補助容量電極 11 ガラス基板 12 ゲート電極 14 ゲート絶縁膜 21 保護膜 23 酸化アルミニウム 3 TFT 4 Source electrode 6 Auxiliary capacitance 7 Pixel 8 Transparent electrode 9,13 Auxiliary capacitance electrode 11 Glass substrate 12 Gate electrode 14 Gate insulating film 21 Protective film 23 Aluminum oxide
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−293329(JP,A) 特開 平4−44014(JP,A) 特開 平1−274116(JP,A) 特開 平4−274029(JP,A) (58)調査した分野(Int.Cl.7,DB名) G02F 1/1368 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-293329 (JP, A) JP-A-4-44014 (JP, A) JP-A-1-274116 (JP, A) JP-A-4- 274029 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) G02F 1/1368
Claims (2)
よび補助容量をマトリックス状に形成してなる液晶表示
装置の製造方法において、前記基板上に、前記薄膜トランジスタのゲート電極と、
前記補助容量の補助容量電極とを同時にパターン形成す
る工程と、 前記ゲート電極および補助容量電極のパターンを含む前
記基板上にゲート絶縁膜を形成する工程と、 前記薄膜トランジスタの動作層およびソース電極/ドレ
イン電極を形成する工程と、 前記薄膜トランジスタを覆う保護膜を形成する工程と、 前記画素電極形成領域の前記保護膜を除去し、前記ソー
ス電極と前記ゲート絶縁膜を露出させる工程と、 露出した前記ソース電極および前記ゲート絶縁膜に接す
る画素電極を形成し、前記ゲート絶縁膜を誘電体とする
前記補助容量を形成する工程と を含む ことを特徴とする
液晶表示装置の製造方法。1. A method for manufacturing a liquid crystal display device comprising a thin film transistor, a pixel electrode, and an auxiliary capacitor formed in a matrix on a substrate, wherein a gate electrode of the thin film transistor is formed on the substrate.
The auxiliary capacitance electrode of the auxiliary capacitance is simultaneously patterned.
And that step, before including a pattern of the gate electrode and the auxiliary capacitance electrode
Forming a gate insulating film on the substrate, and forming an active layer and a source electrode / drain of the thin film transistor.
Forming an in-electrode; forming a protective film covering the thin film transistor ; removing the protective film in the pixel electrode formation region;
Thereby exposing the source electrode and the gate insulating film, Sessu to the source electrode and the gate insulating film is exposed
Forming a pixel electrode, and using the gate insulating film as a dielectric.
You; and a step of forming the storage capacitor
Method of manufacturing a liquid crystal display device.
よび補助容量をマトリックス状に形成してなる液晶表示
装置の製造方法において、前記基板上に、前記薄膜トランジスタのゲート電極と、
前記補助容量の補助容量電極とを同時にパターン形成す
る工程と、 前記ゲート電極および補助容量電極のパターンを含む前
記基板上にゲート絶縁膜を形成する工程と、 前記薄膜トランジスタの動作層およびソース電極/ドレ
イン電極を形成する工程と、 前記薄膜トランジスタを覆う保護膜を形成する工程と、 前記画素電極形成領域の前記保護膜およびゲート絶縁膜
とを除去して前記ソース電極と前記補助容量電極とを露
出させる工程と、 露出した前記補助容量電極を電解酸化して表面に酸化膜
を形成する工程と、 露出した前記ソース電極および前記酸化膜に接する画素
電極を形成し、前記酸化膜を誘電体とする前記補助容量
を形成する工程と を含む ことを特徴とする液晶表示装置
の製造方法。2. A method for manufacturing a liquid crystal display device comprising a thin film transistor, a pixel electrode, and an auxiliary capacitor formed in a matrix on a substrate, wherein the gate electrode of the thin film transistor is provided on the substrate.
The auxiliary capacitance electrode of the auxiliary capacitance is simultaneously patterned.
And that step, before including a pattern of the gate electrode and the auxiliary capacitance electrode
Forming a gate insulating film on the substrate, and forming an active layer and a source electrode / drain of the thin film transistor.
Forming an in-electrode, forming a protective film covering the thin film transistor, and forming the protective film and the gate insulating film in the pixel electrode formation region
To expose the source electrode and the auxiliary capacitance electrode.
And an oxide film on the surface by electrolytically oxidizing the exposed auxiliary capacitance electrode.
Forming, and a pixel in contact with the exposed source electrode and the oxide film
Forming an electrode and using the oxide film as a dielectric;
Method of manufacturing a liquid crystal display device you; and a step of forming a.
Priority Applications (1)
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---|---|---|---|
JP17728892A JP3265622B2 (en) | 1992-07-06 | 1992-07-06 | Manufacturing method of liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17728892A JP3265622B2 (en) | 1992-07-06 | 1992-07-06 | Manufacturing method of liquid crystal display device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001315963A Division JP2002182247A (en) | 2001-10-12 | 2001-10-12 | Liquid crystal display device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0618930A JPH0618930A (en) | 1994-01-28 |
JP3265622B2 true JP3265622B2 (en) | 2002-03-11 |
Family
ID=16028406
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---|---|---|---|
JP17728892A Expired - Lifetime JP3265622B2 (en) | 1992-07-06 | 1992-07-06 | Manufacturing method of liquid crystal display device |
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JP (1) | JP3265622B2 (en) |
Families Citing this family (6)
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US5016032A (en) * | 1986-05-12 | 1991-05-14 | Asahi Kogaku Kogyo Kabushiki Kaisha | Lens shutter camera including zoom lens |
US5214462A (en) * | 1986-05-12 | 1993-05-25 | Asahi Kogaku Kogyo Kabushiki Kaisha | Lens shutter camera including zoom lens and barrier mechanisms |
EP1029598B1 (en) * | 1998-09-11 | 2008-01-09 | Yoshino Kogyosho Co., Ltd. | Trigger type liquid spray container for operation in both upright and inverted positions |
JP2000347096A (en) | 1999-06-04 | 2000-12-15 | Olympus Optical Co Ltd | Photometric and range-finding unit |
KR101219038B1 (en) | 2004-10-26 | 2013-01-07 | 삼성디스플레이 주식회사 | Thin film transistor array panel and manufacturing method thereof |
US8212953B2 (en) * | 2005-12-26 | 2012-07-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
-
1992
- 1992-07-06 JP JP17728892A patent/JP3265622B2/en not_active Expired - Lifetime
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