JP2000314900A - Active matrix display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to suppress the voltage drop of a liquid crystal cell by connecting plural thin film transistors and appropriate capacitances. SOLUTION: A semiconductor film is formed of the same material as that of the channel area of a thin film transistor, an insulating film forming capacitance is formed of the same material as that of an gate insulating film of the thin film transistor, and an electrode forming the capacitance is formed of the same material as that of a gate electrode of the thin film transistor, respectively. By providing capacitance 223 between the thin film transistors 221, 222 connected in series, a voltage appearing across the source and drain of the thin film transistor 222 especially on the pixel electrode is reduced, and the OFF-current of the thin film transistor 222 is decreased. Therefore, it is possible to prevent a thin film transistor from being deteriorated because the deterioration of a thin film transistor depends on the voltage across the source and drain. Moreover, when one or both of the capacitors 223, 224 are formed of MOS type capacitors, it is effective for integration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and an element for improving the image quality of a display screen of an active matrix display device.

[0002]

2. Description of the Related Art FIG. 2A is a schematic view of a conventional example of an active matrix display device. A region (204) surrounded by a broken line in the drawing is a display region, and thin film transistors (201) are arranged in a matrix in the display region. The wiring connected to the source electrode of the thin film transistor (201) is an image (data) signal line (206), and the wiring connected to the gate electrode of the thin film transistor (201) is a gate (select) signal line (205). ).

Here, focusing on the driving element, the thin film transistor (201) performs data switching to drive the liquid crystal cell (203). Auxiliary capacity (2
02) is a capacitor for reinforcing the capacity of the liquid crystal cell, which is used for holding image data. The thin film transistor (201) is used for switching image data of a voltage applied to the liquid crystal. Assuming that the gate voltage of the thin film transistor is V _GS and the drain current is I _D , the relationship becomes V _GS -I _D as shown in FIG. That is, when the gate voltage V _GS is in the OFF region of the thin film transistor, I _D
Becomes larger. This is called an OFF current.

In the case of an N-channel type thin film transistor, V
The OFF current when _GS is negatively biased is defined by the current flowing through the PN junction formed between the P-type layer induced on the surface of the semiconductor thin film and the N-type layers in the source and drain regions. . Since many traps are present in the semiconductor thin film, the PN junction is incomplete and a junction leak current easily flows. The more the gate electrode is negatively biased, the more the OFF current increases because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases and the width of the energy barrier of the PN junction narrows, so that electric field concentration occurs. This is because the junction leakage current increases.

[0005] The OFF current thus generated largely depends on the source / drain voltage. For example, it is known that the OFF current dramatically increases as the voltage applied between the source and the drain of the thin film transistor increases. That is, 5 between source / drain
In the case where a voltage of V is applied and in the case where a voltage of 10 V is applied, the OFF current of the latter may not be twice as large as the former, but may be 10 times or 100 times. Such nonlinearity also depends on the gate voltage. Generally, when the value of the reverse bias of the gate electrode is large (a large negative voltage in the case of the N-channel type), the difference between the two is remarkable.

In order to solve this problem, for example, as described in Japanese Patent Publication No. 5-44195 and Japanese Patent Publication No. 5-44196, a method of connecting thin film transistors in series (multi-gate method) has been proposed. . This is intended to reduce the OFF current of each thin film transistor by reducing the voltage applied to the source / drain of each thin film transistor. For example, when two thin film transistors are connected in series as shown in FIG. 2B, the voltage applied to the source / drain of each thin film transistor becomes half. If the voltage applied to the source / drain is halved, O
The FF current becomes 1/10 or 1/100.

[0007]

However, when the characteristics required for displaying an image on a liquid crystal display become severe, it has become difficult to reduce the OFF current as much as necessary even in the above-mentioned multi-gate method. That is, even if the number of gate electrodes (the number of thin film transistors) is increased to three, four, and five, the voltage applied to the source / drain of each thin film transistor is ３, ４, and ５. This is because it decreases only slightly. In order for the voltage applied to the source / drain to be 1/100, the gate must be 1
00 pieces were required. That is, in this method, the effect was most remarkable when the number of gates was set to two, but a great effect could not be expected even if more gates were provided.

The present invention has been made in view of the above-mentioned problems, and reduces the voltage applied to the source / drain of a thin film transistor connected to a pixel electrode to 1/10 or less of a normal case, preferably 1%. An object of the present invention is to provide a pixel circuit having a structure in which the OFF current is reduced by adjusting the ratio to / 100 or less. What is characteristic at this time is that the number of thin film transistors for the above purpose is made sufficiently small. The above goal is achieved by preferably 5 or less, more preferably 3 thin film transistors.

[0009]

According to one aspect of the present invention, an active matrix display device includes pixel electrodes arranged in a matrix on a substrate, and a thin film transistor is connected to the pixel electrodes. The thin film transistor includes at least a channel region, a source region, a drain region, a gate insulating film in contact with the channel region, and a gate electrode in contact with the gate insulating film. , A capacitor is connected, and the capacitor is composed of an electrode, an insulating film below the electrode, and a semiconductor film under the insulating film, and the semiconductor film is composed of the same material as a channel region of the thin film transistor. It is characterized by the following.

In the above structure, the insulating film forming the capacitor is made of the same material as the gate insulating film of the thin film transistor.

Further, in the above structure, the electrode forming the capacitor is made of the same material as the gate electrode of the thin film transistor.

The basic idea of the present invention is that a thin film transistor (22) connected in series as shown in FIG.
By providing the capacitor (223) between 1) and (222), the thin film transistor (222) particularly on the pixel electrode side is provided.
Is to lower the voltage appearing between the source and the drain of the thin film transistor, thereby reducing the OFF current of the thin film transistor (222). Although the capacity (224) is shown in the figure, this is not always necessary. Rather, since it increases the load at the time of writing, it may be preferable that the ratio between the capacity of the pixel cell (225) and the capacity (223) is not optimal as long as it is optimal.

More specifically, when a selection signal is sent to the gate signal line (226), both of the thin film transistors (221) and (222) are turned on, and the signal of the image signal line (227) is turned on. Depending on the capacity (22
3), (224), the pixel cell (225) is charged.
At the stage of sufficient charge (equilibrium), the voltage between the source and the drain of the thin film transistor (222) is almost equal.

When the selection signal is turned off in this state, the thin film transistors (221) and (222) are both turned off. After that, the signal of another pixel is applied to the image signal line (227), and the thin film transistor (221) has a finite OFF current, so that the charge charged in the capacitor (223) is released, and the voltage decreases. Will be done. However, this speed proceeds at the same speed as the voltage drop of the capacitance (202) of the normal active matrix circuit shown in FIG.

On the other hand, regarding the thin film transistor (222), the OFF current was extremely small at first because the voltage between the source and the drain was almost 0, but thereafter, the voltage of the capacitor (223) dropped. , The voltage between the source and the drain gradually increases, and accordingly, the OFF current also increases. However, the voltage drop of the pixel cell (225) due to the increase of the OFF current is shown in FIG.
Needless to say, it is much slower than that in the normal active matrix circuit shown in FIG.

For example, it is assumed that the thin film transistors (201) and (221) have similar characteristics, and the capacity (20)
2) The voltage is 90% from the initial 10V during one frame
Of 9V. In the case of FIG. 2A, the voltage of the pixel cell (203) drops to 9 V during one frame. However, in the case of FIG.
Even if the voltage of 23) drops to 9 V, the OFF current is extremely small because the voltage between the source and the drain of the thin film transistor (222) is 1 V, and it is a story at the end of one frame. Pixel cell (225)
And the accumulated amount of charge discharged from the capacitor (224) is extremely small, and therefore, the voltage of the pixel cell (225) becomes 10
It is almost the same as V.

Although the comparison with the case of FIG. 2B is not easy, in FIG. 2B, the voltage applied to the source / drain of one thin film transistor is 10 V in FIG. 2A. 5C, which is half of that of the thin film transistor (222) in FIG. 2C, and it is unlikely that the voltage between the source and the drain is 1V. Therefore,
This aspect also shows the superiority of the present invention.

The thin film transistors (221), (2)
When an LDD region or an offset region is placed in the channel of 22), these regions become drain resistance and source resistance, so that it is needless to say that the electric field strength at the drain junction can be reduced and the OFF current can be further reduced. Further, as shown in FIG. 2D, a greater effect can be obtained by further adding a combination of a thin film transistor and a capacitor. However, as compared with the case where FIG. 2A is replaced with FIG. , The rate at which the effect increases is reduced.

In the above description, the capacitances (223), (22)
4) may be a normal capacitor, but if one or both of them are constituted by MOS type capacitors (MOS capacitors), it is effective in terms of integration. Note that the capacity (224) is not always necessary, as described above. For example, three or more thin film transistors are connected in series to one pixel electrode, and at least one thin film transistor except for both ends of the serially connected thin film transistors is always in an ON state and used as a capacitor, or The connection point between the drain of one thin film transistor and the source of the other thin film transistor and the AC ground point
What is necessary is just to connect by OS capacity.

[0020]

Embodiment 1 FIG. 1A shows an example of an active matrix display system in which three thin film transistors are connected to one electrode of one pixel cell (105). All the thin film transistors are of the N-channel type, but the same applies to the P-channel type. Rather, in a thin film transistor using a crystalline silicon semiconductor formed at a low temperature, the P-channel type has a feature that an OFF current is smaller and deterioration is less likely.

Two thin film transistors (101), (1)
02) shares the gate wiring and is connected to the gate signal line. The source of the thin film transistor (101) is connected to an image signal line. A thin-film transistor (103) which is always on between the two thin-film transistors;
Connect. In order to keep the thin film transistor (103) on at all times, it is desirable to apply a sufficiently high positive potential to the gate, which is hardly affected by an image signal or the like.

For example, when the image signal fluctuates between -10V and + 10V, the gate of the thin film transistor is set at + 15V.
It is desirable that the potential is always kept at V or higher, preferably +20 V or higher. For example, a thin film transistor (103)
, The potential difference between the gate and the source fluctuates between +1 to +11 V near the threshold voltage, and the capacitance obtained in the thin film transistor (103) also fluctuates greatly. On the other hand, if the potential of the gate of the thin film transistor (103) is +20 V, the potential difference between the gate and the source fluctuates between +10 and +30 V, but is sufficiently far from the threshold voltage.
The capacitance obtained in the thin film transistor (103) hardly varies.

Liquid crystal cell (105) and storage capacitor (104)
Is connected to the drain of the thin film transistor (102).
The other electrodes of the liquid crystal cell (105) and the storage capacitor (104) may be connected to the installation level. If the capacity of the liquid crystal cell (105) is sufficient, the auxiliary capacity (104)
May not be required. The optimum size of the MOS capacitor (103) may be determined in terms of the ratio between the auxiliary capacitor (104) and the sum of the capacitances of the liquid crystal cells (105).

The operation of FIG. 1A will be described. First, an 'H' level voltage is applied to the gates of the two thin film transistors (101) and (102), and the thin film transistors are turned on. Then, a current according to an image signal flows through the source of the thin film transistor (101),
The thin-film transistor (103) connected to the drain of the thin-film transistor (101), which is always on, functions as a capacitor and starts charging. Since the thin film transistor (103) is always in the ON state, a current flows from the source to the drain of the thin film transistor (102), and charges the storage capacitor (104) and the liquid crystal cell (105).

Next, the thin film transistors (101), (1)
02), when a voltage at the 'L' level is applied to the gate,
The thin film transistor is turned off, the voltage of the source of the thin film transistor (101) drops, an off current flows for the charge stored in the thin film transistor (103) which is always on, and discharge starts. But always O
The voltage drop between the drain and the source of the thin film transistor connected to the pixel is delayed due to the capacitance of the thin film transistor (103) in the N state. Therefore, the amount of discharge of the auxiliary capacitance (104) and the liquid crystal cell (105) decreases, and the liquid crystal cell (1) remains on until the thin film transistor is turned on in the next screen.
05) is suppressed. FIG. 6 shows the above.
(A).

In FIG. 1A, consider a circuit in which the normally ON N-channel thin film transistor (103) is omitted. Two N-channel thin film transistors (10
1 and 102) share the gate wiring, and the liquid crystal cell (10
5) and the storage capacitor (104)
Connect to 2) drain. This is a so-called multi-gate type circuit shown in FIG.

First, two thin film transistors (101),
An 'H' level voltage is applied to the gate electrode of (102), and the thin film transistor is turned on. Then, current flows to the source of the thin film transistor, and the auxiliary capacitance (10
4) and charging the liquid crystal cell (105).

Next, the thin film transistors (101), (1)
02), a voltage at the “L” level is applied to the gate of the thin film transistor (1).
01), the voltage at the source of the thin film transistor (102) also drops. Therefore, the auxiliary capacitance (104) and the liquid crystal cell (105) start discharging. The above is the drain voltage (b) in FIG. The discharge amount is larger than in the case of (a),
It can be seen that the voltage drop is also large.

As described above, the effect of the present invention was proved by the present embodiment. It should be noted that, similarly to FIG. 2D, a greater effect can be obtained if a thin film transistor similar to the thin film transistors (102) and (103) is inserted between the thin film transistors (192) and (104). There will be.

Embodiment 2 FIG. 1B shows an example of a pixel of an active matrix circuit in which two thin film transistors are connected to one pixel electrode. Although all the thin film transistors are of the N-channel type, the same effects can be obtained even if they are of the P-channel type.

Two thin film transistors (111), (1
12) shares the wiring of the gate and connects to the gate signal line. M between the source / drain of the thin film transistor
The OS capacity (113) is connected. MOS capacitance (113)
May be formed by short-circuiting the source and drain of a normal thin film transistor. Since this MOS capacitor uses an N-channel thin film transistor, it functions as a capacitor if the gate is kept at an appropriate positive potential. In order to function as a stable capacitor, it is desirable to maintain a sufficiently high positive potential, similarly to the gate of the thin film transistor (103) of the first embodiment. In order to implement the present invention,
At least during most of the time when the pixel is not selected, the gate of the MOS capacitor (113) needs to be kept at the above-described potential. Also, it is desirable that the gate of the MOS capacitor (103) be kept at the above-mentioned potential even during the time when the pixel is selected (the time when the pixel is written by the signal of the image signal line).

Liquid crystal cell (115) and storage capacitor (114)
Is connected to the drain of the thin film transistor (112), and the source of the thin film transistor (111) is connected to the image signal line. Further, it is preferable that one electrode of the capacitor (114) and the gate of the MOS capacitor (113) are held at a common potential. Note that the auxiliary capacity (114) is not necessary if the capacity of the liquid crystal cell (115) is sufficient.

The operation of FIG. 1B will be described. For simplicity, the gate of the MOS capacitor (113) is always kept at a sufficiently high positive potential. First, an “H” level voltage is applied to the gates of the two thin film transistors (111) and (112), and
It becomes N state. As a result, the thin film transistor (111)
A current flows to the source of the thin film transistor (111), and the MOS capacitor (113) connected to the drain of the thin film transistor (111) starts to be charged. In addition, current flows from the source electrode to the drain electrode of the thin film transistor (112), and charges the storage capacitor (114) and the liquid crystal cell (115).

Next, the thin film transistors (111), (1)
'L' level voltage is applied to the gate electrode of 12),
The thin film transistor is turned off, the voltage of the source electrode of the thin film transistor (111) drops, and the MOS capacitor (113) starts discharging by the off current of the thin film transistor. However, due to the MOS capacitance (113),
The voltage drop between the drain and the source of the thin film transistor connected to the pixel is delayed. Therefore, the auxiliary capacitance and the discharge amount of the liquid crystal cell (115) are reduced, and the liquid crystal cell (115) is maintained until the thin film transistor is turned on in the next screen.
Is suppressed. The operation waveform is the same as that of the first embodiment.

Third Embodiment FIG. 1C shows an example of a pixel of an active matrix circuit in which two thin film transistors are connected to one pixel electrode. Although all the thin film transistors are of the N-channel type, the same effects can be obtained even if they are of the P-channel type. Two thin film transistors (12
1) and (122) share the gate wiring and connect to the gate signal line. A capacitor (123) is connected between the source / drain of the thin film transistor.

The auxiliary capacitance (124) is formed using a MOS capacitance. This may be formed by short-circuiting the source and drain of a normal thin film transistor, similarly to the MOS capacitor (113) of the second embodiment. Since this MOS capacitor uses an N-channel thin film transistor, it functions as a capacitor if the gate is kept at an appropriate positive potential. In order to function as a stable capacitor, it is desirable to maintain a sufficiently high positive potential, similarly to the gate of the MOS capacitor (113) of the second embodiment. In order to implement the present invention,
At least during most of the time when the pixel is not selected, the gate of the storage capacitor (124) needs to be kept at the above-described potential. Also, during the time when the pixel is selected (the time when the pixel is written by the signal of the image signal line), the storage capacitor (1
It is desirable that the gate of 24) be kept at the above potential.

Liquid crystal cell (125) and storage capacitor (124)
Is connected to the drain of the thin film transistor (122), and the source of the thin film transistor (121) is connected to the image signal line. Further, it is preferable that one electrode of the capacitor (123) and the gate of the auxiliary capacitor (124) be kept at a common potential. The operation of such a circuit element is the same as in the first and second embodiments.

Embodiment 4 FIG. 1D shows an example of a pixel of an active matrix circuit in which two thin film transistors are connected to one pixel electrode. Although all the thin film transistors are of the N-channel type, the same effects can be obtained even if they are of the P-channel type. Two thin film transistors (13
1) and (132) share the gate wiring and connect to the gate signal line. A MOS capacitor (133) is connected between the source / drain of the thin film transistor. This may be formed by short-circuiting the source and drain of a normal thin film transistor, similarly to the MOS capacitor (113) of the second embodiment.

In this embodiment, the auxiliary capacitance (134) is also a MOS.
It is formed using a capacitor. Since these MOS capacitors use N-channel thin film transistors, they function as capacitors if the gate is kept at an appropriate positive potential. In order to function as a stable capacitor, it is desirable to maintain a sufficiently high positive potential, similarly to the gate of the thin film transistor (113) of the second embodiment. Further, in order to implement the present invention, it is necessary that the gates of these MOS capacitors be held at the above-mentioned potentials at least for a large part of the time when the pixel is not selected. Also, it is desirable that the gate of the MOS capacitor be kept at the above-mentioned potential even during the time when the pixel is selected (the time when the pixel is written by the signal of the image signal line).

Liquid crystal cell (135) and storage capacitor (134)
Is connected to the drain of the thin film transistor (132), and the source of the thin film transistor (131) is connected to the image signal line. Further, the gate of the MOS capacitor (133) and the gate of the auxiliary capacitor (134) are preferably held at a common potential. The operation of such a circuit element is the same as in the first to third embodiments.

[Embodiment 5] The present embodiment relates to the steps of manufacturing the circuits shown in Embodiments 1-4. This embodiment is characterized in that an offset gate is formed by anodizing a gate electrode to reduce an OFF current. 4A to 4D show the steps of this embodiment. First, the substrate (401) (Corning 7059, 100 mm
× 100 mm) on a silicon oxide film (40
2) was formed at 1000 to 5000 °, for example, 3000 °. The silicon oxide film was formed by decomposing and depositing TEOS by a plasma CVD method. This step may be performed by a sputtering method.

Thereafter, the amorphous silicon film is formed in a thickness of 300 to 1500 by a plasma CVD method or an LPCVD method.
Å, for example, 500Å and deposited at 550-600 ° C.
And allowed to crystallize for 8 to 24 hours. In that case, a small amount of nickel may be added to promote crystallization. This step may be performed by laser irradiation. Then, the silicon film crystallized in this manner was etched to form an island region (403). Further, a gate insulating film (404) was formed thereon. Here, the thickness is 700 to 700 by a plasma CVD method.
A silicon oxide film of 1500 °, for example, 1200 ° was formed. This step may be performed by a sputtering method.

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 to 3 μm, for example, 5000 ° is formed by a sputtering method, and this film is etched. Gate electrodes (405), (406), and (407) were formed. (FIG. 4 (A))

Then, the gate electrode is anodized by passing an electric current in an electrolytic solution to a thickness of 500 to 2500.degree.
A 2000 mm anodic oxide was formed. The electrolytic solution used was prepared by diluting L-tartaric acid with ethylene glycol to a concentration of 5% and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate is immersed in the solution, the + side of the constant current source is connected to the gate electrode on the substrate, and the platinum electrode is connected to the-side, and a voltage is applied at a constant current of 20 mA.
Oxidation was continued until reaching 50V. In addition, 150V
Oxidation was continued until the current became 0.1 mA or less. As a result, aluminum oxide films (408), (409), and (410) having a thickness of 2000 mm were obtained.

Thereafter, impurities (here, phosphorus) are implanted into the island region (403) in a self-aligned manner by ion doping using the gate electrode portion (ie, the gate electrode and the anodic oxide film around the gate electrode) as a mask. Thus, an N-type impurity region was formed. Here, phosphine (PH ₃ ) was used as the doping gas. The dose in this case is 1 ×
10 ¹⁴ -5 × 10 ¹⁵ atoms / cm ² , acceleration voltage 60-9
0 kV, for example, a dose of 1 × 10 ¹⁵ atoms / cm ² ,
The acceleration voltage was 80 kV. As a result, N-type impurity regions (411) to (414) were formed. (FIG. 4 (B))

Further, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) activated the doped impurity regions (411) to (414). Laser energy density is 200 ~
400 mJ / cm ² , preferably 250-300 mJ /
cm ² was adequate. This step may be performed by thermal annealing. Thus, the N-type impurity region is formed. In the present embodiment, it is understood that the impurity region is far from the gate electrode by the thickness of the anodic oxide, that is, a so-called offset gate.

Next, plasma CVD is used as an interlayer insulating film.
A silicon oxide film (415) was formed to a thickness of 5000 ° by the method. At this time, TEOS and oxygen were used as source gases. Then, an interlayer insulating film (415) and a gate insulating film (4
04) to form an N-type impurity region (41).
1) A contact hole was formed. Thereafter, an aluminum film was formed by a sputtering method and etched to form a source electrode / wiring (416). This is an extension of the image signal line. (FIG. 4 (C))

Thereafter, a passivation film (417) was formed. Here, a silicon nitride film is formed by plasma CVD using a mixed gas of NH ₃ / SiH ₄ / H _2.
A film having a thickness of 0 to 8000 °, for example, 4000 ° was formed to form a passivation film. Then, the passivation film (417), the interlayer insulating film (415), and the gate insulating film (404) are etched to form a hole on the anodic oxide film (409) and the N-type impurity region (41).
4) A contact hole for a pixel electrode was formed. Then, an indium tin oxide (ITO) film is formed by a sputtering method, and is etched to form a pixel electrode (41).
8) was formed.

The pixel electrode (418) has an anodic oxide film (4).
09), a capacitor (419) was formed opposite to the gate electrode (406). The N-type impurity region (41
If 2) and (413) are kept at the same potential, the gate electrode (40
A MOS capacitor having the gate insulating film (404) as a dielectric is formed between 6) and the silicon semiconductor thereunder.
(FIG. 4 (D))

Through the above steps, the N-channel thin film transistors (421) and (422) and the capacitor (41)
9) An active matrix circuit element having (420) was formed. In the present embodiment, the pixel electrode forms a capacitance with the gate of the MOS capacitor, and thus is the same as the circuit shown in FIG. 1A or 1B.

FIG. 4 is a cross-sectional view, and FIG. 3 shows an example of this as viewed from above. In this embodiment, when the gate electrode crosses the island region (403) as shown in FIG. 3A, a thin film transistor is formed by the gate (406). On the other hand, when the gate (406) does not cross the island region (403) as shown in FIGS. In any case, in this embodiment, there are three gates, but only two contacts are required, and the capacity is formed by using the multilayer wiring, so that the occupied area is small.

FIG. 3B shows a standard MOS capacitor. Since the channel width of a thin film transistor used for an active matrix circuit element is generally small, the width of the gate (406) must be sufficiently large. ,
It is difficult to secure sufficient capacity. In such a case, as shown in FIG. 3C, the width of the island region (403) may be increased only in the portion of the MOS capacitor. FIG. 3 (D)
The gate (406) may be modified as follows.

However, if none of these methods is sufficient to secure a sufficient capacity, the island-shaped region may be deformed as shown in FIG. In this case, the gates (405) and (407) can be formed on the same straight line, which is advantageous in terms of layout.

[Embodiment 6] FIG. 4E shows a cross section of this embodiment. In this embodiment, N-channel thin film transistors (452) and (453) and a gate (454) are formed therebetween, and a MOS capacitor (450) is formed between the thin film transistor and the silicon semiconductor thereunder by using a gate insulating film as a dielectric. Is done. In addition, a thin film transistor (453) and a pixel electrode (457)
A gate (455) 'is also formed between the contacts, and a MOS capacitor (451) is similarly formed. On the other hand, the metal wiring (456) is an extension of the image signal line.

In this embodiment, the thin film transistor (45)
A first MOS capacitor (450) is formed between (2) and (453), and a pixel electrode (457) and a thin film transistor (4) are formed.
Since the second MOS capacitance (451) is formed during the period 53), it corresponds to FIG. In this embodiment, there are four gates, but the area occupied is relatively small because only two contacts are required.

[Embodiment 7] FIG. 4F shows a cross section of this embodiment. In this embodiment, the N-channel thin film transistors (472) and (473) and the metal wiring (47)
4) is drawn out and extended on the upper surface of the gate (477) provided between the thin film transistor (473) and the pixel electrode (476).
0). On the other hand, a MOS capacitor (471) is formed between the gate (477) and the underlying silicon semiconductor using the gate insulating film as a dielectric. On the other hand, the metal wiring (475) is an extension of the image signal line.

In this embodiment, the gate of the MOS capacitor (47
1) and a capacitance is formed between the wiring (474) extending from the thin film transistors (472) and (473), and the MOS capacitance exists in parallel with the pixel electrode (476).
(C).

[Embodiment 8] FIG. 5 shows the steps of this embodiment. First, a base silicon oxide film (50) is formed on a substrate (501).
2) (2000 mm thick) was deposited, and an island region (503) was formed by a crystalline silicon film. Further, a gate insulating film (504) was formed thereon.

Thereafter, an aluminum film having a thickness of 5000 ° was formed by a sputtering method. In order to improve the adhesion to the photoresist in the subsequent porous anodic oxide film forming step, a thickness of 100 to 400
A thin anodic oxide film may be formed. Thereafter, a photoresist having a thickness of about 1 μm was formed by spin coating. Then, the gate electrodes (505), (506), and (50) are formed by a known photolithography method.
7) was formed by etching. On the gate electrode,
Photoresist masks (508), (509), (5)
10) was left. (FIG. 5 (A))

Next, the substrate is immersed in a 10% oxalic acid aqueous solution, and the + side of the constant current source is connected to the gate electrode (505) on the substrate.
(507), and a negative electrode was connected to a platinum electrode to perform anodic oxidation. At this time, 5 to 50 V, for example, 8
Anodizing is performed at a constant voltage of V for 10 to 500 minutes, for example, 200 minutes, so that the porous anodic oxides (511) and (512) having a thickness of 5000
05) and (507). The obtained anodic oxide was porous. Anodization hardly proceeded due to the presence of the mask materials (508) and (510) on the upper surface of the gate electrode. In addition, the gate electrode (506)
No anodic oxide was formed because no current was passed through. (FIG. 5 (B))

Thereafter, the mask material was removed to expose the upper surface of the gate electrode. Then, in the same manner as in Example 5, L-tartaric acid was diluted to a concentration of 5% in ethylene glycol, and the pH was adjusted to 7.0 ± 0.2 using ammonia. Anodization was performed by passing an electric current through 506) and (507) to form an anodic oxide having a thickness of 500 to 2500 °, for example, 2000 °. As a result, a dense aluminum oxide film (51 mm thick)
3), (514) and (515) were obtained.

After that, an impurity (here, phosphorus) was implanted into the island-shaped silicon region (503) in a self-aligned manner by using the gate electrode portion as a mask by ion doping to form an N-type impurity region. Here, diborane (B ₂ H ₆ ) was used as a doping gas. The dose in this case is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 4
0 to 90 kV, for example, a dose of 1 × 10 ¹⁵ cm ⁻² ,
The acceleration voltage was 65 kV. As a result, P-type impurity regions (516) to (519) were formed. (FIG. 5 (C))

Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to activate the doped impurity regions (516) to (519). Next, plasma C is used as an interlayer insulating film.
The silicon oxide film (520) is formed to a thickness of 3000
Was formed. Further, the interlayer insulating film (520) and the gate insulating film (504) were etched to form a contact hole in the P-type impurity region (516). afterwards,
An aluminum film was formed by a sputtering method and etched to form an image signal line (521). (FIG. 5
(D))

After that, a passivation film (522) is formed, and a passivation film (522) and an interlayer insulating film (5) are formed.
20), the gate insulating film (504) is etched, and a hole is formed on the anodic oxide film (514);
A contact hole for a pixel electrode was formed in the type impurity region (519). Then, ITO was formed and etched to form a pixel electrode (523). The pixel electrode (523) uses the anodic oxide film (514) as a dielectric to form the gate electrode (5).
06) and form a capacitor. Further, if the P-type impurity regions (517) and (518) are kept at the same potential, a MOS capacitor using the gate insulating film (504) as a dielectric between the gate electrode (506) and the silicon semiconductor thereunder is formed. It is formed. (FIG. 5E)

By the steps described above, the P-channel type thin film transistors (526) and (527) and the capacitor (52)
4) An active matrix circuit element having a MOS capacitor (525) was formed. In this embodiment, since the pixel electrode forms a capacitance with the gate of the MOS capacitor, the conductivity type of the transistor is opposite, but is the same as the circuit shown in FIG. 1A or 1B.

In the present embodiment, the offset width of the thin film transistors (526) and (527) for which the OFF current needs to be suppressed is wider than that of the fifth embodiment.
On the other hand, in the case of the MOS capacitor, the presence of the offset is not only unnecessary, but in some cases, it becomes a resistance component, which is not desirable for the circuit.

[0067]

As described above, the voltage drop of the liquid crystal cell can be suppressed by connecting a plurality of thin film transistors and an appropriate capacitor as shown in the present invention. In the present invention, in particular, the thin film transistor (2) shown in FIG.
The source / drain voltage of 22) is kept low in all driving processes. In general, the deterioration of a thin film transistor depends on the voltage between the source and the drain. Therefore, by using the present invention, the deterioration can be prevented.

The present invention is effective in applications requiring higher-level image display. In other words, when expressing extremely delicate shades of 256 gradations or more, it is necessary that the discharge of the liquid crystal cell be suppressed to 1% or less during one frame. In the conventional method, neither of FIGS. 2A and 2B is suitable for this purpose.

The present invention is also suitable for an active matrix display device using a crystalline silicon semiconductor thin film transistor particularly suitable for displaying a matrix having a large number of rows. Generally, in a matrix having a large number of rows, an amorphous silicon semiconductor thin film transistor is not suitable for use because the selection time per row is short. However, there is a problem that a thin film transistor using a crystalline silicon semiconductor has a large OFF current. Therefore, the present invention that can reduce the OFF current can make a great contribution in this field.

[Brief description of the drawings]

FIG. 1 shows an example of an active matrix circuit device according to the present invention.

FIG. 2 schematically shows an active matrix circuit according to the related art and the present invention.

FIG. 3 shows an example of the arrangement of semiconductor regions and gates according to the present invention.

FIG. 4 shows a manufacturing process of the active matrix circuit element in the embodiment.

FIG. 5 shows a manufacturing process of the active matrix circuit element in the embodiment.

FIG. 6 shows an outline of driving an active matrix circuit element according to the present invention.

[Explanation of symbols]

 101, 102 ... thin film transistor 103 ... thin film transistor (always on) 104 ... auxiliary capacitance 105 ... pixel cell 111, 112 ... thin film transistor 113 ... MOS capacitance 114 ... ··· Auxiliary capacitance 115 ···· Pixel cells 121 and 122 ··· Thin film transistor 123 ··· Capacitance 124 ···· Auxiliary capacitance (MOS capacitance) 125 ···· Pixel cells 131 and 132 ··· Thin film transistor 133 ··· MOS capacitance 134 ··· Auxiliary capacitance (MOS capacitance) 135 ··· Pixel cell

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Jun Koyama 398 Hase, Hase, Atsugi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd.

Claims (3)

[Claims] 1. An active matrix display device comprising:
A pixel electrode disposed in a matrix on a substrate; a thin film transistor is connected to the pixel electrode; and the thin film transistor has at least a gate in contact with a channel region, a source region, a drain region, and the channel region. An insulating film, and a gate electrode in contact with the gate insulating film. A capacitor is connected to the thin film transistor. The capacitor includes an electrode, an insulating film below the electrode, and an insulating film under the insulating film. An active matrix display device comprising: a semiconductor film; and the semiconductor film is formed of the same material as a channel region of the thin film transistor. 2. The active matrix type display device according to claim 1, wherein said insulating film forming a capacitor is made of the same material as a gate insulating film of a thin film transistor. 3. The active matrix type display device according to claim 1, wherein said electrode forming a capacitor is made of the same material as a gate electrode of a thin film transistor.