JP2001339074A - Optoelectronic device and active matrix device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optoelectronic device for reducing a leakage current. SOLUTION: In an optoelectronic device and active matrix device having a P-channel thin-film transistor, the P-channel thin-film transistor has structure where boron concentration contained in the channel region is equal to or less than 1017 cm-3, a channel semiconductor layer in contact with a ground insulating film is set to amorphous silicon, and an area on the amorphous silicon layer is set to crystalline silicon by heat-annealing the amorphous silicon. With the current-voltage characteristics of the P-channel thin-film transistor having the structure, the leakage current is equal to or less than 10-12 A when the drain voltage is equal to 1 V.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device or a dynamic RAM (DRAM) having a matrix structure and a MOS or MIS as a switching element.
(Metal-insulator-semiconductor) type field effect element (the above,
The present invention relates to a matrix device (including an electro-optical display device and a semiconductor memory device) having dynamic operation and having a driving circuit therefor. In particular, the present invention relates to an apparatus using a thin-film semiconductor element such as a thin-film semiconductor transistor formed on an insulating substrate as a MOS element.

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are intended to be used to control each pixel in a display device such as a liquid crystal having a matrix structure, and are distinguished as amorphous silicon TFTs or polycrystalline silicon TFTs depending on the material and crystal state of the semiconductor used. Have been. However, recently, research has been made on using a material exhibiting an intermediate state between polycrystalline silicon and amorphous. This material is
It is called semi-amorphous, and is considered to be a state in which small crystals float in an amorphous structure. This material is an excellent material having the characteristics of high mobility in a single crystal state and low leakage current in an amorphous state, as described later.

[0003] Also in a single-crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technique, which is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used.

Further, in a semiconductor circuit on an insulating substrate, since there is no capacitive coupling between the substrate and the wiring, an extremely high-speed operation is possible, and a technology for utilizing as an ultra-high-speed microprocessor or an ultra-high-speed memory has been proposed. .

In general, the electric field mobility of a semiconductor in an amorphous state is small, so that a TF required to operate at high speed is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, unlike a transistor of an active matrix of a liquid crystal, such a high-speed operation is not required, and only one conductivity type is sufficient, and T
It is used for applications where FT is required.

On the other hand, a polycrystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, a value as high as 300 cm ² / Vs is obtained as the electric field mobility. Since the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value,
The operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring. On the other hand, since the OS circuit is on an insulating substrate, there is no such restriction, and a remarkably high-speed operation is expected.

In polycrystalline silicon, the NMOS T
Since not only FT but also PMOS TFT can be obtained in the same manner, a CMOS circuit can be formed. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also peripheral circuits (drivers, etc.) are required. Also, there is known a device having a so-called monolithic structure constituted by a CMOS polycrystalline TFT.

The above-mentioned TFT used in the SRAM also pays attention to this point, and the PMOS is constituted by the TFT.
This is a load transistor.

Further, in a normal amorphous TFT, it is difficult to form a source / drain region by a self-alignment process as used in a single crystal IC technology, and it is difficult to form a gate electrode and a source / drain region. Parasitic capacitance due to the overlap is a problem,
Since a polycrystalline TFT can adopt a self-alignment process, it has a feature that a parasitic capacitance is remarkably suppressed.

[0011]

Some problems have been pointed out with respect to the advantages of the polycrystalline TFT having such characteristics. A general polycrystalline TFT is a coplanar type in which an active layer is formed on an insulating substrate, and a gate insulating film and a gate electrode are provided thereon. Although this structure has an advantage that a self-alignment process can be adopted, it is difficult to reduce a leak current (OFF current) of the active layer.

The details of the cause of the leakage current are not clear, but the major cause was the interface charge generated between the underlayer and the active layer. Therefore, this problem was solved by paying close attention to the preparation of this interface and reducing the interface state density to the same level as that between the gate oxide film and the active layer.

That is, in a high temperature process (maximum process temperature of about 1000 ° C.), quartz is used as a substrate, a silicon film is formed thereon,
After thermal oxidation at about 0 ° C. to form a clean surface, an active silicon layer was formed by a film forming method such as a low pressure CVD method.

Further, a low-temperature process (a maximum process temperature of 6
Process below 50 ° C. Also called medium temperature process. In (2), a method in which a silicon oxide film having a low interface state density as low as the gate insulating film is formed between the substrate and the active layer as a base film. As a method for forming the silicon oxide film, a sputtering method is excellent. In addition, ECR-CVD, TE
An oxide film having excellent characteristics can be obtained also by the plasma CVD method of the OS.

However, the leakage current could not be improved. In particular, the NMOS was one order of magnitude larger than the PMOS. The present inventors presumed that the cause was that the active layer was a weak N-type. Actually, a phenomenon in which the threshold voltages of the PMOS and NMOS fabricated in the high-temperature process and the low-temperature process shift in the negative direction was observed with good reproducibility. It is presumed that this is because, in particular, when silicon has a high purity and no other impurities are added, if the crystallinity is not good like amorphous silicon, the silicon becomes a weak N-type. It is speculated that high-temperature process polycrystalline silicon has many lattice defects and dangling bonds, unlike perfect single-crystal silicon, and these electrons serve as donors to supply electrons. Of course, the possibility of the influence of a small amount of contaminating elements (such as sodium) remains.

Anyway, if there is such a cause, NM
The threshold voltage of OS is significantly lower than that of PMOS,
The explanation is that the leakage current is large. This is shown in FIG. In the NMOS, as shown in FIG. 1A, a source 12 (N ⁺ type) is grounded, and a drain 13 (N ^+
When a voltage higher than the threshold voltage _Vth is applied to the gate electrode 11 while a positive voltage is applied to the
Although a channel is formed on the side of the gate electrode 4 and a drain current (solid line arrow in the figure) flows, since the active layer 14 is weak N-type (N ⁻ type),
A current that hardly depends on the gate voltage (a dotted arrow in the figure) is flowing.

If the potential of the gate electrode is equal to the threshold voltage V
Even when the current is less than _th , the current indicated by the dotted line flows. When the potential of the gate electrode becomes a large negative value, FIG.
As shown in (B), an inversion layer (P-type) 16 is formed, but the entire channel does not reach inversion. Conversely, when an excessive voltage is applied, electrons are accumulated on the opposite side of the gate, and the channel is turned off. It will be formed. N actually obtained
MOS data is consistent with this consideration.

On the other hand, in the PMOS, the threshold voltage becomes large because the active layer is of the N ⁻ type. However, the leakage on the other side of the gate is greatly reduced. FIG. 2 shows a case where a voltage lower than the threshold or a voltage higher than the threshold is applied to the PMOS.

Such a remarkable leak current in the NMOS has been an obstacle in various application fields, particularly in fields requiring dynamic operation. For example, in a liquid crystal active matrix or a DRAM, image information or stored information is lost due to leakage current. Therefore, it was necessary to reduce such a leak current.

One method is to make the active layer of the NMOS intrinsic (I
) Or a weak P-type. For example, when forming the active layer, only the NMOS or the NMOS and the PMO
When an appropriate amount of P-type impurity (for example, boron) is implanted into both of the S and the active layer of the NMOS is made I-type or weak P-type, the threshold voltage of the NMOS rises and the leak current is greatly reduced. Should do it. However, this method has several problems.

Normally, NMOS and PMO are mounted on one substrate.
A CMOS circuit in which S is also mounted is used, but if an impurity is implanted only in the N-type, an extra photolithography step is required. Also, NMOS and PMO
If a P-type impurity is to be implanted into both the active layers of S, a delicate impurity implantation technique is required. If the amount of injection is too large, the threshold voltage of the PMOS will decrease, and the leakage current will increase.

[0022] Ion implantation techniques are also problematic. In the implantation technique for performing mass separation, it is possible to implant only necessary impurity elements, but the processing area is small. In addition, although the so-called ion doping method has a large processing area, unnecessary ions may be implanted due to the absence of a mass separation step, and the doping amount may not be accurate.

Further, such a method of accelerating and implanting ions causes formation of localized levels at the interface between the active layer and the base. Further, unlike the conventional ion implantation for a single crystal semiconductor, since the implantation is performed on an insulating substrate, the charge-up phenomenon is remarkable, and it is difficult to precisely control the implantation amount.

Therefore, it is conceivable to mix P-type impurities in advance when forming the active layer. However, it is difficult to control the amount of trace impurities. In the case of PMO,
Increase the leakage current of S, and increase the NMOS and PMOS
When a is formed from a different film, an additional mask process is required. In addition, controlling the threshold voltage by such a method depends on factors such as gas flow rate and the like.
The variation in the threshold value of the FT occurs, and the variation in the threshold value for each lot becomes significantly large.

The present invention seeks to provide a solution to such a difficult problem. The gist of the present invention is not to reduce the leakage current of the NMOS by the process but to design the circuit. By designing a circuit, a circuit that can be used even with a TFT having a large leak current is designed. As described above, when the active layer is formed of a high-purity silicon material, the active layer becomes N ⁻ -type, but its energy level is extremely reproducible and stable. In addition, the process itself is extremely simple, and the yield is sufficiently high. On the other hand, various methods for controlling the threshold voltage not only complicate the process, but also vary the energy level (Fermi level, etc.) of the obtained active layer for each lot, and lower the yield. I do.

Clearly, the process improvement has resulted in NMO
A process in which impurities are eliminated as much as possible is easier than adjusting S to a circuit, that is, performing a delicate doping of about 10 ¹⁷ cm ^-3 , and designing a circuit according to the resulting NMOS. Is better. Here is the technical idea of the present invention.

[0027]

A semiconductor circuit to which the present invention is applied is not universal. The present invention utilizes a material, such as a liquid crystal display device, whose light transmittance and reflectivity change due to the effect of an electric field, sandwiches these materials between opposing electrodes, and applies an electric field between the opposing electrodes. An active matrix circuit for displaying an image, a memory device such as a DRAM for storing data by accumulating electric charges in a capacitor, and an M
It is suitable for a circuit having a dynamic circuit such as a dynamic shift register for driving a next-stage circuit by using the OS structure as a capacitor or by using another capacitor. In particular, the present invention is suitable for a circuit in which a dynamic circuit and a static circuit are mixed.

One example of the present invention is that a display portion of an active matrix circuit such as a liquid crystal is provided with a PMOS TFT.
Is used as a switching transistor.
Here, it is necessary that the PMOS TFT is inserted in series with the data line and the pixel electrode,
If the TFTs are inserted in parallel, it is not suitable for the purpose of display such as because of a large leak current. Therefore, the present invention includes a case where PMOS and NMOS TFTs are inserted in series in a pixel TFT circuit. Of course, it is within the technical scope of the present invention that two PMOS TFTs are inserted in parallel.

A second example of the present invention is that a driving circuit is a CMOS circuit in an apparatus having the above-described display circuit section (active matrix) and its driving circuit (peripheral circuit). In this case, all of the circuits are CMOS
However, it is desirable that the transmission gate and the inverter circuit be CMOS. FIG. 3 shows a conceptual diagram of such an apparatus. In the figure, a data driver 31 and a gate driver 32 are formed on an insulating substrate 37, and an active matrix 33 having a PMOS TFT is formed in the center. The driver section and the active matrix are connected to a gate line 35 and a data line. Line 3
The display devices connected by 6 are shown. The active matrix 33 is an aggregate of pixel cells 34 having a PMOS.

As for the CMOS circuit, for example, the threshold voltage of the obtained TFT is 2 V for NMOS and PMO
6V for S, and PMO for leakage current of NMOS
Even if it is more than 10 times larger than S, there is no problem in the CMOS inverter.

This is because in a logic circuit such as an inverter, power consumption due to leakage does not matter much. The operation of the inverter is NM in the low voltage state.
The threshold voltage of the OS is lower than the threshold voltage, and the high voltage state is required to be higher than the sum of the drain voltage and the threshold voltage of the PMOS (<0). In this case, the drain voltage is 8 V or higher, ideally If the voltage is 10 V or more, there is no problem. For example, it is sufficient to set the input to two values of 0 V and 8 V.

The third example of the present invention relates to a semiconductor memory such as a DRAM. Semiconductor memory devices have already reached their speed limit with single crystal ICs. To operate at higher speeds than this, it is necessary to increase the current capacity of the transistor, but this not only causes a further increase in the current consumption, but also in particular, stores the charge by storing the charge in the capacitor. For a DRAM that operates, the only way to deal with this is by increasing the drive voltage, as the capacitance of the capacitor cannot be increased any further.

It is said that the single crystal IC has reached the speed limit because, in part, a large loss occurs due to the capacitance of the substrate and the wiring. If an insulator is used for the substrate, sufficiently high-speed driving can be performed without increasing current consumption. For this reason, an IC having an SOI (semiconductor on insulator) structure has been proposed.

In the case of a 1Tr / cell structure, the DRAM has almost the same circuit configuration as that of the above-described liquid crystal display device.
Cell structure), a PMOS TFT having a small leakage current is used for the TFT in the storage bit portion. The basic block configuration is the same as that of FIG. For example, in a DRAM, 31 is a column decoder, 32 is a row decoder, 33 is a storage element unit, 34 is a unit storage bit, 35 is a bit line, 36 is a word line, and 37 is an (insulated) substrate.

The active matrix of the liquid crystal display device is also D
All RAMs also require a refresh operation, but during the refresh period, the TFTs must be sufficiently charged so that the charges stored in the pixel capacitance and the capacitor capacitance are not discharged. It must function as a large resistor. If an NMOS TFT is used in this case, sufficient driving cannot be performed due to a large leak current. This is an advantage of using a PMOS TFT having a low leakage current.

In the present invention, a TFT of a high temperature process is effective, but a TFT of a low temperature process is particularly effective. The TFT obtained by the low-temperature process has an active layer having an intermediate structure between an amorphous layer and a single crystal layer, and has a large lattice distortion, and is in a so-called semi-amorphous state. That is, an active layer made of a pure silicon material by a low-temperature process is usually of the N ⁻ type.

Here, a detailed description of the semi-amorphous state will be given. Silicon in the amorphous state starts crystal growth as heat is applied, but does not reach the state of crystal growth up to about 650 ° C. under atmospheric pressure.
That is, there is a relatively poorly crystalline part between the parts with good crystallinity, and the bonds between the molecules are tight,
It shows a different aspect from the crystal precipitation in a normal ionic crystal. In other words, dangling bonds
Is characterized by an extremely small number. If the crystal growth is 6
When the temperature exceeds 80 ° C., the growth rate of the crystal is remarkably accelerated, and a polycrystalline state composed of many crystal grains is obtained. In this case, the molecular bonds at the crystal grain boundaries that have been buffered by the lattice distortion are broken, and a large number of dangling bonds are formed at the grain boundaries.

Now, in such a semi-amorphous material, even if the active layer is doped with impurities,
As in the case of amorphous silicon, it does not contribute much to activation. The inventor of the present invention thinks that the cause is that the dopant impurities are selectively trapped particularly in a portion having many dangling bonds. Therefore, in an active layer in a semi-amorphous state or an active layer formed by a low-temperature process, it is difficult to control the threshold voltage by doping.

The present invention is also effective in a TFT having two active layers as described in Japanese Patent Application No. 4-73315 which is an invention of the present inventors. In this TFT, an active layer in an amorphous state is provided on the substrate side, and an active layer in a semi-amorphous or polycrystalline state is provided on the active layer. The leakage generated by the charge existing at the interface between the substrate and the active layer is minimized. Can be reduced. However, the lower active layer is N ^- type because of the use of amorphous silicon in structure. Therefore, even though the leakage due to the interface can be reduced, the leakage due to the active layer cannot be easily reduced. For example, even if the leakage current is 10 ⁻¹² A or less (drain voltage 1 V) in the PMOS, the leakage current is 100 times or more that in the NMOS.

The manufacturing method is illustrated in FIG. First,
On the substrate 41, a film 42 having a strong passivation force such as silicon nitride is formed. If the substrate is sufficiently clean, such a film need not be formed. Furthermore, the base oxide film 4
Form 3 Then, two amorphous silicon films are formed. By optimizing the deposition rate and the deposition substrate temperature, it is determined whether the amorphous silicon film remains in an amorphous state, becomes semi-amorphous or becomes polycrystalline by a subsequent heat treatment. You. In this example, the upper layers 45 and 47 become semi-amorphous (or polycrystalline), and the lower layers 44 and 47 become
47 remains amorphous.

A feature of such a method is that, while film formation is performed using the same chamber, two types of silicon films having different properties can be formed by slightly changing the conditions. Threshold voltage control will undermine the advantages of this method. if,
If one attempts to change the underlying layers 44, 46 from N ^- type to I-type, this layer remains amorphous and therefore has a poor ionization rate and requires heavy doping. Therefore, there is a possibility that the chamber is significantly contaminated by these impurities, and conversely, the active layer of the PMOS becomes P-type. Therefore, a TFT having such an active layer having a two-layer structure is extremely suitable for the present invention which does not require threshold voltage control by doping. A method for forming such a TFT will be described in detail in Examples.

[0042]

[Embodiment 1] FIG. 4 shows a CMO using the present invention.
An example of manufacturing the S circuit will be described. In this embodiment, the substrate 41
A Corning 7059 glass substrate was used. Various other types of substrates can be used, but it is necessary to take measures according to the substrate so that mobile ions such as sodium do not enter the semiconductor film. The ideal substrate is a synthetic quartz substrate with a small alkali concentration, but if it is difficult to use it cost-effectively,
Commercially available low alkali glass or non-alkali crow will be used. In this embodiment, the thickness of the substrate 41 is set to 5 to 2 in order to prevent mobile ions from entering the substrate 41.
A silicon nitride film 42 having a thickness of 00 nm, for example,
Formed by Method D. Further, a silicon oxide film 43 having a thickness of 20 to 1000 nm, for example, 50 nm was formed on the silicon nitride film by a sputtering method. The thickness of these films is designed according to the degree of penetration of mobile ions or the degree of influence on the active layer.

For example, the quality of the silicon nitride film 42 is not good.
When the charge trap is large, the upper semiconductor layer is affected through the silicon oxide film. In this case, the silicon oxide film 43 needs to be thickened.

These films may be formed not only by the above-described low pressure CVD method or sputtering method but also by a method such as plasma CVD method. In particular, TEOS may be used for forming the silicon oxide film. The selection of these means may be determined in consideration of investment scale, mass productivity, and the like. Needless to say, these films may be continuously formed.

Thereafter, a monosilane is used as a raw material, and a thickness of 20 to 200 nm, for example, 100
A nm-thick amorphous silicon film was formed. The substrate temperature was 430 to 480 ° C, for example, 450 ° C. Further, the substrate temperature was continuously changed, and an amorphous silicon film having a thickness of 5 to 200 nm, for example, 10 nm was formed at 520 to 560 ° C., for example, 550 ° C. As a result of the study of the present inventors, it has been revealed that the substrate temperature has an important influence upon the subsequent crystallization. For example, it was difficult to crystallize a film formed at 480 ° C. or lower. 520 ° C
Films formed at the above temperatures were easily crystallized. The amorphous silicon film thus obtained has a thickness of 600
Thermal annealing at 24 ° C. for 24 hours. As a result, only the upper silicon film was crystallized, and crystalline silicon referred to as so-called semi-amorphous silicon was obtained. On the other hand, the lower silicon film remained in an amorphous state.

In order to promote crystallization of the upper silicon film, it is desirable that the concentrations of carbon, nitrogen and oxygen contained in the film are all 7 × 10 ¹⁹ cm ⁻³ or less. In this example, it was confirmed by SIMS analysis that it was 1 × 10 ¹⁷ cm ⁻³ or less. Conversely, in order to suppress crystallization of the lower silicon film, it is convenient that these elements are contained in a large amount. However, excessive doping has an adverse effect on semiconductor characteristics and, consequently, TFT characteristics. Therefore, the presence or absence and the amount of doping are designed in accordance with the characteristics of the TFT.

Now, the amorphous silicon film is thermally annealed.
After forming a crystalline silicon film with
Etching to a simple pattern, island-shaped semiconductor for NTFT
A region 45 and an island-shaped semiconductor region 47 for PTFT are formed.
You. Above each island-shaped semiconductor region, an intentional impurity
In particular, the concentration of impurities such as boron is 10¹⁷cm ^-3
The following facts are reported to SIMS (Secondary Ion Mass Spectrometry)
Therefore, it was confirmed. Therefore, the conductivity type of this part is N
^-Inferred to be a type. On the other hand, the lower part of each semiconductor region
The silicon layers 44 and 46 are substantially amorphous silicon
Met.

Thereafter, a gate insulating film (silicon oxide) 48 is formed to a thickness of 50 to 300 nm, for example, 100 nm by a sputtering method using silicon oxide as a target in an oxygen atmosphere.
Only formed. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum film having a thickness of 500 nm was formed by a sputtering method, and this was patterned with a mixed acid (a phosphoric acid solution to which 5% nitric acid was added) to form gate electrodes / wirings 49 and 50. The etching rate is 225 when the etching temperature is 40 ° C.
nm / min. Thus, the outer shape of the TFT was adjusted. At this time, the size of each channel is 8
μm and a width of 20 μm. The state at this time is shown in FIG.
Shown in

Further, aluminum oxide was formed on the surface of the aluminum wiring by anodic oxidation. The method of anodic oxidation is disclosed in Japanese Patent Application No. 3-23, which is an invention of the present inventors.
1188 or the method described in Japanese Patent Application No. 3-238713. A detailed embodiment may be changed depending on the characteristics of the target device, process conditions, investment scale, and the like. In this example, aluminum oxide films 51 and 52 having a thickness of 250 nm were formed by anodic oxidation.

After that, the N-type source / drain region 53 and the P-type source / drain region 5 are formed by an ion implantation method through a gate oxide film with the aid of a well-known CMOS fabrication technique.
4 was formed. In each case, the impurity concentration is 8 × 10 ¹⁹ cm ^−3.
It was made to become. As the ion source, boron fluoride ions were used for the P type and phosphorus ions were used for the N type. The former was implanted at an acceleration voltage of 80 keV, and the latter was implanted at an acceleration voltage of 110 keV. The accelerating voltage depends on the thickness of the gate oxide film, the semiconductor region 45,
47 is set in consideration of the thickness. Instead of the ion implantation method, an ion doping method may be used. In the ion implantation method, unnecessary ions are not implanted because ions to be implanted are separated by mass, but the size of a substrate that can be processed by the ion implantation apparatus is limited. On the other hand, in the ion doping method, although a relatively large substrate (for example, a diagonal of 30 inches or more) is capable of being processed, hydrogen ions and other unnecessary ions are simultaneously accelerated and implanted, so that the substrate is easily heated. . In this case, it is difficult to selectively implant impurities using a photoresist as a mask as used in the ion implantation method.

In this way, a TFT having an offset region was manufactured. This is shown in FIG. Finally, the source / drain regions were recrystallized by laser annealing using the gate electrode as a mask. The conditions for laser annealing are described, for example, in Japanese Patent Application No. Hei.
1188 and 3-238713. As the interlayer insulator 55, silicon oxide is R
An F-plasma CVD method was used, holes for forming electrodes were formed in the F-CVD, and aluminum wirings 56 to 48 were formed to complete the device.

In this embodiment, the films 45 and 47, which were originally crystalline silicon, were formed by laser annealing.
Not only that, the coating 44 made of amorphous silicon,
Up to 46 are crystallized. This is because laser annealing is powerful. As a result, as shown in FIG. 4C, all of the initial amorphous regions 44 and 46 except for the portions 59 and 60 below the channel were converted into materials having the same crystallinity as the source / drain. As a result, the thickness of the source / drain was substantially the same as that of the island-shaped semiconductor regions 45 and 47. However, the effective channel thickness was less than the source / drain regions, as apparent from the figure, at about 10 nm. As a result, it was possible to exhibit excellent characteristics such that the sheet resistance of the source / drain was small and the OFF current was small because the channel was thin.

FIG. 4 shows a manufacturing process of a CMOS circuit used for a driving circuit of a liquid crystal display device. In the active matrix portion on the same substrate, a PMOS is similarly formed. The characteristics of the TFT thus formed were as follows: the channel length was 5 μm, the channel width was 20 μm, the source / drain voltage was 1 V, the leakage current of the NMOS was １００100 pA, and the PMOS was 〜1 pA of the PMOS. . As described above, the off-state resistance of the PMOS was 100 times larger. When the gate voltage is +8 V (−8 V in the case of PMOS), the NMOS is 10 μA,
The PMOS passed a current of 100 nA. The reason why the drain current of the PMOS is significantly smaller than that of the NMOS is that the threshold voltage is negatively shifted in the case of the PMOS. Therefore, the gate voltage of the PMOS is set to -12V
, The drain current was 1 μA. That is, if a transmission gate is formed using such a TFT, the potential applied to the PTFT should be shifted to the negative side.

The PMOS TF of the active matrix section
T has a channel length of 5 μm and a channel width of 10 μm
And PMO used as active matrix
Gate voltage of S TFT changed from 0V to -12V
The drain current is 10 ⁶Because it increases by a factor of two,
There was no problem for image display. In addition,
If necessary, two PMOS TFTs
If it is configured in series and has a so-called dual gate structure
Good. In this case, in the off state, the resistance of the TFT is small.
In the ON state, the resistance of the TFT increases by about one digit.
Since the resistance is only about twice, the drain current
Is 10⁷Will also fluctuate. Three-stage TFTs in series
Once done, the rate of change will increase by an order of magnitude.

[Embodiment 2] FIG. 5 shows a process of fabricating an NMOS and a PMOS device for carrying out the present invention. In this example, a TFT was manufactured by a high-temperature process. First, a quartz substrate 61 (width 105 mm × length 105 m)
m × thickness 1.1 mm), a low-pressure CVD method is used to deposit a non-doped polysilicon film having a thickness of 100 mm.
To 500 nm, preferably 150 to 200 nm. This was oxidized in a dry high-temperature oxygen atmosphere. The temperature is in the range of 850 to 1100 ° C.
0-1050 ° C. was particularly preferred. In this way,
A silicon oxide film 62 was formed on the substrate (FIG. 5A).

Further, a plasma C using disilane as a raw material
An amorphous silicon film is formed to a thickness of 100 to 1000 nm, preferably 35
It was formed in a thickness of 0 to 700 nm. Substrate temperature is 350-450 ° C
And Then, this was annealed at 550 to 650 ° C., preferably 580 to 620 ° C. for a long time to have crystallinity. Then, this is patterned, and FIG.
As shown in the figure, the NMOS region 63a and the PMOS region 6
3b was formed.

Next, the surface of the silicon region 63 is oxidized in a dry and high-temperature oxidizing atmosphere, so that the surface of the silicon region has a thickness of 50 to 150 nm as shown in FIG.
m, preferably a silicon oxide film 64 having a thickness of 50 to 70 nm. The oxidation conditions were the same as those of the silicon oxide 62.

After that, the phosphorus was 10 ¹⁹ to 2 × 10 ²⁰ c
m ⁻³ , for example, 8 × 10 ¹⁹ cm ⁻³ doped silicon film having a thickness of 200 to 500 nm, preferably 350 to 400 nm.
5 nm, and this was patterned as shown in FIG. 5D to form an NMOS gate 65a and a PMOS gate 65b. Furthermore, by ion implantation,
NMOS and PMOS impurity regions 66 and 67 were formed, respectively.

At this time, the bottom surfaces of these impurities were prevented from reaching the underlying silicon oxide film 62. That is, many localized levels are formed at the interface between the underlying oxide film and the silicon film, and as a result, the silicon film near the underlying oxide film has a specific conductivity type (N-type in a normal case). If the impurity region is adjacent to such a portion of the silicon film, a leak occurs. Therefore, in this embodiment, a space of 50 to 200 nm is provided between the bottom surface of the impurity region and the base oxide film 62 in order to avoid such a leak.

In this embodiment, the ion implantation is performed through the silicon oxide film 64. However, in order to more precisely control the depth of the impurity region, the silicon oxide film 64 may be removed and thermal diffusion may be performed. Good.

After the formation of the impurity regions, the crystallinity of the impurity regions was recovered by thermal annealing. After that, an interlayer insulator (phosphorus glass) 68 was deposited, flattened by reflow, and a contact hole was formed to form metal wirings 69 to 71 in the same manner as in a normal TFT manufacturing process.

A 1Tr / cell DRAM (16 kbits) was manufactured using the TFTs formed by the above steps. The channel length of the TFT is set to the channel length 2
When the source / drain voltage is 1 V, the leakage current of the NMOS is about 10 pA when the channel width is 10 μm, and the leakage current of the PMOS is about 0.3 μm under the same conditions.
It was 1 pA. The memory element has a channel length of 2 μm,
A PMOS having a channel width of 2 μm was used. The capacity of the capacitor in the memory element portion was set to 0.5 pF, and the refresh cycle could be held for a long time of a maximum of 5 seconds. This is because the PMOS off-state resistance is 5 × 10 ¹³ Ω
It was possible because of the high value. In addition, the peripheral circuit was made CMOS using the NMOS and PMOS fabricated in the above steps. DRA on such an insulating substrate
M, high-speed operation is possible, and 1 per bit
Writing / reading was possible in 00 nsec.

[0064]

According to the present invention, the reliability and performance of particularly dynamic circuits and devices having such circuits can be increased. Conventionally, polycrystalline TFTs have a low ON / OFF ratio, particularly for purposes such as the active matrix of a liquid crystal display device, and there have been various difficulties in practical use. However, such problems are almost solved by the present invention. It seems that it was done. Further, as shown in Embodiment 2, the semiconductor circuit on the insulating substrate is excellent in high-speed operation. Although not shown in the examples, it will be apparent that the effects can be obtained by implementing the present invention in a TFT used as a means for forming a three-dimensional single crystal semiconductor integrated circuit.

For example, a peripheral logic circuit is constituted by a semiconductor circuit on a single crystal semiconductor, and a TF is formed thereon via an interlayer insulator.
T may be provided to form a memory element portion. In this case, the memory element section is a DRAM circuit using a PMOS TFT, and the driving circuit is formed by converting a single crystal semiconductor circuit into CMOS. Moreover, when such a circuit is used for a microprocessor, the memory section is raised to the second floor, so that the area can be saved. Thus, the present invention is considered to be an industrially extremely useful invention.

[Brief description of the drawings]

FIG. 1 shows a conceptual diagram of the operation of an NMOS TFT.

FIG. 2 shows a conceptual diagram of the operation of a PMOS TFT.

FIG. 3 shows a conceptual diagram of the configuration of the present invention.

FIG. 4 shows a manufacturing process of the TFT of the present invention.

FIG. 5 shows a manufacturing process of the TFT of the present invention.

[Explanation of symbols]

11, 21 ... gate electrode 12, 22 ... source region 13, 23 ... drain region 14, 24 ... active layer 15, 25 ... channel 16, 26 ... inversion layer 31 ... data Driver (column decoder for DRAM) 32 Gate driver (row decoder for DRAM) 33 Active matrix section (storage element section for DRAM) 34 Unit pixel (DRAM Is a unit storage bit) 35 ... gate line (bit line in case of DRAM) 36 ... data line (word line in case of DRAM) 37 ... insulating substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 618F

Claims (24)

[Claims] 1. An electro-optical device having a P-channel thin film transistor, wherein the P-channel thin film transistor has a drain voltage of 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 2. An electro-optical device having a P-channel thin film transistor and a capacitor, wherein the capacitor is connected to the P-channel thin film transistor, and the drain voltage of the P-channel thin film transistor is 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 3. An electro-optical device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate electrode formed on the gate insulating film, wherein the channel forming region contains boron at a concentration of 10 ¹⁷ cm ^-3 or less; Type thin film transistor drain voltage is 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 4. An electro-optical device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate insulating film formed, and a gate electrode formed on the gate insulating film, wherein the channel forming region includes an amorphous silicon layer;
The P-channel type thin film transistor is formed of a crystalline silicon layer formed on the amorphous silicon layer.
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 5. An electro-optical device comprising: a substrate having an insulating surface; a pixel electrode formed on the insulating surface; and a MOS transistor connected to the pixel electrode, wherein the MOS transistor contains a P-type impurity. Having a source region, a drain region, and a channel forming region, wherein when a drain voltage of the MOS transistor is 1 V, a leak current is 10 ⁻¹² A or less; and a channel forming region of the MOS transistor includes an amorphous silicon layer and An electro-optical device comprising a crystalline silicon layer formed on the amorphous silicon layer. 6. A substrate; a silicon nitride film formed on the substrate; a silicon oxide film formed on the silicon nitride film; a plurality of pixel electrodes formed above the substrate; In an electro-optical device having a thin film transistor electrically connected to the thin film transistor, the thin film transistor is formed on the silicon oxide film, and includes a silicon film having a source region, a drain region, and a channel formation region; A gate insulating film formed, and a gate electrode formed in contact with the gate insulating film, wherein the channel forming region contains boron at a concentration of 10 ¹⁷ cm ⁻³ or less; The drain voltage of the channel type thin film transistor is 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 7. An electro-optical device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate electrode formed on the gate insulating film; and a P-type impurity in the channel forming region at 10 ¹⁷ cm ^−3.
And the drain voltage of the P-channel thin film transistor is 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 8. A substrate, a silicon nitride film formed on the substrate, a silicon oxide film formed on the silicon nitride film, a plurality of pixel electrodes formed above the substrate, In an electro-optical device including a thin film transistor that is electrically connected, the thin film transistor is formed over the silicon oxide film, and includes a silicon film having a source region, a drain region, and a channel formation region; A gate electrode formed in contact with the gate insulating film; and a P-type impurity in the channel formation region at 10 ¹⁷ cm ^−3.
And the drain voltage of the P-channel thin film transistor is 1
The electro-optical device according to claim 1, wherein the leakage current at V is 10 ^-12 A or less. 9. The electro-optical device according to claim 1, wherein the thin film transistor has a dual gate structure. 10. The electro-optical device according to claim 1, wherein a capacitor is connected to the P-channel thin film transistor. 11. The electro-optical device according to claim 1, wherein the electro-optical device has a peripheral circuit, and the peripheral circuit is a CMOS circuit. 12. The electro-optical device according to claim 6, wherein the silicon film contains polycrystalline silicon or single-crystal silicon. 13. An active matrix device having a P-channel thin film transistor, wherein the P-channel thin film transistor has a drain voltage of 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 14. An active matrix device having a P-channel thin film transistor and a capacitor, wherein the capacitor is connected to the P-channel thin film transistor, and a drain voltage of the P-channel thin film transistor is 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 15. An active matrix device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate electrode formed on the gate insulating film, wherein the channel forming region contains boron at a concentration of 10 ¹⁷ cm ^-3 or less; Type thin film transistor drain voltage is 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 16. An active matrix device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate insulating film formed, and a gate electrode formed on the gate insulating film, wherein the channel forming region includes an amorphous silicon layer;
The P-channel type thin film transistor is formed of a crystalline silicon layer formed on the amorphous silicon layer.
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 17. An active matrix device comprising: a substrate having an insulating surface; a pixel electrode formed on the insulating surface; and a MOS transistor connected to the pixel electrode, wherein the MOS transistor has a P-type impurity. Having a source region, a drain region, and a channel forming region, wherein when a drain voltage of the MOS transistor is 1 V, a leak current is 10 ⁻¹² A or less; and a channel forming region of the MOS transistor includes an amorphous silicon layer and An active matrix device comprising a crystalline silicon layer formed on the amorphous silicon layer. 18. A substrate, a silicon nitride film formed on the substrate, a silicon oxide film formed on the silicon nitride film, a plurality of pixel electrodes formed above the substrate, In an active matrix device including an electrically connected thin film transistor, the thin film transistor is formed over the silicon oxide film, and includes a silicon film having a source region, a drain region, and a channel formation region; A gate insulating film formed, and a gate electrode formed in contact with the gate insulating film, wherein the channel forming region contains boron at a concentration of 10 ¹⁷ cm ⁻³ or less; The drain voltage of the channel type thin film transistor is 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 19. An active matrix device having a P-channel thin film transistor, wherein the P-channel thin film transistor is formed on an insulating surface and has a source region, a drain region, and a channel formation region; A gate electrode formed on the gate insulating film; and a P-type impurity in the channel forming region at 10 ¹⁷ cm ^−3.
And the drain voltage of the P-channel thin film transistor is 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 20. A substrate, a silicon nitride film formed on the substrate, a silicon oxide film formed on the silicon nitride film, a plurality of pixel electrodes formed above the substrate, In an active matrix device including an electrically connected thin film transistor, the thin film transistor is formed over the silicon oxide film, and includes a silicon film having a source region, a drain region, and a channel formation region; A gate electrode formed in contact with the gate insulating film; and a P-type impurity in the channel formation region at 10 ¹⁷ cm ^−3.
And the drain voltage of the P-channel thin film transistor is 1
An active matrix device, wherein a leakage current at V is 10 ^-12 A or less. 21. The method of claim 13, 14, 15, 16, or 19.
The active matrix device according to any one of claims 1 to 3, wherein the thin film transistor has a dual gate structure. 22. The active matrix device according to claim 13,14, 16 or 19, wherein a capacitor is connected to said P-channel type thin film transistor. 23. The active matrix device according to claim 13, wherein the active matrix device has a peripheral circuit, and the peripheral circuit is a CMOS circuit. 24. The active matrix device according to claim 18, wherein the silicon film contains polycrystalline silicon or single crystal silicon.