JP3291038B2 - Method for manufacturing semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit and a method for manufacturing the same. Specifically, a liquid crystal display device or a dynamic R
Like an AM (DRAM), it has a matrix structure, and has a MOS or MIS (metal-
A matrix device (including an electro-optical display device and a semiconductor memory device) having an insulator-semiconductor type field effect element (the above is generally referred to as a MOS element) and performing a dynamic operation; And a driving circuit therefor, or a semiconductor circuit having an integrated driving circuit such as an image sensor. In particular, the present invention relates to an apparatus using a thin film semiconductor element such as a thin film semiconductor transistor formed on an insulating surface as a MOS element, and particularly to an apparatus having a polysilicon thin film transistor in which an active layer of the thin film transistor is formed of polysilicon.

[0002]

2. Description of the Related Art In recent years, studies have been made on an insulating gate type semiconductor device having a thin-film active layer (also called an active region) on an insulating substrate. In particular, a thin film insulated gate transistor, a so-called thin film transistor (TFT), has been enthusiastically studied. These are formed on a transparent insulating substrate and used for controlling each pixel in a display device such as a liquid crystal having a matrix structure, or used for a driving circuit of an image sensor similarly formed on an insulating substrate. The purpose is to distinguish between amorphous silicon TFT and polysilicon (also referred to as polycrystalline silicon) TFT depending on the material and crystal state of the semiconductor to be used.

[0003] Recently, however, studies have been made on the use of a material exhibiting an intermediate state between polysilicon and amorphous. Intermediate states have been discussed, but are described herein in some thermal processes, for example,
Any material that reaches a certain crystalline state by thermal annealing at a temperature of 450 ° C. or more or irradiation with strong energy such as laser light is referred to as polysilicon.

[0004] Also in a single crystal silicon integrated circuit, a polysilicon TFT is used as a so-called SOI technique, and this is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used.

Further, in a semiconductor circuit on an insulating substrate, since there is no capacitive coupling between the substrate and the wiring, an extremely high-speed operation is possible, and a technology for utilizing as an ultra-high-speed microprocessor or an ultra-high-speed memory has been proposed. .

Generally, the electric field mobility of a semiconductor in an amorphous state is small, and therefore, a TF which requires high-speed operation is required.
Not available for T. Further, in the case of amorphous silicon, the P-type electric field mobility is extremely small, so that a P-channel TFT (PMOS TFT) cannot be manufactured.
T) and complementary MOS circuit (CMOS)
Cannot be formed.

However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, such as an active matrix transistor of a liquid crystal display having a small matrix scale, such a high speed operation is not required, and only one conductivity type is sufficient and a TFT having a high charge retention capability is required. It is used for However, it has been difficult to use amorphous silicon TFTs for more advanced applications, for example, large-scale matrix liquid crystal displays. Naturally, it cannot be used for a peripheral circuit of a display or a driving circuit of an image sensor which requires a high-speed operation. In addition, although it has the same matrix configuration, it has been difficult to use it for a semiconductor memory device.

On the other hand, a polycrystalline semiconductor has a higher electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, a value as high as 300 cm ² / Vs is obtained as the electric field mobility. Since the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value,
The operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring. On the other hand, since the OS circuit is on an insulating substrate, there is no such restriction, and a remarkably high-speed operation is expected.

In polysilicon, the NMOS TF
Since not only T but also PMOS TFT can be obtained in the same manner, a CMOS circuit can be formed. For example, in an active matrix type liquid crystal display device, not only an active matrix portion but also peripheral circuits (drivers and the like) are required. Also, there is known a device having a so-called monolithic structure constituted by a CMOS polycrystalline TFT. The TFT used in the above-mentioned SRAM also pays attention to this point, and the PMOS is constituted by the TFT, which is used as a load transistor.

Further, in a normal amorphous TFT, it is difficult to form a source / drain region by a self-alignment process as used in a single crystal IC technology, and it is difficult to form a gate electrode and a source / drain region. Parasitic capacitance due to the overlap is a problem,
Polysilicon TFTs can adopt a self-aligned process, and thus have the characteristic that parasitic capacitance is significantly reduced.

However, the polysilicon TFT has a larger leakage current when no voltage is applied to the gate (when not selected) than the amorphous silicon TFT, and when used in a liquid crystal display, it needs to compensate for this leakage current. In order to reduce the leakage current, an auxiliary capacitor is provided, and two TFTs are connected in series.

For example, if a high OFF resistance of an amorphous silicon TFT is used and a peripheral circuit of a polysilicon TFT having a high mobility is monolithically formed on the same substrate, amorphous silicon is formed. Has been proposed to selectively irradiate a laser to crystallize only peripheral circuits.

However, at present, the yield is low due to the reliability problem of the laser irradiation process (for example, the in-plane uniformity of the irradiation energy is low), and the amorphous silicon TFT having low mobility is provided in the active matrix region. Therefore, it was difficult to use the software more advancedly. For the laser irradiation process, more reliable and lower cost thermal annealing was desired.
In order to increase the added value of products, at least TFT
Was desired to be 5 cm ² / Vs.

[0014]

Although the present invention seeks to provide an answer to such a difficult problem, it is not desirable that the process becomes complicated, resulting in a decrease in yield and an increase in cost. . The gist of the present invention is to easily fabricate two types of TFTs, a TFT requiring a high mobility and a TFT requiring a low leakage current, while maintaining mass productivity by minimizing a process change. Is to divide.

[0015]

A semiconductor circuit to which the present invention is applied is not universal. The present invention utilizes a material, such as a liquid crystal display device, whose light transmittance or reflectivity changes due to the effect of an electric field, sandwiches these materials between opposing electrodes, and applies an electric field between the opposing electrodes. And an active matrix circuit for displaying an image, a memory device such as a DRAM for storing data by accumulating electric charges in a capacitor, and an M
A circuit having a dynamic circuit such as a dynamic shift register that drives the next-stage circuit by using the OS structure as a capacitor or by using another capacitor;
Further, it is suitable for a circuit having a digital circuit such as a driving circuit of an image sensor and a circuit for controlling analog signal output. In particular, the present invention is suitable for a circuit in which a dynamic circuit and a static circuit are mixed.

Heretofore, in order to manufacture a TFT having a high mobility, the concentration of impurities contained therein has been reduced as much as possible. This is because, unlike the single crystal state, the energy barrier at the crystal grain boundary is lowered in polysilicon by impurities. According to the study of the present inventors, it has been found that the characteristics of the TFT vary depending on the concentration of oxygen or nitrogen contained in the polysilicon. That is, in general, when the concentration of oxygen or nitrogen increases, the NMOS also becomes PMOS.
It was also observed that the mobility decreased. For example, if the oxygen concentration in polysilicon is 9 × 10 ¹⁷ cm ⁻³ , the NMO
The electric field mobilities of S and PMOS are 42 cm ² /
Vs, 29 cm ² / Vs, but the oxygen concentration was 4 × 1
At 0 ¹⁸ cm ^-3 , the electric field mobilities of NMOS and PMOS are
Each, 36cm ² / Vs, and drops 22 cm ² / Vs.

However, what is more interesting is that
Due to the presence of oxygen or nitrogen, the leakage current is NMO
It has been discovered that S and PMOS behave quite differently. The situation is shown in FIG.
In FIG. 1 (B), as the oxygen concentration increases from 9 × 10 ¹⁷ cm ⁻³ (curve indicated by c in the figure) to 4 × 10 ¹⁸ cm ⁻³ (curve indicated by d in the figure), Leakage current is 1
Although it increased by one digit from 0 pA to 100 pA (drain voltage +1 V, gate voltage -10 V), PMOS increased
In FIG. 1A, from 10 × 10 ¹⁷ cm ⁻³ (curve indicated by “a” in the figure) to 4 × 10 ¹⁸ cm ⁻³ (curve indicated by “b”), from 10 pA This was reduced to 1 pA (drain voltage -1 V, gate voltage +10 V). Our studies have shown that very dramatic changes occur around oxygen or nitrogen concentrations of around 10 ¹⁸ cm ^-3 .

The mobility increases with increasing oxygen concentration.
The decrease in both S and NMOS is explained by the fact that the energy barrier at the crystal grain boundary of polysilicon of the active layer is increased as described above. On the other hand, the change in the leak current can be explained as follows: oxygen and nitrogen function as donors in the same manner as phosphorus, antimony, arsenic, bismuth, etc., so that the polysilicon active layer functions as a weak N-type.

The present invention utilizes this characteristic. In a TFT requiring high mobility, the impurity concentration in active polysilicon is reduced as much as possible. Use a PMOS and intentionally increase the concentration of oxygen or nitrogen to 10 ¹⁸ c
m ^-3 or more. Preferably, it is 10 ¹⁹ cm ⁻³ or more.
At that time, there is a concern that the mobility may decrease. However, according to the study of the present inventors, the mobility decrease is at most 50%, and the PM
Since the OS is 10 cm ² / Vs or more, sufficient characteristics can be obtained when used in various devices aimed at by the present invention.

In the present invention, the above configuration is achieved by introducing oxygen or nitrogen (or both) ions by masking the region of the high mobility TFT when introducing oxygen or nitrogen. It is characterized by the following.
Further, thereafter, the high mobility TFT is formed by thermal annealing.
Crystallization of the active layer of both the TFT and the low leakage current TFT. Here, thermal annealing is used because it is excellent in uniformity. Note that the thermal annealing step may be performed after the gate electrode is formed or after the source / drain is formed. Although the temperature of the thermal annealing is restricted by the substrate and other materials, when silicon or quartz is used as the substrate, it is possible to perform thermal annealing up to 1100 ° C. For example, in the case of Corning 7059 glass, a typical alkali-free glass, 6
Annealing at a temperature of 50 ° C. or less is desirable.

The present invention is characterized in that the state of the active layer is changed by introducing oxygen or nitrogen.
Here, it should be noted that a small amount of donors and acceptors such as phosphorus and boron (1
(0 ¹⁷ cm ⁻³ or less) The present invention has a great difference in that an amount 10 times or more than that of the threshold voltage control by introducing the same is introduced. For example, in a liquid crystal display or an image sensor, the typical size of a substrate is several times larger than that used in a conventional IC process. Technology cannot be used. Therefore, a very small amount of doping of 10 ¹⁷ cm ⁻³ or less could hardly be performed. Therefore, the conventional threshold voltage control was impossible.

On the other hand, in the present invention, the object is achieved by a dose amount which is at least one order of magnitude larger, but there is almost no decrease in mass productivity. In addition, since the control of the dose amount of this level is relatively easy, it is extremely economical in consideration of maintenance and maintenance costs of the apparatus.

One example of the present invention is that a display portion of an active matrix circuit such as a liquid crystal is a PMOS TFT.
Is used as a switching transistor, and the oxygen concentration in the active layer of the TFT in the active matrix region is 10 ¹⁸ c
m ⁻³ or more, preferably 10 ¹⁹ cm ⁻³ or more, while the concentration of oxygen or nitrogen in the active layer of the TFT used for the peripheral circuit is 10 ¹⁸ cm ⁻³ or less, preferably 10 ¹⁷ cm ⁻³ or less.
^-3 or less. Here, a PMOS TFT
Need to be inserted in series with the data line and the pixel electrode, and if the NMOS TFT is inserted in parallel, it is not suitable for the purpose of display such as because there is a large amount of leakage current. . However, in the TFT circuit of the pixel, P
The present invention includes a case where MOS and NMOS TFTs are inserted in series. Of course, it is within the technical scope of the present invention that two PMOS TFTs are inserted in parallel.

In a device having the above-described display circuit section (active matrix) and its driving circuit (peripheral circuit), the driving circuit is a CMOS circuit. In this case, not all of the circuits need to be CMOS, but it is desirable that the transmission gate and the inverter circuit be CMOS. Figure 2 shows a conceptual diagram of such a device.
(A). In the figure, a data driver 1 and a gate driver 2 are formed on an insulating substrate 7, and an active matrix 3 having a PMOS TFT is formed in the center, and the driver section and the active matrix are connected to a gate line 5 and a data line. The display devices connected by line 6 are shown. Active matrix 3 is PMOS
Is an aggregate of pixel cells 4 having

Regarding the CMOS circuit of the driver section,
In order to obtain high mobility, the concentration of impurities such as oxygen, nitrogen and carbon in the active layer is 10 ¹⁸ cm ⁻³ or less, preferably 10 ¹⁸ cm ⁻³ or less.
It is desired to be ¹⁷ cm ^-3 or less. As a result, for example, the threshold voltage of a TFT is 0.5 to 2 for an NMOS.
-0.5 to -3V for V and PMOS, and the mobility is
NMOS In 30~150cm ² / Vs, was a PMOS in 20~100cm ² / Vs.

On the other hand, in the active matrix portion, the auxiliary capacitance can be reduced by using a single element or a plurality of elements having a leakage current of about 1 pA at a drain voltage of 1 V, and the storage capacity can be reduced. We were able to.

The second example of the present invention relates to a semiconductor memory such as a DRAM. Semiconductor memory devices have already reached their speed limit with single crystal ICs. To operate at higher speeds than this, it is necessary to increase the current capacity of the transistor, but this not only causes a further increase in current consumption, but also, in particular, stores the charge by storing the charge in the capacitor. For a DRAM that operates, the only way to deal with this is by increasing the drive voltage, as the capacitance of the capacitor cannot be increased any further.

The single crystal IC is said to have reached the speed limit because, in part, a large loss is caused by the capacitance of the substrate and the wiring. If an insulator is used for the substrate, sufficiently high-speed driving can be performed without increasing current consumption. For this reason, an IC having an SOI (semiconductor on insulator) structure has been proposed.

In the case of a DRAM having a 1Tr / cell structure, the circuit configuration is almost the same as that of the above liquid crystal display device, and a DRAM having another structure (for example, 3Tr / cell) is used.
Cell structure), the PMOS of the present invention having a small leakage current is used as the TFT in the storage bit portion. On the other hand, since the driving circuit is required to operate at a sufficiently high speed, similarly to the above-described liquid crystal display device, an element having an extremely low impurity concentration in the active layer is used, and for the purpose of suppressing power consumption, it is similarly used. It is desirable to use CMOS.

The basic block configuration of such a semiconductor memory device is the same as that of FIG. 2A. For example, in a DRAM, 1 is a column decoder, 2 is a row decoder, 3 is a storage element unit, 4 is a unit storage bit, 5 is a bit line, 6 is a word line, and 7 is an (insulating) substrate.

The active matrix of the liquid crystal display device is also D
All RAMs also require a refresh operation, but during the refresh period, the TFTs must be sufficiently charged so that the charges stored in the pixel capacitance and the capacitor capacitance are not discharged. It must function as a large resistor. The present invention suppresses the leak current by intentionally doping oxygen or nitrogen into the active layer of the TFT used for such a purpose. However, this doping does not reduce the mobility. As described above. In addition, the degree of the decrease in the mobility varies depending on the dose, but those who intend to implement the present invention have:
It goes without saying that the optimum dose must be selected so that the leakage current and the mobility meet the purpose.

A third application example of the present invention is a driving circuit for an image sensor or the like. FIG. 2B shows an example of a 1-bit circuit of the image sensor.
Usually, the flop circuit 8 and the buffer circuit 9
An OS circuit is required to have a high-speed response that can follow a high-speed pulse applied to a scanning line. On the other hand, the TFT 10 in the signal output stage has a role of a dam that discharges the electric charge accumulated in the capacitor by the photodiode to the data line by the signal from the shift register units 8 and 9.

Such a TFT 10 is required not only to have a high-speed response but also to have a small leak current.
Therefore, in such a circuit, the T
It is desired that the impurity concentration of the FT active layer be 10 ¹⁸ cm ⁻³ or less, preferably 10 ¹⁷ cm ⁻³ or less. One T
In FT10, the concentration of nitrogen or oxygen is 10 ¹⁸
cm ^-3 or more is desired. Also in this case, it is needless to say that the optimum dose must be selected so that the leak current and the mobility meet the purpose.

[0034]

[Embodiment 1] FIG. 3 shows this embodiment. In the present embodiment, a polysilicon TFT formed by low-temperature annealing is used for a peripheral circuit and an active matrix region of a TFT type liquid crystal display device.

First, a base oxide film 102 having a thickness of 20 to
200 nm was deposited. Further, an amorphous silicon film having a thickness of 5 is formed thereon by a plasma CVD method or a low pressure CVD method using monosilane or disilane as a raw material.
0 to 150 nm was deposited. At this time, the concentrations of oxygen and nitrogen in the amorphous silicon film are set to 10 ¹⁸ cm ^-2 or less, preferably 10 ¹⁷ cm ^-2 or less. The low pressure CVD method is suitable for this purpose. In this embodiment, the oxygen concentration is set to 10 ¹⁷ cm ⁻² or less. On this amorphous silicon film, a protective silicon oxide film (thickness: 10 to 50 nm) 105 was formed again by the sputtering method. Thereafter, the peripheral circuit region 104 was covered with a photoresist 106 or the like, and only the active matrix region 103 was exposed.

Then, by the ion doping apparatus,
Irradiation with oxygen ions was performed as shown in FIG. The acceleration energy is 10 to 100 depending on the thickness of the protective layer 105.
keV. The dose amount depends on the thickness and acceleration energy of the protective layer 105 and the underlying amorphous silicon film 10.
An optimum value may be determined according to the thickness of the third layer. For example,
When the thickness of the amorphous silicon film is 100 nm, the protective layer is 25 nm, and the acceleration energy is 50 keV, by setting the dose to 5 × 10 ¹³ cm ⁻² , the oxygen concentration becomes 5 × over almost the entire area of the amorphous silicon film 103. 10 ¹⁸ cm ^-3 could be obtained.

Next, after removing the photoresist 106, the amorphous silicon film was crystallized by annealing at 600 ° C. for 24 hours. afterwards,
These Si films are patterned in an island shape, for example, as shown in FIG.
As in (B), an island region 107 of the peripheral circuit and an island region 108 of the active matrix region were formed. Further, a silicon oxide film (thickness: 50 to 150 nm) was formed by sputtering to cover these island-shaped regions, and this was used as a gate insulating film 109. Then, a thickness of 200 nm to 5
A μm aluminum film was formed by an electron beam evaporation method, and this was patterned to form a gate electrode in each island region.

Further, the substrate was immersed in an electrolytic solution, and a current was passed through the gate electrode to form an anodic oxide layer therearound. In this case, Japanese Patent Application Nos.
38637 and 4-54322, the anodic oxide film of the TFT in the peripheral circuit region is made thinner to improve the mobility, and the anodic oxide film of the TFT in the active matrix portion is made thicker to prevent gate leak. Although it is desirable to adopt a configuration, in this example, the thickness of the anodic oxide film was 200 to 250 nm in all cases. Through the above steps, gate electrode portions 110 to 112 of each TFT were manufactured.

Thereafter, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner by using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) as a mask by ion doping. At this time, first, phosphorus is injected into the entire surface using phosphine (PH ₃ ) as a doping gas, and then only the right side of the island-like region 107 in the figure is covered with a photoresist, and diborane (B ₂ H ₆ ) is doped. As a gas, boron was injected into the left side of the island region 107 and the active matrix region. The dose is 2 to 8 for phosphorus.
× 10 ¹⁵ cm ^-2 , boron is 4-10 × 10 ¹⁵ cm ^-2 ,
The dose of boron was set to exceed that of phosphorus.

Although the crystallinity of the silicon film is destroyed by the doping process, its sheet resistance can be reduced to about 1 kΩ / □. However, if this level of sheet resistance is too high, then at 600 ° C.
The sheet resistance can be further reduced by annealing for 24 hours.

Through the above steps, the N-type region 114,
And P-type regions 113 and 115 were formed. The sheet resistance in these regions was 200 to 800 Ω / □.
At the same time, active layers 116 to 118 were also formed. Of these, the active layers 116 and 117 had a nitrogen, oxygen, and carbon concentration of 10 ¹⁷ cm ⁻³ or less, while the active layer 118 was formed as shown in FIG. By the step (A), the oxygen concentration becomes 5
It has been increased to × 10 ¹⁸ cm ^-3 . After that, a silicon oxide film having a thickness of 300 to 1000 nm was formed over the entire surface as an interlayer insulator 119 by a sputtering method. This may be a silicon oxide film formed by a plasma CVD method. In particular,
In a plasma CVD method using TEOS as a raw material, a silicon oxide film with good step coverage can be obtained.

Thereafter, an ITO film was formed as a pixel electrode 120 by a sputtering method, and this was patterned. Then, the source / drain (impurity region) of the TFT
Contact holes are formed in the chrome wirings 121 to 12
4 was formed. FIG. 3D shows NTFT and PTF on the left side.
T indicates that an inverter circuit is formed. The wirings 121 to 124 may be multilayer wirings made of chromium or titanium nitride with aluminum as a base to reduce sheet resistance. Finally, annealing was performed at 350 ° C. for 2 hours in hydrogen to reduce dangling bonds in the silicon film. Through the above steps, the peripheral circuit and the active matrix circuit were formed integrally.

[Embodiment 2] In an image sensor driving circuit in which a photodiode and a TFT driving circuit are integrally formed on an insulating substrate, a shift register portion is formed by C
In the MOS TFT circuit, the TFT for controlling the accumulated charge by a signal from the shift register is constituted by a PMOS TFT. For these TFTs, polysilicon TFTs formed by low-temperature annealing were used. An example of the structure is shown in FIG. The process used was substantially the same as that in Example 1. Oxygen was implanted into the active layer of TF10 of FIG. 2 by ion doping, and its concentration was set to 2 × 10 ¹⁸ cm ⁻³ . In other TFTs, the concentrations of oxygen, nitrogen and carbon were set to 1 × 10 ¹⁷ cm ⁻³ or less. As a result, an image sensor having a high ability to collect charges accumulated by the photodiode could be manufactured.

[0044]

As is apparent from the above description, the present invention provides a conventional polysilicon TFT manufacturing process which has a minimum step of providing a step for selectively introducing oxygen or nitrogen into silicon. The change solved the problem.

The present invention has made it possible to increase the reliability and performance of particularly dynamic circuits and devices having such circuits. Conventionally, polysilicon TF has been used especially for purposes such as the active matrix of a liquid crystal display device.
T had a low ON / OFF ratio and had various difficulties in practical application, but it seems that such problems were almost completely solved by the present invention. Further, as shown in the second embodiment, the present invention can be used for a driving circuit of an image sensor on an insulating substrate. Although not shown in the examples, it will be apparent that the effects can be obtained by implementing the present invention in a TFT used as a means for forming a three-dimensional single crystal semiconductor integrated circuit.

For example, a peripheral logic circuit is constituted by a semiconductor circuit on a single crystal semiconductor, and a TF is formed thereon via an interlayer insulator.
T may be provided to form a memory element portion. In this case, the memory element is replaced with the P of the present invention.
It is a DRAM circuit using MOS TFTs, and its drive circuit is formed by converting a single crystal semiconductor circuit into CMOS. Moreover, when such a circuit is used for a microprocessor, the memory section is raised to the second floor, so that the area can be saved. Thus, the present invention is considered to be an industrially extremely useful invention.

[Brief description of the drawings]

FIG. 1A shows a gate voltage-drain current characteristic of an NMOS TFT. (B) shows a gate voltage-drain current characteristic of a PMOS TFT. (In each case, the horizontal axis is the gate voltage (V _G ) and the vertical axis is the drain voltage (V _D )

FIG. 2A is a block diagram showing a case where the present invention is applied to an active matrix device. (B) shows a circuit example when the present invention is applied to a driving circuit of an image sensor.

FIG. 3 shows the steps of the example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Insulating substrate 102 Base oxide film 103 Semiconductor region (matrix region) 104 Semiconductor region (peripheral circuit region) 105 Protective insulating film 106 Mask (fore-resist) 107 Island semiconductor region (for peripheral circuit) 108 Island semiconductor region (for matrix) ) 109 Gate insulating film 110 Gate electrode (for PTFT) 111 Gate electrode (for NTFT) 112 Gate electrode (Active matrix T)
113, 115 P-type impurity region 114 N-type impurity region 116 to 118 Active layer 119 Interlayer insulator 120 Pixel electrode (ITO) 121 to 124 Metal wiring

Claims (5)

(57) [Claims] 1. A semiconductor layer having an Amosphas having an oxygen concentration of 10 ¹⁸ cm ⁻³ or less or a crystallinity equivalent thereto is formed on an insulating surface, and oxygen is selectively added to the semiconductor film. Then, a region in which the concentration of oxygen is 10 ¹⁸ cm ⁻³ or more is formed, the semiconductor film is crystallized, and the crystallized semiconductor film is patterned to form a first region including the oxygen-added portion. and the island-shaped region of the form and a second island region comprising the portion where the oxygen is not added, to form a gate insulating film covering the first island region and said second island region Forming a gate electrode on the gate insulating film; and adding an impurity to the first island region and the second island region to form an impurity region. 2. An amosphath having a concentration of 10 ¹⁸ cm ⁻³ or less or a semiconductor film having low crystallinity equivalent thereto is formed on an insulating surface, and nitrogen is selectively added to the semiconductor film. Then, a region in which the concentration of nitrogen is 10 ¹⁸ cm ⁻³ or more is formed, the semiconductor film is crystallized, and the crystallized semiconductor film is patterned to form a first region including the nitrogen-added portion. and the island-shaped region of the form and a second island region comprising a portion where the nitrogen is not added, to form a gate insulating film covering the first island region and said second island region Forming a gate electrode on the gate insulating film; and adding an impurity to the first island region and the second island region to form an impurity region. 3. The method for manufacturing a semiconductor circuit according to claim 1, wherein the Amosphas or a semiconductor film having low crystallinity equivalent thereto is an amorphous silicon film. 4. The method according to claim 1, wherein
The method for manufacturing a semiconductor circuit, wherein the gate electrode includes aluminum. 5. The method according to claim 1, wherein:
The method for manufacturing a semiconductor circuit, wherein the gate insulating film includes silicon oxide.