JP3467255B2 - Memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a matrix structure like a liquid crystal display device or a dynamic RAM (DRAM), and has a MOS type or MIS as a switching element.
(Metal-insulator-semiconductor) type field effect element (above,
The present invention relates to a matrix device (including an electro-optical display device and a semiconductor memory device) which has a MOS type element) and performs a dynamic operation, and a drive circuit therefor. In particular, the present invention relates to a device using a thin film semiconductor element such as a thin film semiconductor transistor formed on an insulating substrate as a MOS type element.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal having a matrix structure, and are distinguished as amorphous silicon TFT or polycrystalline silicon TFT depending on the material and crystal state of the semiconductor used. Has been done. However, recently, research has also been carried out using a material exhibiting an intermediate state between polycrystalline silicon and amorphous. This material is
It is called semi-amorphous, and it is considered that small crystals float in an amorphous structure. This material is an excellent material that has the characteristics of high mobility in the single crystal state and low leakage current in the amorphous state, as will be described later.

Also in a single crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technology, and this is used as a load transistor in, for example, a highly integrated SRAM. However, in this case, the amorphous silicon TFT is hardly used.

Further, in a semiconductor circuit on an insulating substrate, since there is no capacitive coupling between the substrate and wiring, very high speed operation is possible, and a technique for use as an ultra high speed microprocessor or an ultra high speed memory has been proposed. .

Generally, a semiconductor in an amorphous state has a low electric field mobility, and therefore a TF requiring a high speed operation.
Not available for T. Further, in amorphous silicon, since the P-type electric field mobility is extremely small, a P-channel type TFT (PMOS TFT) cannot be manufactured. Therefore, an N-channel type TFT (NMOS TF) is not produced.
T) combined with complementary MOS circuit (CMOS)
Cannot be formed.

However, a TFT formed of an amorphous semiconductor has a characteristic that the OFF current is small. Therefore, unlike a transistor of a liquid crystal active matrix, such a high speed operation is not required, and only one conductivity type is sufficient and the charge holding ability is high.
It is used in applications that require FT.

On the other hand, a polycrystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and therefore can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, an electric field mobility as high as 300 cm ² / Vs is obtained. Considering that the electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is about 500 cm ² / Vs, it is an extremely large value, and M on the single crystal silicon is large.
While the operating speed of the OS circuit is limited by the parasitic capacitance between the substrate and the wiring, there is no such restriction because it is on the insulating substrate, and extremely high speed operation is expected.

In polycrystalline silicon, the T
Since not only FT but also PMOS TFT can be obtained in the same manner, it is possible to form a CMOS circuit. For example, in an active matrix type liquid crystal display device, not only the active matrix portion but also peripheral circuits (driver etc.) Also known is one having a so-called monolithic structure, which is composed of a CMOS polycrystalline TFT.

The TFT used in the above-mentioned SRAM also pays attention to this point, and the PMOS is constituted by the TFT,
This is used as a load transistor.

Further, in a normal amorphous TFT, it is difficult to form the source / drain regions by the self-alignment process as used in the single crystal IC technique, and the gate electrode and the source / drain regions are geometrically shaped. While the parasitic capacitance due to overlap is a problem,
Since the polycrystalline TFT can adopt the self-alignment process, it has a feature that the parasitic capacitance can be significantly suppressed.

[0011]

Some problems have been pointed out for the advantages of the polycrystalline TFT having such characteristics. A general polycrystalline TFT is a coplanar type in which an active layer is formed on an insulating substrate and a gate insulating film and a gate electrode are formed on the active layer. Although this structure has an advantage that a self-alignment process can be adopted, it is difficult to reduce the leak current (OFF current) of the active layer.

The cause of this leak current is not clear, but the major cause was the interface charge generated between the underlayer and the active layer. Therefore, it was solved by paying close attention to the fabrication of this interface and reducing the interface state density to the same level as between the gate oxide film and the active layer.

That is, in a high temperature process (maximum process temperature of about 1000 ° C.), quartz is used as a substrate, a silicon film is formed on the substrate, and this is used for 100
After thermal oxidation at about 0 ° C. to form a clean surface, an active silicon layer was formed by a film forming method such as a low pressure CVD method.

In addition, a low temperature process (maximum process temperature 6
Process below 50 ° C. Also called a medium temperature process. ), A method of forming a silicon oxide film having a low interface state density as a base film between the substrate and the active layer is adopted. A sputtering method is excellent as a method for forming a silicon oxide film. In addition, ECR-CVD method and TE
An oxide film with excellent characteristics can also be obtained by the plasma CVD method of OS.

However, the leak current could not be improved. In particular, NMOS was an order of magnitude larger than PMOS. The present inventor speculated that the cause was N-type weak active layer. Actually, the phenomenon that the threshold voltages of the PMOS and the NMOS manufactured in the high temperature process or the low temperature process shift in the negative direction was observed with good reproducibility. It is presumed that this is because, particularly in silicon, when the impurity is not added and the purity is high, when the crystallinity is not good like amorphous silicon, the N-type becomes weak. It was speculated that high-temperature-process polycrystalline silicon has many lattice defects and dangling bonds, which are different from perfect single-crystal silicon and serve as donors to supply electrons. Of course, there is also a possibility that a small amount of contaminant elements (sodium, etc.) may have an effect.

Anyway, if there is such a cause, NM
The threshold voltage of OS is significantly lower than that of PMOS,
It can be explained that the leak current is large. The situation is shown in FIG. In the NMOS, as shown in FIG. 1A, the source 12 (N ⁺ type) is grounded and the drain 13 (N
^If a voltage larger than the threshold voltage V _th is applied to the gate electrode 11 with a positive voltage applied to ( ⁺ type), the active layer 1
Although a channel is formed on the gate electrode side of 4 and a drain current (solid arrow in the figure) flows, the active layer 14 is a weak N type (N ⁻ type).
A current (dotted line arrow in the figure) that hardly depends on the gate voltage is flowing.

If the potential of the gate electrode is the threshold voltage V
_{Even in} the state of _th or less, the current on the dotted line is flowing. When the potential of the gate electrode becomes a large negative value,
Although the inversion layer (P-type) 16 is generated as shown in (B), it does not reach the inversion of the entire channel. On the contrary, when an excessive voltage is applied, electrons are accumulated on the opposite side of the gate and the channel is opened. Will be formed. N actually obtained
MOS data is consistent with this consideration.

On the other hand, in the PMOS, since the active layer is the N ⁻ type, the threshold voltage becomes large. However, the leak on the other side of the gate is greatly reduced. FIG. 2 shows a state in which a voltage below the threshold value or a voltage above the threshold value is applied to the PMOS.

The leak current which is remarkable in the NMOS has been an obstacle in various fields of application, especially fields requiring dynamic operation. For example, in an active matrix of liquid crystal or a DRAM, leak current causes loss of image information and stored information. Therefore, it has been necessary to reduce such leak current.

One method is to make the active layer of the NMOS intrinsic (I
Type) or weak P type. For example, when forming the active layer, only NMOS or NMOS and PMO
When an appropriate amount of P-type impurities (for example, boron) is implanted into both S to make the active layer of the NMOS an I-type or a weak P-type, the threshold voltage of the NMOS increases and the leakage current is greatly reduced. Should do. However, this method has some problems.

Normally, NMOS and PMO are formed on one substrate.
A CMOS circuit in which S is also mixed is used, but if impurity implantation is to be performed only on the N type, an extra photolithography process is required. Also, NMOS and PMO
If a P-type impurity is to be implanted into both active layers of S, a delicate impurity implantation technique is required. If the amount of implantation is too large, the threshold voltage of the PMOS will decrease and the leakage current will increase.

Ion implantation technology is also a problem. With the implantation technique that performs mass separation, it is possible to implant only the necessary impurity elements, but the processing area is small. Further, in the so-called ion doping method, although the processing area is large, unnecessary ions are also injected because there is no mass separation step, and the doping amount may not be accurate.

Further, the method of accelerating and implanting such ions causes formation of a localized level at the interface between the active layer and the underlayer. Further, unlike the conventional ion implantation for a single crystal semiconductor, since the implantation is performed on the insulating substrate, the charge-up phenomenon is remarkable and it is difficult to precisely control the implantation amount.

Therefore, it is possible to mix P-type impurities in advance at the time of forming the active layer, but it is difficult to control the amount of a trace amount of impurities, and when the NMOS and the PMOS are formed from the same film. Is not appropriate for PMO
Increases the leakage current of S, and also NMOS and PMOS
An additional masking process is required when forming from different coatings. In addition, controlling the threshold voltage by such a method depends on factors such as the gas flow rate.
Since the FT threshold value also varies, the variation in the threshold value for each lot becomes extremely large.

The present invention is intended to provide an answer to such a difficult problem, but the gist of the invention is not to reduce the leak current of the NMOS by the process but to design the circuit. Is designed to optimize a circuit that can be used even in a TFT having a large leak current. As described above, when the active layer is made of a highly pure silicon material, it becomes N ⁻ type, but its energy level is extremely reproducible and stable. Also, the process itself is extremely simple and the yield is sufficiently high. On the other hand, various methods of controlling the threshold voltage not only complicate the process, but also the energy levels (Fermi level, etc.) of the obtained active layer vary from lot to lot, and the yield decreases. To do.

Apparently, the process improvements allow NMO
The process of removing impurities as much as possible is easier than adjusting S to the circuit, that is, performing delicate doping of about 10 ¹⁷ cm ^-3 , and the circuit is designed according to the resulting NMOS. Better than that. This is the technical idea of the present invention.

[0027]

Solution to the Problem The semiconductor circuit to which the present invention is applied is not universal. The present invention particularly utilizes materials whose light transmissivity and reflectivity are changed by the effect of an electric field such as a liquid crystal display device, and sandwiches these materials between the electrodes facing each other to form an electric field between the electrodes and the counter electrode. Therefore, an active matrix circuit for displaying an image, a memory device for holding a memory by accumulating electric charges in a capacitor such as a DRAM, or an M-type MOS transistor.
It is suitable for a circuit having a dynamic circuit such as a dynamic shift register which drives a circuit of the next stage by using the OS structure portion as a capacitor or another capacitor. In particular, the invention is suitable for a circuit in which a dynamic circuit and a static circuit are mixed.

One example of the present invention is a PMOS TFT in a display portion of an active matrix circuit such as a liquid crystal.
Is used as a switching transistor.
Here, it is necessary that the PMOS TFT is inserted in series with the data line and the pixel electrode.
If the TFTs are inserted in parallel, a large leak current is not suitable for such a display purpose. Therefore, the present invention also includes the case where the PMOS and NMOS TFTs are inserted in series in the pixel TFT circuit. Of course, it is also within the technical scope of the present invention that two PMOS TFTs are inserted in parallel.

A second example of the present invention is that the drive circuit is a CMOS circuit in the device having the display circuit section (active matrix) and the drive circuit (peripheral circuit) thereof as described above. In this case, all circuits are CMOS
However, it is preferable that the transmission gate and the inverter circuit are formed in CMOS. A conceptual diagram of such a device is shown in FIG. In the figure, a data driver 31 and a gate driver 32 are formed on an insulating substrate 37, and an active matrix 33 having a PMOS TFT is formed in the central portion. These driver portion and the active matrix are formed by a gate line 35 and a data line. Line 3
Display devices connected by 6 are shown. The active matrix 33 is an aggregate of pixel cells 34 having PMOS.

Regarding the CMOS circuit, for example, the threshold voltage of the obtained TFT is 2V for NMOS and PMO.
6V for S, and PMO for leak current of NMOS
Even if it is more than 10 times larger than S, there is no problem in the CMOS inverter.

This is because power consumption due to leakage is not a serious problem in a logic circuit such as an inverter. The operation of the inverter is NM in the low voltage state.
The threshold voltage of OS is lower than the threshold voltage, and the high voltage state is required to be higher than the sum of the drain voltage and the threshold voltage of PMOS (<0). In this case, the drain voltage is 8V or higher, ideally. There is no problem as long as it is 10 V or higher. For example, it is sufficient if the input is a binary value of 0 V and 8 V.

The third example of the present invention relates to a semiconductor memory such as DRAM. Semiconductor memory devices have already reached the speed limit of single crystal ICs. In order to achieve higher-speed operation than this, it is necessary to increase the current capacity of the transistor, but this not only causes a further increase in current consumption, but especially by storing electric charge in the capacitor. As for the DRAM that operates, the capacity of the capacitor cannot be expanded any further, and the only way to cope with this is to increase the drive voltage.

It is said that the single crystal IC has reached the speed limit because, in part, a large loss occurs due to the capacitance of the substrate and wiring. If an insulator is used for the substrate, it can be driven at a sufficiently high speed without increasing the current consumption. For this reason, an IC having an SOI (semiconductor on insulator) structure has been proposed.

Also in the DRAM, in the case of the 1Tr / cell structure, the circuit configuration is almost the same as that of the above liquid crystal display device, and the DRAM of the other structure (for example, 3Tr / cell).
Even in the cell structure), a PMOS TFT having a small leak current is used as the TFT in the memory bit portion. The basic block configuration is the same as that of FIG. For example, in a DRAM, 31 is a column decoder, 32 is a row decoder, 33 is a memory element part, 34 is a unit memory bit, 35 is a bit line, 36 is a word line, and 37 is an (insulating) substrate.

The active matrix of the liquid crystal display device is also D
All of the RAMs also require a refresh operation, but the TFTs are sufficient to prevent the electric charge accumulated in the pixel capacitance and the capacitor capacitance from being discharged during the refresh period. It has to act as a great resistance. If an NMOS TFT is used in this case, sufficient drive cannot be performed because the leak current is large. This is the advantage of using a PMOS TFT having a low leak current.

In the present invention, the TFT of the high temperature process is effective, but the TFT of the low temperature process is particularly effective. The TFT obtained by the low-temperature process has a texture structure of its active layer intermediate between amorphous and single crystal, has a large lattice strain, and is in a so-called semi-amorphous state, and thus is physically close to an amorphous state. That is, an active layer made of pure silicon material by a low temperature process is mostly N ^- type.

Here, if the semi-amorphous state is described in detail, the silicon in the amorphous state starts crystal growth as heat is applied, but under atmospheric pressure, the crystal growth does not occur up to about 650 ° C.
That is, there is a relatively poorly crystalline portion between the portions with good crystallinity, and the intermolecular bond is tight,
It shows a different aspect from crystal precipitation in ordinary ionic crystals. That is, dangling bond
Is characterized by being extremely small. If the crystal growth is 6
When the temperature exceeds 80 ° C., the crystal growth rate is remarkably accelerated, and a polycrystalline state composed of many crystal grains is formed. Then, in this case, the molecular bonds at the crystal grain boundaries, which have been buffered by the lattice strain until then, are broken, and many dangling bonds are formed at the grain boundary portions.

Now, in such a semi-amorphous material, even if the active layer is doped with impurities,
As in the case of amorphous silicon, it does not contribute much to activation. The present inventors suspect that the reason for this is that the dopant impurities are selectively trapped in the places where there are many dangling bonds. Therefore, it is difficult to control the threshold voltage by doping in an active layer in a semi-amorphous state or an active layer formed by a low temperature process.

The present invention is also effective for a TFT having two active layers as described in Japanese Patent Application No. 4-73315, which is an invention of the present inventors. In this TFT, an active layer in an amorphous state is provided on the substrate side, and an active layer in a semi-amorphous state or a polycrystalline state is provided thereon, so that the leak generated by the electric charge existing at the interface between the substrate and the active layer is minimized. Can be reduced. However, since the structure uses amorphous silicon, the lower active layer is N ⁻ type. Therefore, even if the leak caused by the interface can be reduced, the leak caused by the active layer cannot be easily reduced. For example, even if the leak current is 10 ⁻¹² A or less (drain voltage 1 V) in the PMOS, the leak current is 100 times or more that in the NMOS.

The manufacturing method is illustrated in FIG. First,
A film 42 having a strong passivation force such as silicon nitride is formed on the substrate 41. If the substrate is sufficiently clean, it is not necessary to form such a film. Further underlying oxide film 4
3 is formed. Then, two layers of the amorphous silicon film are formed. By optimizing the deposition rate and the deposition substrate temperature, it is determined whether the amorphous state is maintained in the later heat treatment, semi-amorphous or polycrystallized. It In this example, the upper layers 45 and 47 are semi-amorphized (or polycrystallized), and the lower layers 44 and 47 are
47 remains amorphous.

A characteristic of such a method is that two kinds of silicon films having different properties can be formed by subtly changing the conditions while forming a film using the same chamber. Threshold voltage control negates the advantages of this method. if,
Even if one tries to change the lower layers 44, 46 from N ^- type to I-type, since the layers remain amorphous, the ionization rate is poor and a large amount of doping is required. Therefore, the chamber is significantly contaminated by these impurities, and on the contrary, there is a possibility that the active layer of the PMOS becomes P type. Therefore, a TFT having such an active layer having a two-layer structure is extremely suitable for the present invention which does not require threshold voltage control by doping. A method for forming such a TFT will be described in detail in the embodiments.

[0042]

EXAMPLES Example 1 FIG. 4 shows a CMO using the present invention.
An example of manufacturing the S circuit will be described. In this embodiment, the substrate 41
A No. 7059 glass substrate manufactured by Corning Inc. was used as. Various other types of substrates can be used, but it is necessary to take measures depending on the substrate so that mobile ions such as sodium do not enter into the semiconductor film. The ideal substrate is a synthetic quartz substrate with a low alkali concentration, but if it is difficult to use costly,
Commercially available low-alkali glass or non-alkali crow will be used. In this embodiment, a thickness of 5 to 2 is provided on the substrate 41 for the purpose of preventing mobile ions from entering the substrate 41.
The silicon nitride film 42 of 00 nm, for example, 10 nm is decompressed by CV.
It was formed by the D method. Further, a silicon oxide film 43 having a thickness of 20 to 1000 nm, for example 50 nm, was formed on the silicon nitride film by the sputtering method. The thickness of these coatings is designed according to the degree of penetration of mobile ions or the degree of influence on the active layer.

For example, the quality of the silicon nitride film 42 is not good,
If the charge trap is large, it affects the upper semiconductor layer through the silicon oxide film. In that case, the silicon oxide film 43 must be thickened.

To form these films, not only the above-mentioned low pressure CVD method and sputtering method but also plasma CVD method or the like may be used. In particular, TEOS may be used for forming the silicon oxide film. The selection of these means may be determined in consideration of the scale of investment and mass productivity. Needless to say, these coatings may be continuously formed.

After that, monosilane is used as a raw material in a thickness of 20 to 200 nm, for example, 100 by a low pressure CVD method.
nm amorphous silicon film was formed. The substrate temperature was 430 to 480 ° C, for example 450 ° C. Further, the substrate temperature was continuously changed, and an amorphous silicon film having a thickness of 5 to 200 nm, for example, 10 nm was formed at 520 to 560 ° C., for example, 550 ° C. As a result of research by the present inventors, it was revealed that the substrate temperature has an important influence on the subsequent crystallization. For example, it was difficult to crystallize a film formed at 480 ° C. or lower. Conversely, 520 ° C
The film formed at the above temperature was easy to crystallize. The amorphous silicon film thus obtained has a thickness of 600
It was annealed at 24 ° C. for 24 hours. As a result, only the upper silicon film was crystallized, and crystalline silicon called so-called semi-amorphous silicon was obtained. On the other hand, the lower silicon film remained in an amorphous state.

In order to promote the crystallization of the upper silicon film, the concentrations of carbon, nitrogen and oxygen contained in the film are all preferably 7 × 10 ¹⁹ cm ^-3 or less. In this example, it was confirmed by SIMS analysis that it was 1 × 10 ¹⁷ cm ⁻³ or less. On the contrary, in order to suppress the crystallization of the lower silicon film, it is convenient that these elements are contained in a large amount. However, since excessive doping adversely affects semiconductor characteristics and eventually TFT characteristics, the presence or absence of doping and the amount thereof are designed according to the characteristics of the TFT.

Now, the amorphous silicon film is thermally annealed.
A crystalline silicon film according to
Island-shaped semiconductor for NTFT by etching into various patterns
A region 45 and an island-shaped semiconductor region 47 for PTFT are formed.
It On top of each island-shaped semiconductor region, an intentional impurity
The impurity concentration such as boron is 10¹⁷cm ^-3
SIMS (Secondary Ion Mass Spectrometry)
Therefore confirmed. Therefore, the conductivity type of this portion is N
^-Suspected to be a type. On the other hand, the bottom of each semiconductor region
Silicon layers 44 and 46 are substantially amorphous silicon
Met.

Thereafter, a gate insulating film (silicon oxide) 48 having a thickness of 50 to 300 nm, for example 100 nm, is formed by a sputtering method targeting silicon oxide in an oxygen atmosphere.
Just formed. This thickness is determined by the operating conditions of the TFT and the like.

Next, an aluminum film having a thickness of 500 nm was formed by the sputtering method, and this was patterned with a mixed acid (phosphoric acid solution containing 5% nitric acid) to form gate electrodes / wirings 49 and 50. The etching rate is 225 when the etching temperature is 40 ° C.
nm / min. In this way, the outer shape of the TFT was adjusted. At this time, the size of the channel is 8
The width was 20 μm. The state at this time is shown in FIG.
Shown in.

Further, aluminum oxide was formed on the surface of the aluminum wiring by the anodic oxidation method. As a method of anodizing, Japanese Patent Application No. 3-23, which is an invention of the present inventors, is used.
The method described in 1188 or Japanese Patent Application No. 3-238713 was used. The detailed mode of implementation may be changed according to the characteristics of the target element, process conditions, investment scale, and the like. In this example, aluminum oxide coatings 51 and 52 having a thickness of 250 nm were formed by anodic oxidation.

After that, the N-type source / drain regions 53 and the P-type source / drain regions 5 are formed by the well-known CMOS fabrication technique by the ion implantation method through the gate oxide film.
4 was formed. In both cases, the impurity concentration is 8 × 10 ¹⁹ cm ^-3
So that As the ion source, boron fluoride ions were used for the P type and phosphorus ions for the N type, and the former was implanted at an accelerating voltage of 80 keV and the latter was implanted at an accelerating voltage of 110 keV. The acceleration voltage depends on the thickness of the gate oxide film, the semiconductor region 45,
It is set in consideration of the thickness of 47. An ion doping method may be used instead of the ion implantation method. In the ion implantation method, since the implanted ions are separated by mass, unnecessary ions are not implanted, but the size of the substrate that can be processed by the ion implantation apparatus is limited. On the other hand, the ion doping method has the ability to process a relatively large substrate (for example, a diagonal size of 30 inches or more), but since hydrogen ions and other unnecessary ions are simultaneously accelerated and implanted, the substrate is easily heated. . In this case, it is difficult to selectively implant impurities using a photoresist as a mask, which is used in the ion implantation method.

In this way, a TFT having an offset region was manufactured. This is shown in FIG. 4 (B). Finally, the source / drain regions were recrystallized by the laser annealing method using the gate electrode portion as a mask. The conditions of laser annealing are, for example, Japanese Patent Application No. 3-23.
The method described in 1188 or 3-238713 was used. Then, as the interlayer insulator 55, silicon oxide is used as R
It was formed by the F plasma CVD method, holes for electrode formation were opened in this, and aluminum wirings 56 to 48 were formed to complete the element.

In this example, the coatings 45 and 47, which were originally crystalline silicon, were formed by laser annealing.
Not only the film 44 which was amorphous silicon,
Up to 46 is crystallized. This is because laser annealing is powerful. As a result, as shown in FIG. 4C, the initial amorphous regions 44 and 46 are all converted into a material having the same crystallinity as the source / drain except the portions 59 and 60 under the channels. As a result, the thickness of the source / drain was substantially the same as that of the island-shaped semiconductor regions 45 and 47. However, the substantial channel thickness was thinner than the source / drain regions by about 10 nm as apparent from the figure. As a result, the sheet resistance of the source / drain was small, and the excellent characteristics that the OFF current was small due to the thin channel could be exhibited.

FIG. 4 shows a manufacturing process of a CMOS circuit used for a driving circuit of a liquid crystal display device, but a PMOS is similarly formed in an active matrix portion on the same substrate. The characteristics of the TFT thus formed are that the channel length is 5 μm, the channel width is 20 μm, the source / drain voltage is 1 V, the leakage current of NMOS is ˜100 pA, and that of PMOS is ˜1 pA of PMOS. . Thus, the off resistance of the PMOS was 100 times larger. When the gate voltage is + 8V (-8V in the case of PMOS) in the ON state, the NMOS has 10 μA,
The PMOS applied a current of 100 nA. The drain current of the PMOS is significantly smaller than that of the NMOS because the threshold voltage of the PMOS is negatively shifted. Therefore, the gate voltage of the PMOS is -12V
Then, the drain current was 1 μA. That is, if a transmission gate is formed using such a TFT, the potential applied to the PTFT should be shifted to the negative side.

TF of PMOS of active matrix section
The size of T has a channel length of 5 μm and a channel width of 10 μm.
And PMO used as an active matrix
Change the gate voltage of S TFT from 0V to -12V.
The drain current is 10 ⁶Because it doubles
There was no problem for displaying images. Furthermore,
Two PMOS TFTs if required to operate
If it is configured in series to form a so-called dual gate structure
Good. In this case, the resistance of the TFT is
In addition, although it increases by about an order of magnitude, the resistance of the TFT is increased in the ON state.
Since the resistance is only about twice, the drain current is eventually
Is 10⁷Will also fluctuate. Forming three stages of TFTs in series
Once done, the volatility will increase by one digit.

[Embodiment 2] FIG. 5 shows a manufacturing process of NMOS and PMOS devices for carrying out the present invention. In this example, a TFT was manufactured by a high temperature process. First, the quartz substrate 61 (width 105 mm x length 105 m
m × thickness 1.1 mm), a polysilicon film not doped with impurities is formed to a thickness of 100 by a low pressure CVD method.
.About.500 nm, preferably 150 to 200 nm. Then, this was oxidized in a dry high temperature oxygen atmosphere. The temperature is in the range of 850 to 1100 ° C. and is 95
0-1050 degreeC was especially preferable. In this way
A silicon oxide film 62 was formed on the substrate (FIG. 5A).

Further, plasma C using disilane as a raw material
An amorphous silicon film having a thickness of 100 to 1000 nm, preferably 35, is formed by the VD method or the low pressure CVD method.
The thickness was 0 to 700 nm. Substrate temperature is 350-450 ° C
And Then, this was annealed at 550 to 650 ° C., and more preferably at 580 to 620 ° C. for a long time to give it crystallinity. Then, by patterning this, FIG.
As shown in, the NMOS region 63a and the PMOS region 6
3b was formed.

Then, the surface of the silicon region 63 is oxidized in a dry and high temperature oxidizing atmosphere, and the thickness of the surface of the silicon region is 50 to 150 n as shown in FIG. 5C.
A silicon oxide film 64 having a thickness of m, preferably 50 to 70 nm was formed. The oxidizing conditions were the same as those for silicon oxide 62.

After that, phosphorus is added at 10 ¹⁹ to 2 × 10 ²⁰ c.
m ⁻³ , for example, 8 × 10 ¹⁹ cm ⁻³ doped silicon film having a thickness of 200 to 500 nm, preferably 350 to 400
Then, the gate gate 65a of the NMOS and the gate 65b of the PMOS are formed by patterning as shown in FIG. 5D. Furthermore, by the ion implantation method,
Impurity regions 66 and 67 for NMOS and PMOS are formed, respectively.

At this time, the bottom surfaces of these impurities were prevented from reaching the underlying silicon oxide film 62. That is, many localized levels are formed at the interface between the underlying oxide film and the silicon film, and as a result, the silicon film near the underlying oxide film exhibits a specific conductivity type (normally N type). If the impurity region is adjacent to the silicon film in such a portion, leakage occurs. Therefore, in order to avoid such a leak, a space of 50 to 200 nm is provided between the bottom surface of the impurity region and the base oxide film 62 in this embodiment.

In this embodiment, ion implantation is performed through the silicon oxide film 64. However, in order to control the depth of the impurity region more precisely, the silicon oxide film 64 may be removed and thermal diffusion may be performed. Good.

After forming the impurity region, the crystallinity of the impurity region was recovered by thermal annealing. After that, as in a normal TFT manufacturing process, an interlayer insulator (phosphorus glass) 68 was deposited and flattened by reflow, contact holes were formed, and metal wirings 69 to 71 were formed.

A 1Tr / cell DRAM (16 kbits) was manufactured using the TFT formed by the above steps. The channel size of the TFT is 2
When the source / drain voltage is 1 V, the leak current of the NMOS is about 10 pA when the channel width is 10 μm and the leak current of the PMOS is about 0.
It was 1 pA. The memory element section has a channel length of 2 μm,
A PMOS with a channel width of 2 μm was used. The capacity of the capacitor of the memory element section was set to 0.5 pF, and the refresh cycle could be held for a long time of up to 5 seconds. This is because the PMOS off-state resistance is 5 × 10 ¹³ Ω.
It was possible because it was a high value. Further, the peripheral circuit was made into a CMOS by using the NMOS and the PMOS manufactured in the above steps. DRA on such an insulating substrate
Since it is M, high-speed operation is possible and 1 per bit
Writing / reading was possible in 00 nsec.

[0064]

The invention has made it possible to increase the reliability and the performance of particularly dynamic circuits and devices having such circuits. Conventionally, a polycrystalline TFT has a low ON / OFF ratio and has various difficulties in practical use, especially for purposes such as an active matrix of a liquid crystal display device. However, the present invention solves such a problem. It seems that it was done. Further, as shown in the second embodiment, the semiconductor circuit on the insulating substrate is excellent in that it operates at high speed. Although not shown in the examples, it will be apparent that the effect can be achieved by implementing the present invention in a TFT used as a means for three-dimensionalizing a single crystal semiconductor integrated circuit.

For example, the peripheral logic circuit is composed of a semiconductor circuit on a single crystal semiconductor, and TF is formed on the peripheral logic circuit via an interlayer insulator.
It is also possible to provide T to form a memory element part. In this case, the memory element portion is a DRAM circuit using a PMOS TFT, and its drive circuit is formed by forming a CMOS into a single crystal semiconductor circuit. Moreover, when such a circuit is used in a microprocessor, the memory section is raised to the second floor, so that the area can be saved. Thus, the present invention is considered to be an extremely useful invention in industry.

[Brief description of drawings]

FIG. 1 shows a conceptual diagram of the operation of an NMOS TFT.

FIG. 2 shows a conceptual diagram of the operation of a PMOS TFT.

FIG. 3 shows a conceptual diagram of the configuration of the present invention.

FIG. 4 shows a manufacturing process of a TFT of the present invention.

FIG. 5 shows a manufacturing process of a TFT of the present invention.

[Explanation of symbols]

11, 21 ... Gate electrodes 12, 22 ... Source regions 13, 23 ... Drain regions 14, 24 ... Active layers 15, 25 ... Channels 16, 26 ... Inversion layer 31 ... Data Driver (column decoder in case of DRAM) 32 ... Gate driver (row decoder in case of DRAM) 33 ... Active matrix section (memory element section in case of DRAM) 34 ... Unit pixel (in case of DRAM) Is a unit memory bit) 35 ... Gate line (bit line in case of DRAM) 36 ... Data line (word line in case of DRAM) 37 ... Insulating substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-61-116873 (JP, A) JP-A-60-109282 (JP, A) JP-A-60-74564 (JP, A) JP-A-51- 95742 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/336 H01L 27/108 H01L 29/786

Claims (16)

(57) [Claims] 1. A silicon nitride film formed on a glass substrate.
A silicon oxide film formed on the silicon nitride film,
A P-type thin film transistor formed on a silicon oxide film;
A memory device having a driving circuit which is formed on the silicon oxide film and includes a complementary thin film transistor for driving the P type thin film transistor, wherein the P type thin film transistor and the complementary thin film transistor have a source region and a drain region. And a semiconductor film including a channel formation region, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film, wherein the source region and the drain region are crystalline semiconductors. And the channel formation region includes an upper layer made of a crystalline semiconductor and an
A memory device, comprising a lower two-layer semiconductor made of a morphous semiconductor , wherein the upper layer of the channel forming region is thinner than the source region and the drain region. 2. Low-alkali glass or non-alkali glass
A silicon nitride film formed on a glass substrate made of
Silicon oxide film formed on a silicon oxide film and the silicon oxide film
A P-type thin film transistor formed on the above, and the above-mentioned silicon oxide.
Formed on the base film, including complementary thin film transistor
And a drive circuit for driving a P-type thin film transistor.
In the memory device according to claim 1, the P-type thin film transistor and the complementary thin film transistor are provided.
The transistor includes a source region, a drain region and a channel forming region.
A semiconductor film, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film, and the source region and the drain region are crystalline semiconductors.
And the channel formation region has an upper layer made of a crystalline semiconductor and an
The upper layer of the channel forming region is made of a two-layer semiconductor of a lower layer made of a morphous semiconductor, and the upper layer of the channel forming region has a thickness of the source.
Thinner than the region and the drain region
Memory device. 3. The method of claim 1 or 2, memory device, wherein the semiconductor film is a silicon film. 4. The method according to any one of claims 1 to 3.
And a memory device characterized by being an active matrix device. 5. The odor according to any one of claims 1 to 3.
A memory device characterized by being a DRAM. 6. A silicon nitride film formed on a glass substrate.
A silicon oxide film formed on the silicon nitride film,
A thin film transistor formed on the silicon oxide film, the acid
A memory device having a capacitor connected to the thin film transistor formed on a silicon oxide film, wherein the thin film transistor is formed on the semiconductor film having a source region, a drain region and a channel forming region, and formed on the channel forming region. A gate insulating film and a gate electrode formed on the gate insulating film, the source region and the drain region are made of a crystalline semiconductor, and the channel formation region is made of an upper layer made of a crystalline semiconductor.
A memory device, comprising a lower two-layer semiconductor made of a morphous semiconductor , wherein the upper layer of the channel forming region is thinner than the source region and the drain region. 7. Low-alkali glass or non-alkali glass
A silicon nitride film formed on a glass substrate made of
Silicon oxide film formed on a silicon oxide film and the silicon oxide film
A thin film transistor formed on the silicon oxide film
And a capacitor connected to the thin film transistor.
The thin film transistor has a source region, a drain region and a channel forming region.
A semiconductor film, a gate insulating film formed on the channel forming region, and a gate electrode formed on the gate insulating film, and the source region and the drain region are crystalline semiconductors.
And the channel formation region has an upper layer made of a crystalline semiconductor and an
The upper layer of the channel forming region has a lower crystallinity than the lower layer.
Higher than the source region and the drain region
A memory device characterized by being thin. 8. The system of claim 6 or 7, memory device, wherein the semiconductor film is a silicon film. 9. The memory device according to claim 6 , wherein the thin film transistor is a P-channel thin film transistor. 10. A silicon nitride film formed on a glass substrate.
A silicon oxide film formed on the silicon nitride film,
A first thin film transistor formed on the silicon oxide film;
A memory device comprising: a capacitor connected to a source region or a drain region of the first thin film transistor; and a drive circuit formed on the silicon oxide film for driving the first thin film transistor and having a second thin film transistor. The first and second thin film transistors have a semiconductor film including a source region, a drain region and a channel formation region, a gate insulating film in contact with the semiconductor film, and a gate electrode formed on the gate insulating film. The source region and the drain region are made of a crystalline semiconductor, and the channel formation region is made of an upper layer made of a crystalline semiconductor.
A memory device, comprising a lower two-layer semiconductor made of a morphous semiconductor , wherein the upper layer of the channel forming region is thinner than the source region and the drain region. 11. Low-alkali glass or non-alkali glass
A silicon nitride film formed on a glass substrate,
A silicon oxide film formed on the silicon nitride film;
A first thin film transistor formed on the film;
Contact the source or drain region of the thin film transistor of
And a capacitor formed on the silicon oxide film.
1 thin film transistor is driven, and 2nd thin film transistor
And a driving circuit having a drive circuit, the first and second thin film transistors include a source region, a drain region, and a channel forming region.
A semiconductor film, a gate insulating film in contact with the semiconductor film, and a gate electrode formed on the gate insulating film, wherein the source region and the drain region are crystalline semiconductors.
And the channel formation region has an upper layer made of a crystalline semiconductor and an
The upper layer of the channel forming region is made of a two-layer semiconductor of a lower layer made of a morphous semiconductor, and the upper layer of the channel forming region has a thickness of the source.
Thinner than the region and the drain region
Memory device. 12. A silicon nitride film formed on a glass substrate.
A silicon oxide film formed on the silicon nitride film,
A first thin film transistor formed on the silicon oxide film;
Source region or drain of the first thin film transistor
In a memory device having a capacitor connected to a region and a drive circuit having a second thin film transistor formed on the silicon oxide film and driving the first thin film transistor, the first and second thin film transistors are: A semiconductor film including a source region, a drain region, and a channel formation region; a gate insulating film in contact with the semiconductor film; and a gate electrode formed on the gate insulating film, wherein the source region and the drain region are crystalline. And a channel forming region in which the channel forming region and an upper layer made of a crystalline semiconductor are formed.
The upper layer of the channel forming region is thinner than the source region and the drain region, and the first thin film transistor and the second thin film transistor are the same. A memory device formed by a method. 13. Low-alkali glass or non-alkali glass
A silicon nitride film formed on a glass substrate,
A silicon oxide film formed on the silicon nitride film;
A first thin film transistor formed on the film;
Contact the source or drain region of the thin film transistor of
And a capacitor formed on the silicon oxide film.
Second thin film transistor for driving one thin film transistor
And a driving circuit having a drive circuit, the first and second thin film transistors include a source region, a drain region, and a channel forming region.
A semiconductor film, a gate insulating film in contact with the semiconductor film, and a gate electrode formed on the gate insulating film, wherein the source region and the drain region are crystalline semiconductors.
And the channel formation region has an upper layer made of a crystalline semiconductor and an
The upper layer of the channel forming region is made of a two-layer semiconductor of a lower layer made of a morphous semiconductor, and the upper layer of the channel forming region has a thickness of the source.
Thinner than a region and the drain region, the first thin film transistor and the second thin film transistor
The transistors are formed by the same method.
Memory device. 14. Oite <br/> to any one of claims 10 to 13, wherein the semiconductor film memory device which is a silicon film. 15. A silicon nitride film formed on a glass substrate.
A silicon oxide film formed on the silicon nitride film,
A plurality of bit lines formed on the silicon oxide film, the oxide
A plurality of word lines formed on a silicon film , unit storage bits formed in a matrix at the intersections of the bit lines and the word lines, and the oxidation formed on the unit storage bits. in memory device having a thin film transistor on the silicon film, and a capacitor formed in the unit memory bits, and the thin film transistors of the unit memory bit is driven circuit connected through the bit lines and the word lines The driving circuit has a plurality of thin film transistors formed on the silicon oxide film, and the thin film transistor of the unit memory bit and the thin film transistor of the driving circuit include a source region, a drain region, and a channel forming region, respectively. A semiconductor film, a gate insulating film formed on the semiconductor film, and formed on the gate insulating film Has been a gate electrode, the source region and the drain region is a crystalline semiconductor, the channel formation region upper and A consisting of crystalline semiconductor
A memory device, comprising a lower two-layer semiconductor made of a morphous semiconductor , wherein the upper layer of the channel forming region is thinner than the source region and the drain region. 16. A glass base made of low-alkali glass or non-alkali glass.
A silicon nitride film formed on the plate, and a silicon nitride film formed on the silicon nitride film.
And a silicon oxide film formed on the silicon oxide film.
A plurality of bit lines and a plurality of bit lines formed on the silicon oxide film
Cross the word line and the bit line and the word line
Units formed in a matrix form
Storage bit and the oxidation formed on the unit storage bit.
In a memory device having a thin film transistor on a silicon film and a capacitor formed in the unit storage bit, the thin film transistor of the unit storage bit has the bit
Drive circuit is connected via the power line and the word line.
The drive circuit includes a plurality of drive circuits formed on the silicon oxide film.
A thin film transistor, a thin film transistor of the unit memory bit and the driving circuit.
The thin film transistor of the channel includes a source region, a drain region and a channel forming region , respectively.
A semiconductor film, a gate insulating film formed on the semiconductor film, and a gate electrode formed on the gate insulating film, and the source region and the drain region are crystalline semiconductors.
And the channel formation region has an upper layer made of a crystalline semiconductor and an
The upper layer of the channel forming region is made of a two-layer semiconductor of a lower layer made of a morphous semiconductor, and the upper layer of the channel forming region has a thickness of the source.
Thinner than the region and the drain region
Memory device.