JP3977032B2 - Thin film transistor and semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate semiconductor device, such as a thin film transistor (TFT), having a thin-film active layer (also called an activation region or a channel region) formed on an insulating substrate. Fields to which the present invention is applied include semiconductor integrated circuits, liquid crystal display devices, optical reading devices, and the like.
[0002]
[Prior art]
Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer on an insulating substrate. In particular, thin-film insulated gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel of a display device such as a liquid crystal having a matrix structure. Depending on the material and crystal state of the semiconductor to be used, an amorphous silicon TFT or a polycrystalline silicon TFT is used. It is distinguished. However, recently, research has also been made to use a material that exhibits an intermediate state between polycrystalline silicon and amorphous. This is said to be semi-amorphous and is considered to be a state in which small crystals are floated in an amorphous structure.
[0003]
Also in a single crystal silicon integrated circuit, a polycrystalline silicon TFT is used as a so-called SOI technology, and this is used as a load transistor in a high integration SRAM, for example. However, in this case, the amorphous silicon TFT is hardly used.
[0004]
In general, the electric field mobility of an amorphous semiconductor is small, and therefore it cannot be used for a TFT that requires high-speed operation. In addition, since the P-type field mobility is extremely small in amorphous silicon, a P-channel TFT (PMOS TFT) cannot be manufactured. Therefore, in combination with an N-channel TFT (NMOS TFT), A complementary MOS circuit (CMOS) cannot be formed.
[0005]
However, a TFT formed of an amorphous semiconductor has a feature that the OFF current is small. Therefore, unlike a liquid crystal active matrix transistor, such a high-speed operation is not required, and only one of the conductivity types is sufficient, and it is used for an application that requires a TFT having a high charge retention capability. .
[0006]
On the other hand, a polycrystalline semiconductor has a larger electric field mobility than an amorphous semiconductor, and thus can operate at high speed. For example, in a TFT using a silicon film recrystallized by laser annealing, the electric field mobility is 300 cm. ² A value of / Vs is obtained. The electric field mobility of a MOS transistor formed on a normal single crystal silicon substrate is 500 cm. ² / Vs is an extremely large value, and the MOS circuit on the single crystal silicon is limited to the operation speed due to the parasitic capacitance between the substrate and the wiring. There are no such restrictions, and remarkable high-speed operation is expected.
[0007]
In addition, in the case of polycrystalline silicon, not only NTFT but also PTFT can be obtained in the same manner, so that a CMOS circuit can be formed. For example, in an active matrix liquid crystal display device, not only the active matrix portion but also peripheral circuits can be formed. A device having a so-called monolithic structure in which (a driver or the like) is formed of a CMOS polycrystalline TFT is also known. The TFT used in the above-described SRAM is also paying attention to this point, and the PMOS is constituted by a TFT, which is used as a load transistor.
[0008]
[Problems to be solved by the invention]
However, in general, a polycrystalline TFT has a larger leakage current than an amorphous TFT due to a larger electric field mobility, and is inferior in an ability to hold a charge of an active matrix pixel. For example, when used for a liquid crystal display element, there has been no particular problem because the pixel size is several hundred μm square and the pixel capacity is large. However, the pixel capacity is reduced, which is insufficient for stable static display.
[0009]
Several solutions have been proposed for the leakage current problem of such polycrystalline TFTs. One of them is a method of thinning the active layer. This has been reported to reduce the OFF current. For example, when the thickness of the active layer is 25 nm, the OFF current is 10 ^-13 It is known that A or less can be achieved. However, it is known that it is very difficult to crystallize a thin semiconductor film and it is not easily crystallized.
[0010]
Moreover, reducing the thickness of the active layer leads to reducing the thickness of the source / drain regions. That is, in a normal manufacturing method, the source / drain and the active layer are formed from the semiconductor film manufactured at the same time and have the same thickness. This leads to an increase in the resistance of the source / drain region.
[0011]
For this purpose, a method is employed in which the source / drain regions are formed separately so that most of the source / drain regions are thick, but this is an additional mask process, which is not preferable from the viewpoint of yield.
[0012]
Further, according to the knowledge of the present inventors, the MOS threshold voltage is greatly shifted in the TFT having an active layer of 50 nm or less, and particularly in the case of the NMOS, the threshold is 0 V or negative. Value. When a CMOS is manufactured using such TFTs, the operation becomes unstable.
[0013]
On the other hand, when the active layer is thickened, the leakage current increases. However, the magnitude is not proportional to the thickness of the active layer, and therefore, it is considered that the leakage current increases nonlinearly due to some factor. As a result of the study by the present inventors, it has been clarified that most of the leakage current of the TFT having a thick active layer flows in a bypass manner via a portion of the active layer on the substrate side. There are two possible causes for such a leakage current. One is due to the electric charge fixed at the interface state between the substrate and the active layer, and the other is that mobile ions such as sodium enter the active layer from the substrate side, This is to make it conductive. The latter is overcome by increasing the cleanliness of the process.
[0014]
The former cannot be solved even if the interface between the substrate and the active layer is cleaned. For example, stacking the active layer directly on the substrate raises the interface state, so that an oxide film as good as the gate oxide film (for example, a thermal oxide film of silicon) is used as a base, However, even if an active layer was formed, the leakage current could not be solved. That is, it was found that the fixed charge cannot be easily removed.
[0015]
[Means for Solving the Problems]
In order to solve such a difficulty, the present inventor forms another gate electrode (referred to as a backside gate electrode) between the substrate and the active layer, and maintains the potential of the gate electrode at an appropriate value. It was discovered that the effect of the fixed charge as described above can be counteracted. A typical example of the configuration of the present invention is shown in FIGS.
[0016]
FIG. 1 illustrates the concept of the present invention, where A is a normal gate electrode and B is a back gate electrode. Such a backside gate electrode may overlap the entire surface of the source and drain as shown in FIG. 1A, but in this case, the parasitic capacitance between the source and drain and the backside gate electrode increases. When high-speed operation or the like is required, a configuration in which the source and / or the drain does not overlap with each other as illustrated in FIG. What is important is that such a back gate electrode overlaps at least a part of the active layer and crosses the active layer as much as possible to ensure the effect.
[0017]
For example, in the conventional NMOS, when the source and gate potentials are set to 0 and the drain potential is set to 10 V, the drain current is ideally 0, but the active layer is weakly inverted by the fixed charges on the substrate side. Since it is in a state, a drain current flows due to thermal excitation. This is shown in FIG. That is, in the conventional TFT, a weak inversion region as shown in the figure is formed by a fixed charge on the substrate side. This is a source of leakage current because it exists almost unchanged regardless of the voltage applied to the gate electrode. However, when the thickness of the active layer is extremely thin, the gate electrode affects the substrate side and the weak inversion region disappears due to the gate potential. So far, it has been reported that the leakage current can be reduced by making the active layer thin without particularly knowing the reason. However, this model has shown that the threshold voltage easily shifts and it is also clear that this is not an essential solution.
[0018]
The present invention intends to eliminate the effect of fixed charges by providing the back gate electrode as described above and setting the back gate electrode to 0 or a negative value. FIG. 2 shows an example of the present invention. In this case, the back gate electrode is provided with a contact hole in a part of the insulating film, connected to the source region, and always at the same potential as the source. In FIG. 2A, the back gate electrode 9 is configured to overlap with the source region 6 and the drain region 5 in exactly the same manner. In this case, the process is relatively simple, and a yield is good because there is no step in a portion where the gate electrode is present.
[0019]
If an element having such a structure is to be formed, it may be performed as follows. That is, a film to be a back gate electrode and an insulating film 8 are formed on a substrate, a contact hole 10 is formed in this, a semiconductor layer is further formed, and this is patterned together. Then, the gate insulating film 4 and the gate electrode 1 are formed to form the drain region 5 and the source region 6 in a self-aligning manner, and the portion not doped with impurities becomes the active layer 7. Finally, the drain electrode 2 and the source electrode 3 may be formed. The number of masks used in the above steps is four (if the source electrode and drain electrode are not formed simultaneously, five masks).
[0020]
On the other hand, in FIG. 2B, the back gate electrode 19 and the drain region 15 are not overlapped, and the step of the back gate electrode affects the gate electrode 11. Therefore, the gate electrode may be peeled off. Further, the number of steps increases as compared with FIG. That is, the back surface gate electrode 19 is first patterned, then the insulating film 18 is formed, and a contact hole is provided. Then, a semiconductor layer is formed and patterned, and then the gate electrode 11 is patterned, and the source region 14, the drain 15, and the activation region 17 are formed in a self-aligned manner, and the source electrode 13 and the drain electrode 12 are formed. To do. There are five to six masks used in the above process. In order to reduce the parasitic capacitance and simplify the process, it is ideal that the back gate electrode is also formed in a self-aligned manner with the source region and the drain region.
[0021]
The material of the back gate electrodes 9 and 19 must be determined in consideration of the subsequent processes. For example, when a gate insulating film is formed by a thermal oxidation method, the gate insulating film must be formed of a material that can withstand such a high temperature, and diffusion of isotopic harmful elements from the back gate material to the active layer must be avoided. For example, if the active layer is made of silicon and the gate insulating film is a thermal oxide film of silicon, the maximum process temperature normally exceeds 1000 ° C., so doped polysilicon is desirable as the material for the back gate electrode.
[0022]
In a low temperature process where the maximum process temperature is about 600 ° C., doped silicon may be used, but if a lower resistance material is used, chromium, tantalum or tungsten is preferable. Of course, the use of materials other than these should also be handled as a design matter of the practitioner.
[0023]
The operation of the TFT having such a structure is summarized in FIG. Here, an example of NMOS is shown, but in the case of PMOS, the direction of the inequality sign may be reversed. First, the gate potential V _G Is the source potential V _S Or drain potential V _D Consider the case of whichever is lower. In this case, since the source and the drain are not symmetrical as shown in FIG. _D The situation depends on the height of the. If V _S <V _D Then, as shown in FIG. 3A, the gate electrode, the back gate electrode, and the source are at the same potential, and electrons are swept out from these regions to form a depletion region or an accumulation region. Conversely, if V _D <V _S Then, as shown in FIG. 3B, the gate electrode side is a depletion region, but an inversion region is formed on the back gate electrode side, and a drain current flows. The above discussion is very rough and, strictly speaking, the threshold voltage must be considered, but the outline of the present invention can be understood.
[0024]
V _D > V _S In the condition of V _G <V _S Then, the depletion region extends to the entire active layer (FIG. 3C), but V _G > V _S Then, an inversion region is formed on the gate electrode side (FIG. 3D). Also, V _D <V _S In the condition of V _G <V _D Then, an inversion region is formed on the back gate side, and a drain current flows (FIG. 3E). _G > V _D Then, inversion regions are formed on both sides (FIG. 3F).
[0025]
V _D Is V _S The situation is complicated if they are equal to or similar to. That is, in this case, since there is no electric field line flowing from the source to the drain (or from the drain to the source), a weak inversion region is formed due to the influence of the fixed charge on the back gate side, as seen in the conventional TFT. Leak current is generated (FIGS. 3G and 3H).
[0026]
The back gate electrode is practically conveniently maintained at the same potential as the source or drain, but if this is not possible, it may be maintained at the same potential as other power supply potentials. Even when the potential is kept the same as that of the source or drain, if the potential does not fluctuate, the influence on the operation characteristics of the element is small.
[0027]
For example, when reducing the leakage in the off state and allowing the TFT to be turned on / off, FIG. 3 (A) or (C) (OFF state) and FIG. 3 (D), (F) or (H ) (ON state) may be determined so that the potential is determined. In addition, a CMOS inverter circuit can be configured using this element.
[0028]
Since fixed charge is mainly a problem with NMOS, PMOS may be manufactured in the same way as before, and only NMOS may be manufactured using the present invention. However, when charge is negative, PMOS also has a problem. Both may be used.
[0029]
【Example】
[Embodiment 1] In this embodiment, a method for manufacturing a crystallized silicon TFT by a high temperature process using the present invention will be described. In this embodiment, both the gate electrode and the back gate electrode are made of doped polysilicon. Since the manufacturing technique is the same as various known semiconductor integrated circuit process techniques, details are not described.
[0030]
Phosphorus 10 on the quartz substrate 21 ¹⁹ ~ 5x10 ²⁰ cm ^-3 For example 8 × 10 ¹⁹ cm ^-3 A doped polycrystalline silicon film was formed to a thickness of 100 to 500 nm, for example, 200 nm by a low pressure CVD method, and thermally oxidized in an oxygen atmosphere at 1000 ° C. to form a silicon film 22 and a silicon oxide film 23. The thickness of silicon oxide was 50 to 200 nm, for example 70 nm. A silicon film that is not doped with impurities may be formed and then doped with impurities and then thermally oxidized, or may be thermally oxidized and then doped with impurities.
[0031]
Thereafter, an amorphous silicon film 24 not doped with impurities was deposited to a thickness of 100 to 1000 nm, for example, 300 nm. The substrate temperature during deposition was 450 to 550 ° C., for example, 480 ° C. Moreover, although monosilane and polysilane (disilane, trisilane) could be used as source gas, disilane was more stable than polysilane more than trisilane, and could form a better film than monosilane. Then, crystals were grown slowly at 600 ° C. over 12 hours. The state up to this point is shown in FIG.
[0032]
Next, patterning is performed to form an island-shaped semiconductor region (silicon island), and thermal oxidation is performed in an oxygen atmosphere to form a silicon oxide film 25 serving as a gate insulating film on the surface with a thickness of 50 to 500 nm. For example, 150 nm was formed. The state up to this point is shown in FIG.
[0033]
Further, a polycrystalline silicon film doped with phosphorus was formed by a low pressure CVD method to a thickness of 300 to 1000 nm, for example, 500 nm, and this was patterned to form a gate electrode 26. Further, ion implantation was performed in a self-aligned manner using this gate electrode as a mask, and annealing was performed at 1000 ° C. to form a source region 28 and a drain region 27. Then, an interlayer insulator 29 was formed by a plasma CVD method using TEOS, and a contact hole was provided in this to form a drain electrode 30. The state up to this point is shown in FIG.
[0034]
Thereafter, a source electrode was formed. Since this process is special, it will be described in detail. First, after forming the drain electrode, an interlayer insulator 31 was further formed. Then, a photoresist 32 was formed by a spin coating method, and a hole 33 was provided to form a contact hole for the source electrode.
[0035]
Next, the interlayer insulating layer and the gate insulating film (both silicon oxide) were etched by an isotropic etching method such as an isotropic dry etching method or a wet etching method. At this time, it is desired that only the silicon oxide film is selectively etched. For example, thin hydrofluoric acid may be used as an etchant. When the etching time is long, the etching reaches the side surface of the contact hole, and a contact hole 34 wider than the hole 33 is formed. The state up to this point is shown in FIG.
[0036]
This time, etching was performed by an anisotropic etching method such as RIE (reactive ion etching method), and the source region 28 was etched almost faithfully to the hole 33 to form a contact hole 35. The state up to this point is shown in FIG. Thereafter, the thin silicon oxide film existing between the source region and the back gate electrode was also removed.
[0037]
After removing the photoresist, a source electrode 36 was formed on the source with a metal wiring material. That is, the contact in the contact hole is sufficiently formed in both the source region and the back gate electrode by the previous two-stage etching. This state is shown in FIG. This completes the TFT.
[0038]
The NMOS and PMOS TFTs thus formed were combined as shown in FIG. 6A to constitute a CMOS inverter circuit. A circuit diagram of this circuit is shown in FIG. In this inverter circuit, the back gate electrode is always at the source potential (V in the case of PMOS). _H V for NMOS _L ). That is, in a static state, V _in Is V _H (Thus V _out Is V _L ), The NMOS is in the state of FIG. 3 (H) and the PMOS is in the state of FIG. 3 (A). Conversely, V _in Is V _L (Thus V _out Is V _H ), The NMOS is in the state of FIG. 3A and the PMOS is in the state of FIG. 3H, and the leakage current on the substrate side is extremely suppressed.
[0039]
The reason why the leakage current can be reduced simply by maintaining the back gate electrode at the same potential as the source is explained as follows.
That is, in the NMOS, as shown in FIG. 6C, a state is considered in which the drain 61 has a higher potential than the source 63. If there is no back gate electrode or the back gate electrode 64 is in a floating state, the lines of electric force from the drain to the source cross the active layer region 62 straightly as shown in FIG. 6C. To do.
[0040]
However, if the back surface gate electrode is kept at the same potential as the source, a part of the lines of electric force that normally go straight to the source are drawn to the back surface gate electrode, and the lines of electric force are as shown in FIG. To be bent.
[0041]
Actually, the situation is complicated because there is a fixed charge at the interface between the active layer region and the insulating film. That is, if there is no back gate electrode or is in a floating state, the electric lines of force are affected by the fixed charge (in this case, positive), and as shown in FIG. Electric lines of force having components from the electrode) side toward the active layer are generated. The meaning of such lines of electric force is that the potential of the insulating film (or backside gate electrode) is higher than that inside the active layer. A weak inversion region is formed in the vicinity of the film interface. Since the weak inversion region is continuously generated from the drain to the source, it causes a leak current.
[0042]
On the other hand, when the back gate electrode is kept at the same potential as the source, even if there is a fixed charge between the active layer and the insulating film (or back gate electrode), Since they have components toward the back electrode, they cancel each other out, and as shown in FIG. 6 (F), there are almost no lines of electric force having components from the back electrode toward the active layer surface. Moreover, even if an electric field line having such a component is generated in part, it does not occur entirely from the source to the drain.
[0043]
Thus, leakage current could be remarkably reduced by keeping the back gate electrode at the source potential. For example, when a CMOS circuit is configured, the sustain current in the static state is on average about the sum of the leakage currents of NMOS and PMOS, but in a conventional TFT, when the drain voltage is 5 V, A current of about 1 pA flowed. For example, although there are about 2 million CMOS inverter circuits in a 1-Mbit static RAM, a current of about 2 μA constantly flows to retain the memory.
[0044]
However, the sustain current of one CMOS inverter has been reduced to 0.01 to 0.1 pA or less because the leakage current of NMOS in particular has been significantly reduced by the present invention. Therefore, the holding current of the 1 Mbit SRAM can be reduced to 0.02 to 0.2 μA. When the present invention is used in a nonvolatile memory in which a backup battery is packaged in an SRAM, the battery life can be increased 10 to 100 times that of the conventional battery.
[0045]
In the present invention, the capacitance C between the gate electrode and the channel incorporated as a design matter in the conventional CMOS inverter circuit. ₁ In addition, the drain and source parasitic capacitance C via the back gate electrode ₂ , C _Three Note that there exists. This parasitic capacitance acts as a load, reduces the signal transmission speed during operation of the inverter, and increases power consumption. In a simple calculation, the signal delay time is C ₂ And C _Three The power consumption is proportional to the fourth power of the sum.
[0046]
Therefore, it is desirable to reduce these parasitic capacitances as much as possible. In practice, the fixed charge is almost positive, so it has no effect on the MOS. Therefore, it is effective to apply the present invention by using the same structure as that of the conventional PMOS and providing the back gate electrode only in NMOPs. If considered simply, the parasitic capacitance can be halved, and the power loss due to the parasitic capacitance can be reduced to 1/16.
[0047]
[Embodiment 2] In this embodiment, a method of manufacturing a crystallized silicon TFT by a high temperature process using the present invention will be described. In this embodiment, both the gate electrode and the back gate electrode are made of doped polysilicon. Since the manufacturing technique is the same as various known semiconductor integrated circuit process techniques, details are not described.
[0048]
A polycrystalline silicon film doped with phosphorus was formed on the quartz substrate 71 under the same conditions as in Example 1, and this was patterned to form a back gate electrode 72. Then, thermal oxidation was performed in an oxygen atmosphere at 1000 ° C. to form a silicon oxide film 73. Thereafter, an amorphous silicon film 74 not doped with impurities was deposited under the same conditions as in Example 1, and crystals were grown by thermal annealing. The state up to this point is shown in FIG.
[0049]
Next, patterning was performed to form an island-shaped semiconductor region (silicon island), and a thermal oxide film 75 was formed in the same manner as in Example 1. Further, a gate electrode 77 for NMOS and a gate electrode 76 for PMOS are formed by doped silicon, and N-type impurity ions are implanted in a self-aligned manner to form an impurity region 78. At this time, an N-type impurity (for example, phosphorus or arsenic) is also implanted into the back gate electrode, but there was no problem because the back gate electrode itself was N-type. The state up to this point is shown in FIG.
[0050]
Next, the TFT portion on the right side of the figure was covered with a photoresist or the like, and P-type impurity ions (boron or the like) were implanted. Through the above steps, a PMOS source 79 and drain 80, an NMOS source 82 and drain 81 were formed. Thereafter, an interlayer insulator 83 was formed. The state up to this point is shown in FIG.
[0051]
Thereafter, a photoresist 84 was formed on the entire surface, and holes 85 to 87 were formed in portions where contact holes were to be provided. Then, contact holes 88 to 90 were provided in the interlayer insulating layer and the gate oxide film (both silicon oxide) by isotropic etching in the same manner as in Example 1. In either case, the contact hole expanded more than the hole formed in the resist. Further, the silicon layer was etched in 85 to 87 holes by anisotropic etching, and the thin silicon oxide film below the contact hole 90 was also etched. The state up to this point is shown in FIG.
[0052]
Finally, electrodes 91 to 93 were formed from a metal material. This state is shown in FIG. An inverter was formed with the electrode 91 at a high potential, the electrode 93 at a low potential, and the electrode 92 as an output terminal. In the inverter according to such a process, there is a concern that there are more PMOS leaks than in the first embodiment, but in general, the present invention reduces the NMOS leak current by one to two digits. On the other hand, the PMOS leakage current can be improved only by about an order of magnitude, and as a result, even if the present invention is applied only to the NMOS, the difference between the leakage current of the NMOS and the PMOS is reduced. No particular deterioration of the circuit characteristics was observed.
[0053]
Further, in the CMOS inverter, in the high voltage input state (NMOS is ON, PMOS is OFF), the leakage current is determined by the PMOS leakage current, and in the low voltage input state (NMOS is OFF and PMOS is ON), The leakage current was determined by the NMOS leakage current. In the conventional TFT, the leakage current of NMOS is 100 times or more that of PMOS. When this is used as an SRAM circuit, one of the inverters is in a low voltage input state (NMOS) in one memory cell. In the end, the leakage current of the SRAM circuit is dominated by the leakage current of the NMOS.
[0054]
Therefore, it is substantially sufficient to provide the back gate electrode only in the NMOS and reduce the leakage current of the NMOS by 1 to 2 digits as in the present embodiment. This is because even if backside gate electrodes are provided on both NMOS and PMOS, most of the leakage current is due to NMOS. Rather, considering the demerits due to the parasitic capacitance between the back gate electrode and the drain, it is advisable not to provide the back gate electrode in the PMOS.
[0055]
【The invention's effect】
According to the present invention, a TFT having excellent characteristics with little leakage current can be produced. Further, as already shown, the characteristics of the CMOS inverter could be improved by combining this TFT. TFTs can be applied not only to liquid crystal displays and image sensors, but also to high-speed logic circuits and high-speed memories. The present invention can be applied to these devices, and is effective in improving various characteristics such as reliability and power consumption of these devices. In the examples, a high-temperature process is mainly taken up and a method of application to this is shown. When a low temperature process is employed, an anodic oxidation process as shown in Japanese Patent Application Nos. 4-38637 and 4-54322 which are the inventions of the present inventors may be used.
[0056]
Although TFTs are also used in conventional single crystal integrated circuits, by using the present invention, they are used as a substitute for ordinary MOS transistors rather than the conventional auxiliary purpose, and the circuit characteristics are further improved. It will be clear that it can be increased. Thus, the present invention is an invention with great industrial value.
[0057]
In addition, as described in the paragraph of means for solving the above problems, another gate electrode (backside gate electrode) is formed between the substrate and the active layer as shown in FIGS. By keeping the potential of the gate electrode at an appropriate value, the effect of the fixed charge as described above can be canceled. Such a backside gate electrode may overlap the entire surface of the source and drain as shown in FIG. 1A, but in this case, the parasitic capacitance between the source and drain and the backside gate electrode increases. When high-speed operation is required, it may be as shown in FIG. In the present invention, when such a back gate electrode has a structure that overlaps at least a part of the active layer, the above-described effect can be obtained by making the back gate electrode cross the active layer as much as possible. Can be made more reliable.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of a structure of a TFT of the present invention.
FIG. 2 shows a configuration example of a conventional TFT.
FIG. 3 shows the operation of the TFT of the present invention.
FIG. 4 shows the operation of a conventional TFT.
FIG. 5 shows a manufacturing process of a TFT of the present invention.
FIG. 6 shows an application example of a TFT of the present invention.
FIG. 7 shows a manufacturing process of a TFT of the present invention.
[Explanation of symbols]
1, 11 ・ ・ ・ Gate electrode
2, 12 ... Drain electrode
3, 13 ... Source electrode
4, 14 ... Gate insulating film
5, 15 ... Drain region
6, 16 ... source region
7, 17 ... Active region
8, 18 ... Insulating film
9, 19 ・ ・ ・ Back side gate electrode
10, 20 ... Contact part

Claims (17)

A first gate electrode facing one surface of the active layer via a first insulating film and a second gate electrode facing the other surface of the active layer via a second insulating film are formed on the insulating surface. have to,
The first gate electrode is provided between the insulating surface and the active layer so as to be in contact with and overlap with the source through a contact hole formed in the first insulating film so as not to overlap the drain. A thin film transistor characterized in that the thin film transistor is provided. A first gate electrode facing one surface of the active layer via a first insulating film and a second gate electrode facing the other surface of the active layer via a second insulating film are formed on the insulating surface. have to,
The first gate electrode is in contact with the source between the insulating surface and the active layer through a contact hole formed in the first insulating film, and at least a part of the active layer and the source A thin film transistor provided so as to overlap with a drain and not to overlap with a drain. A first gate electrode facing one surface of the active layer via a first insulating film and a second gate electrode facing the other surface of the active layer via a second insulating film are formed on the insulating surface. have to,
The first gate electrode is provided between the insulating surface and the active layer so as to cross the active layer, and is in contact with the source through a contact hole formed in the first insulating film. A thin film transistor provided so as to overlap with each other and not to overlap with a drain.   4. The thin film transistor according to claim 1, wherein the thin film transistor is an NMOS, and the first gate electrode is held at a potential of 0 V or less. 5.   The thin film transistor according to claim 1, wherein the active layer is made of a polycrystalline semiconductor film. A semiconductor integrated circuit formed using thin film transistors on an insulating surface,
The thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second gate electrode opposed to the other surface of the active layer via a second insulating film Have
The first gate electrode is provided between the insulating surface and the active layer so as to be in contact with and overlap with the source through a contact hole formed in the first insulating film so as not to overlap the drain. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is provided. A semiconductor integrated circuit formed using thin film transistors on an insulating surface,
The thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second gate electrode opposed to the other surface of the active layer via a second insulating film Have
The first gate electrode is in contact with the source between the insulating surface and the active layer through a contact hole formed in the first insulating film, and at least a part of the active layer and the source The semiconductor integrated circuit is provided so as to overlap with the drain and not to overlap with the drain. A semiconductor integrated circuit formed using thin film transistors on an insulating surface,
The thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second gate electrode opposed to the other surface of the active layer via a second insulating film Have
The first gate electrode is provided between the insulating surface and the active layer so as to cross the active layer, and is in contact with the source through a contact hole formed in the first insulating film. A semiconductor integrated circuit characterized by being provided so as to overlap with each other and not to overlap with a drain.   9. The semiconductor integrated circuit according to claim 6, wherein the thin film transistor is an NMOS, and the first gate electrode is held at a potential of 0 V or less. A semiconductor integrated circuit formed using a P-channel thin film transistor and an N-channel thin film transistor on an insulating surface,
The P-channel type thin film transistor has a gate electrode opposed to one surface of an active layer through an insulating film,
The N-channel type thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second electrode opposed to the other surface of the active layer via a second insulating film. Has a gate electrode,
The first gate electrode is provided between the insulating surface and the active layer so as to be in contact with and overlap with the source through a contact hole formed in the first insulating film so as not to overlap the drain. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is provided. A semiconductor integrated circuit formed using a P-channel thin film transistor and an N-channel thin film transistor on an insulating surface,
The P-channel type thin film transistor has a gate electrode opposed to one surface of an active layer through an insulating film,
The N-channel type thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second electrode opposed to the other surface of the active layer via a second insulating film. Has a gate electrode,
The first gate electrode is in contact with the source between the insulating surface and the active layer through a contact hole formed in the first insulating film, and at least a part of the active layer and the source The semiconductor integrated circuit is provided so as to overlap with the drain and not to overlap with the drain. A semiconductor integrated circuit formed using a P-channel thin film transistor and an N-channel thin film transistor on an insulating surface,
The P-channel type thin film transistor has a gate electrode opposed to one surface of an active layer through an insulating film,
The N-channel type thin film transistor includes a first gate electrode opposed to one surface of the active layer via a first insulating film, and a second electrode opposed to the other surface of the active layer via a second insulating film. Has a gate electrode,
The first gate electrode is provided between the insulating surface and the active layer so as to cross the active layer, and is in contact with the source through a contact hole formed in the first insulating film. A semiconductor integrated circuit characterized by being provided so as to overlap with each other and not to overlap with a drain.   13. The semiconductor integrated circuit according to claim 10, wherein the first gate electrode is held at a potential of 0 V or less.   14. The semiconductor integrated circuit according to claim 10, wherein the P-channel thin film transistor and the N-channel thin film transistor form a complementary MOS circuit.   The semiconductor integrated circuit according to claim 10, wherein the P-channel thin film transistor and the N-channel thin film transistor form a CMOS inverter circuit.   The semiconductor integrated circuit according to claim 6, wherein the active layer is made of a polycrystalline semiconductor film.   The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is an optical reading device.

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