JP2001119033A - Thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate difference in brightness within a panel surface by reducing leak current, when a thin-film transistor is off and to improve minute machining accuracy and mating accuracy of photolithographic technique, according to the tendency toward making TFT fine. SOLUTION: In this semiconductor of a thin-film transistor formed on an insulation substrate, the film thickness of source and drain pats is made larger than the film thickness of a semiconductor part directly below or above a gate electrode via a gate insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor structure for manufacturing a high performance thin film transistor on a glass substrate.

[0002]

2. Description of the Related Art Hydrogenated amorphous silicon has been put to practical use as a switching transistor for a pixel of a liquid crystal panel, an optical sensor for an image sensor of a facsimile, and a solar cell of a battery for a calculator. The greatest advantage of hydrogenated amorphous silicon is that it can be stably manufactured over a large area with good reproducibility at a process temperature of at most about 300 ° C. However, as the density of pixels of a display or an image sensor increases, a silicon semiconductor thin film capable of following higher-speed driving has been required. The mobility of conventional hydrogenated amorphous silicon is at most 1.0 cm ²
/ V · sec, which is not a performance that can sufficiently satisfy the requirement. Therefore, as a process for improving the mobility by crystallizing those thin films, 1) a manufacturing method in which hydrogen or SiF ₄ is mixed with silane gas and used for plasma CVD to crystallize a thin film to be deposited, 2) amorphous A production method for attempting crystallization using silicon as a precursor has been developed.

[0003] As a method of crystallization described in 2), 60
Examples include a solid phase growth method in which heat treatment is performed at a temperature of about 0 ° C. for a long time and an excimer laser annealing method. In particular, the latter excimer laser annealing method has high mobility (> 100 cm ² / V · se) without actively increasing the temperature of the substrate.
c) A polycrystalline silicon thin film has been successfully obtained. For more information, see IEEE Electron Device
Letters, 7 (1986) p276-278, I
EEE Transactions onElectr
on Devices, 42 (1995) p251-2
57.

When an amorphous silicon TFT or a polycrystalline silicon TFT developed as described above is used as a switching transistor in a pixel portion of a liquid crystal panel, it is necessary to write a signal to the liquid crystal within a given time. A sufficient on-current is required, and at the same time, a reduction in off-state current is required. When a driving circuit or the like is built in a glass substrate around a liquid crystal panel using a polycrystalline silicon TFT, the performance and reliability of each TFT as a circuit element must be sufficiently ensured.

[0005] From the above viewpoints, particularly in a polycrystalline silicon TFT, a structure in which an appropriate gap, for example, about 0.5 μm is provided between a semiconductor channel portion (directly below a gate electrode) and a source and a drain (offset structure). And a structure in which an impurity-doped region having a lower concentration than the source / drain region is provided between the channel portion of the semiconductor (immediately below the gate electrode) and the source and the drain (LDD structure) to achieve both performance and reliability. At the same time, the so-called leakage current at the time of off is also reduced. Since the amorphous silicon TFT is used for the pixel portion TFT, a leakage current at the time of off is a problem, but at present, the leakage current can be sufficiently reduced only by forming a doped layer in the source / drain portion.

However, as the definition of a liquid crystal panel increases and the speed of a built-in drive circuit increases, the size of a TFT needs to be reduced. Miniaturization of the TFT used for the built-in driver enables high-speed driving to reduce the parasitic capacitance of the TFT element itself. In the miniaturization of the pixel TFT, not only the aperture ratio of the pixel is improved but also the reduction of the parasitic capacitance accompanying the miniaturization is advantageous for improving the image quality and driving.

[0007]

In the future, a liquid crystal panel that will be demanded in the world will be a low-cost liquid crystal panel with excellent image quality (for example, a photographic quality panel). In that case, it is natural that higher definition of the panel and higher speed of the built-in drive circuit are required, and technically, miniaturization of the TFT is an important essential technology. The miniaturization of TFTs used for built-in drivers
High-speed driving is possible because the parasitic capacitance of the FT element itself can be reduced. In the miniaturization of the pixel TFT, not only the aperture ratio of the pixel is improved but also the reduction of the parasitic capacitance accompanying the miniaturization is advantageous for improving the image quality and driving.

At this time, there are two problems to be solved for the miniaturization of the TFT from the viewpoint of the pixel TFT and the viewpoint of the reliability of the TFT for the driving circuit. The problem in the case of a pixel TFT is that if the area of one pixel is reduced and the storage capacitor portion, which has conventionally been storing signal charges, can be designed to be small, the aperture ratio will not be reduced and a bright and excellent panel will be obtained. but its realization for the need to eliminate the luminance difference of the leakage current (about 10 @ ¹² a) more order of magnitude or more reduced to panel plane when a conventional off. From the viewpoint of the reliability of the TFT for a drive circuit, in order to obtain the offset structure or the LDD structure described in the above-described related art in accordance with the miniaturization of the TFT, the precision of the fine processing and the matching accuracy of the photolithography technology are large. The above problems are required, and a self-aligned offset structure or LDD structure that exhibits stable characteristics is required.

[0009]

In order to solve the above-described problems, in a semiconductor of a thin film transistor formed on an insulating substrate, the thickness of a semiconductor portion immediately below or directly above a gate electrode via a gate insulating film is reduced. In comparison, a thin film transistor characterized in that the thickness of the source and drain portions is large, and the thickness of the semiconductor thin film immediately below the electrode is preferably 30 nm.
In the following, the thickness of the source / drain portion exceeds 30 nm, and more preferably, the thin film transistor has a thickness of 50 nm or more.

In the thin film transistor, the source and drain portions have a distribution of impurities in a depth direction from a surface on an electrode forming side, and a high concentration region and a low concentration region of the impurity are formed. A first semiconductor layer doped with an n-type or p-type dopant on an undoped layer in the source and drain portions of the thin-film transistor, and further doped with an n-type or p-type dopant; In the thin film transistor characterized by laminating a semiconductor layer having a larger doping amount than the semiconductor layer, furthermore, in the source and drain portions of the transistor, the same material as the semiconductor thin film in the channel portion and a different material from the semiconductor thin film in the channel portion are used. A thin film transistor having a stacked structure of materials is preferable.

The semiconductor thin film in the channel portion of the thin film transistor is a crystalline Si thin film, and the source and drain portions have a laminated structure of a crystalline Si thin film and a SiC thin film. A thin film transistor, wherein a semiconductor thin film in a channel portion of the thin film transistor is an amorphous Si thin film, and a source and a drain portion of the thin film transistor have a laminated structure of an amorphous Si thin film and a SiC thin film; A thin film transistor, wherein the semiconductor thin film in the channel portion of the transistor is an amorphous Si thin film, and the source and drain portions have a gradient composition layer structure of an amorphous Si thin film and a SiC thin film; At the source and drain of the thin film transistor, the same as the semiconductor thin film at the channel A thin film transistor, wherein the source and drain portions of the thin film transistor are formed of a crystalline Si thin film and an amorphous Si thin film. The problem can be solved by a thin film transistor characterized by being stacked with a thin film.

Normally, the offset structure and the LDD structure of a TFT are provided with a certain space between the channel of the semiconductor thin film and the source / drain in the plane of the substrate, or a region with a lower carrier concentration than the source / drain. Is the prior art. However, the present invention is characterized in that a region performing such a function can be formed more stably and with higher performance by providing the region in the direction perpendicular to the substrate surface (in the thickness direction).

[0013]

(Embodiment 1) FIG. 1 shows an embodiment of the present invention. A glass substrate is used as the substrate 1. The semiconductor layer 3 is provided on the buffer layer 2. As shown in FIG.
The drain portion has a thicker structure than the channel portion. The semiconductor layer 3 is made of amorphous silicon or polycrystalline silicon. Further, another semiconductor thin film, for example, a thin film of SiGe or SiC may be used. The gate insulating film 4 is made of SiO ₂ , and has a gate electrode 5 and an interlayer insulating film 6.
And a source electrode 7 and a drain electrode 8. FIG.
2 shows an enlarged view of the source section in FIG. The drain section has a similar structure. The source portion of the present invention changes the concentration of the impurity introduced in the thickness direction. The profile can be easily obtained by ion implantation of phosphorus or boron. It should be noted that in the present invention, a region to which almost no impurities are introduced in the impurity profile (that is, a region having an impurity concentration of 10 ¹⁷ cm ⁻³ or less) is present at least about the thickness d of the channel portion of the semiconductor. Having a structure.

FIG. 3 shows a structure of a conventional TFT. In the present invention, a region corresponding to a region A for providing an offset structure or an LDD structure is arranged in a vertical direction (film thickness direction) as shown in FIG. Has formed.

FIG. 4 shows the Id-Vg characteristics of a TFT having a conventional structure.

When the thickness d of the semiconductor layer 3 'is gradually reduced, the off-state leakage current is reduced and the on-state current is also reduced. This is because the injection of carriers from the source side is rate-limited as the semiconductor film thickness is reduced, so that a state in which the on-current cannot be increased is brought about.

However, even when the thickness of the semiconductor layer in the channel portion is less than 30 nm as in the present invention, in the case of the structure in which only the source / drain is thickened,
Since the carrier injection from the drain can be sufficiently performed, the ON current does not decrease and the OFF current can be reduced.

In addition, in the case of the structure according to the present invention, problems such as in-plane variation of characteristics and parasitic capacitance are caused because there is no problem of mask misalignment occurring when an offset structure or an LDD structure in a conventional TFT is manufactured. Does not occur. In other words, if mask alignment is used when fabricating the region A in FIG.
Region becomes asymmetric on the source and drain sides,
Sometimes, the area A on one side is almost completely lost. In the case where the off-current has almost no gate voltage dependence as shown in FIG.
The reliability of the FT characteristics is excellent.

FIG. 5 shows the variation in the substrate surface of a TFT having a channel length of 2 μm. FIG.
5A shows the case of a TFT device having a conventional structure, and FIG. 5B shows the case of a TFT device of the present invention. When a TFT is used in a high-definition panel for the purpose of incorporating a drive circuit, it is expected that the channel length L is shortened to increase the operation speed. Of course, the drive voltage is reduced as the channel length is shortened in consideration of the reliability of the TFT element, but the channel length becomes almost the same as the alignment accuracy of the liquid crystal array process ( For example, in a conventional TFT structure with L = 2 to 1 μm), it is difficult to obtain more stable characteristics and reliability from the viewpoint described above (see FIG. 5A). As in the TFT structure of the present invention, the offset structure or the L
When the DD structure is formed, stable device characteristics and reliability of the TFT can be secured without such a problem (see FIG. 5B). The present invention can be applied not only to the above-described top gate type TFT but also to a bottom gate type TFT.

(Embodiment 2) FIG. 1 shows an embodiment of the present invention. A glass substrate is used as the substrate 1. The semiconductor layer 3 is provided on the buffer layer 2. As shown in FIG. 1, the source / drain portion of the semiconductor layer has a structure that is thicker than the channel portion. The semiconductor layer 3 is made of amorphous silicon or polycrystalline silicon. Further, other semiconductor thin films such as SiGe
Or a thin film such as SiC. The gate insulating film 4 is made of Si
O _2, which includes a gate electrode 5, an interlayer insulating film 6, a source electrode 7 and a drain electrode 8. FIG. 6 shows an enlarged view of the source section of FIG. The drain section has a similar structure. According to the present invention, the source portion is n from the surface in the thickness direction.
+ / N- / i. The concentration of the introduced impurities is determined by adjusting phosphorus and boron to PH at the time of film deposition.
It is introduced and controlled in a gas state such as ₃ or B ₂ H ₆ . It should be noted that in the present invention, a region to which almost no impurities are introduced in the impurity profile (that is, a region having an impurity concentration of 10 ¹⁷ cm ⁻³ or less) is present at least about the thickness d of the channel portion of the semiconductor. Having a structure. The film to be laminated with i / n− / n + is made of the same material as the semiconductor in the channel portion (in the case of Si, S
i), the same material as the semiconductor in the channel portion, or a different phase (when the i-layer is a polycrystalline thin film Si, n− / n + is doped amorphous silicon). Further, the film laminated with i / n− / n + is made of a material different from that of the semiconductor in the channel portion (Si in the case of Si).
C) and may be different in phase from the semiconductor in the channel portion (when the i-layer is a polycrystalline thin film Si, n− / n + is dop
ed amorphous silicon carbon).

FIG. 3 shows the structure of a conventional TFT. In the present invention, a region corresponding to a region A for providing an offset structure or an LDD structure is arranged in a vertical direction (film thickness direction) as shown in FIG. Has formed.

FIG. 4 shows the Id-Vg characteristics of the conventional TFT.

When the thickness d of the semiconductor layer 3 'is gradually reduced, the off-state leakage current is reduced and the on-time current is also reduced. This is because the injection of carriers from the source side is rate-limited as the semiconductor film thickness is reduced, so that a state in which the on-current cannot be increased is brought about.

However, even in the case where the thickness of the source / drain only is increased even when the thickness of the semiconductor layer in the channel portion is less than 30 nm as in the present invention, the source / drain is increased.
Since the carrier injection from the drain can be sufficiently performed, the ON current does not decrease and the OFF current can be reduced.

Further, in the case of the structure according to the present invention, problems such as in-plane variation of characteristics and parasitic capacitance are caused because there is no problem of mask misalignment occurring when an offset structure or an LDD structure is produced in a conventional TFT. Does not occur. In other words, if mask alignment is used when fabricating the region A in FIG.
Region becomes asymmetric on the source and drain sides,
Sometimes, the area A on one side is almost completely lost. In the case where the off-current has almost no gate voltage dependence as shown in FIG.
The reliability of the FT characteristics is excellent.

FIG. 5 shows a state of variation in the substrate surface of a TFT having a channel length of 2 μm. FIG.
5A shows the case of a TFT device having a conventional structure, and FIG. 5B shows the case of a TFT device of the present invention. When a TFT is used in a high-definition panel for the purpose of incorporating a drive circuit, it is expected that the channel length L is shortened to increase the operation speed. Of course, the drive voltage is reduced as the channel length is shortened in consideration of the reliability of the TFT element, but the channel length becomes almost the same as the alignment accuracy of the liquid crystal array process ( For example, in a conventional TFT structure with L = 2 to 1 μm), it is difficult to obtain more stable characteristics and reliability from the viewpoint described above (see FIG. 5A). As in the TFT structure of the present invention, the offset structure or the L
When the DD structure is formed, stable device characteristics and reliability of the TFT can be secured without such a problem (see FIG. 5B). The present invention can be applied not only to the above-described top gate type TFT but also to a bottom gate type TFT.

(Embodiment 3) FIG. 1 shows an embodiment of the present invention. A glass substrate is used as the substrate 1. The semiconductor layer 3 is provided on the buffer layer 2. As shown in FIG. 1, the source / drain portion of the semiconductor layer has a structure that is thicker than the channel portion. The semiconductor layer 3 is made of amorphous silicon or polycrystalline silicon. Further, other semiconductor thin films such as SiGe
Or a thin film such as SiC. The gate insulating film 4 is made of Si
O _2, which includes a gate electrode 5, an interlayer insulating film 6, a source electrode 7 and a drain electrode 8. FIG. 7 shows an enlarged view of the source section of FIG. The drain section has a similar structure. According to the present invention, the source portion is n from the surface in the thickness direction.
+ / N- / i. The concentration of the introduced impurities is determined by adjusting phosphorus and boron to PH at the time of film deposition.
It is introduced and controlled in a gas state such as ₃ or B ₂ H ₆ . Further, a gradient composition structure in which the amount of carbon is gradually increased from below. The amount of carbon on the surface is about 20% of the whole. Here, what should be noted in the present invention is a region where impurities are hardly introduced in the impurity profile (that is, a region having an impurity concentration of 10 ¹⁷ cm ⁻³ or less).
Has a structure in which the thickness of the semiconductor channel portion is about d or more.

FIG. 3 shows the structure of a conventional TFT. In the present invention, a region corresponding to a region A for providing an offset structure or an LDD structure is arranged in a vertical direction (film thickness direction) as shown in FIG. Has formed.

FIG. 4 shows the Id-Vg characteristics of the conventional TFT.

When the thickness d of the semiconductor layer 3 'is gradually reduced, the off-state leakage current is reduced and the on-time current is also reduced. This is because the injection of carriers from the source side is rate-limited as the semiconductor film thickness is reduced, so that a state in which the on-current cannot be increased is brought about.

However, even when the thickness of the semiconductor layer in the channel portion is less than 30 nm as in the present invention, in the case of the structure in which only the source / drain is thickened,
Since the carrier injection from the drain can be sufficiently performed, the ON current does not decrease and the OFF current can be reduced.

Further, in the case of the structure according to the present invention, since there is no problem such as misalignment of the mask which occurs when manufacturing an offset structure or an LDD structure in a conventional TFT, there is a problem of in-plane variation of characteristics and parasitic capacitance. Does not occur. In other words, if mask alignment is used when fabricating the region A in FIG.
Region becomes asymmetric on the source and drain sides,
Sometimes, the area A on one side is almost completely lost. In the case where the off-current has almost no gate voltage dependence as shown in FIG.
The reliability of the FT characteristics is excellent.

FIG. 5 shows the variation in the substrate surface of the TFT having a channel length of 2 μm. FIG.
5A shows the case of a TFT device having a conventional structure, and FIG. 5B shows the case of a TFT device of the present invention. When a TFT is used in a high-definition panel for the purpose of incorporating a drive circuit, it is expected that the channel length L is shortened to increase the operation speed. Of course, the drive voltage is reduced as the channel length is shortened in consideration of the reliability of the TFT element, but the channel length becomes almost the same as the alignment accuracy of the liquid crystal array process ( For example, in a conventional TFT structure with L = 2 to 1 μm), it is difficult to obtain more stable characteristics and reliability from the viewpoint described above (see FIG. 5A). As in the TFT structure of the present invention, the offset structure or the L
When the DD structure is formed, stable device characteristics and reliability of the TFT can be secured without such a problem (see FIG. 5B). The present invention can be applied not only to the above-described top gate type TFT but also to a bottom gate type TFT.

[0034]

According to the present invention, it is possible to provide a structure capable of stably obtaining a TFT having excellent performance and reliability even in a short channel.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a TFT according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a source / drain portion of a TFT according to an embodiment of the present invention.

FIG. 3 is a diagram showing an example of the structure of a conventional TFT.

FIG. 4 is a graph showing the dependence of the Id-Vg characteristic of a TFT having a conventional structure on the thickness of a channel portion.

FIG. 5 is a diagram showing Id-Vg characteristics of a TFT having a conventional structure and a TFT of the present invention in a short channel (L = 2 μm).

FIG. 6 is an enlarged view of a source / drain portion of a TFT according to an embodiment of the present invention.

FIG. 7 is an enlarged view of a source / drain portion of a TFT according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3, 3 'Semiconductor layer of channel part 4 Gate insulating film 5 Interlayer insulating film 6 Gate electrode 7 Source electrode 8 Drain electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 AA01 AA02 AA04 AA06 BB02 CC02 CC08 DD02 FF02 GG01 GG02 GG13 GG15 GG22 GG25 GG28 GG34 GG35 HJ01 HJ04 HJ12 HJ13 HM02 HM05 HM07 HM14

Claims (10)

[Claims] In a semiconductor of a thin film transistor formed on an insulating substrate, the thickness of a source and a drain is larger than the thickness of a semiconductor portion immediately below or immediately above a gate electrode with a gate insulating film interposed therebetween. Thin film transistor. 2. A source and a drain of a thin film transistor, wherein an impurity is distributed in a depth direction from a surface on an electrode forming side, and a high concentration region and a low concentration region of the impurity are formed. 3. The thin film transistor according to claim 1. 3. A source and drain portion of a thin film transistor, a first semiconductor layer doped with an n-type or p-type dopant on a layer not doped with an impurity, and further doped with an n-type or p-type dopant; 2. The thin film transistor according to claim 1, wherein a semiconductor layer having a larger doping amount than the first semiconductor layer is stacked. 4. The thin film transistor according to claim 1, wherein a source and a drain of the thin film transistor have a laminated structure of the same material as the semiconductor thin film of the channel portion and a material different from the semiconductor thin film of the channel portion. 3. The thin film transistor according to claim 1. 5. The thin film transistor according to claim 4, wherein the semiconductor thin film in the channel portion of the thin film transistor is a crystalline Si thin film, and the source and drain portions have a laminated structure of the crystalline Si thin film and the SiC thin film. 3. The thin film transistor according to claim 1. 6. The thin film transistor according to claim 1, wherein the semiconductor thin film in the channel portion of the thin film transistor is an amorphous Si thin film, and the source and drain portions have a laminated structure of the amorphous Si thin film and the SiC thin film. Item 6. A thin film transistor according to item 4. 7. The semiconductor thin film in a channel portion of the thin film transistor is an amorphous Si thin film, and its source and drain portions have a gradient composition layer structure of an amorphous Si thin film and a SiC thin film. The thin film transistor according to claim 4. 8. The thin film transistor has a source and drain portion having a laminated structure of the same material as the semiconductor thin film of the channel portion and the same material as the semiconductor thin film of the channel portion but different crystalline phases or amorphous thin films. The thin film transistor according to claim 1. 9. The thin film transistor according to claim 8, wherein the source and drain portions of the thin film transistor are formed by laminating a crystalline Si thin film and an amorphous Si thin film. 10. The thin film transistor according to claim 1, wherein the thickness of the channel portion is 30 nm or less, and the thickness of the source and drain portions exceeds 30 nm. Thin film transistor.