JPH08204207A - Active matrix display - Google Patents

Abstract

PURPOSE: To reduce the leak current upon turning a switching element off by connecting more than two TFTs in series with a single pixel electrode and controlling a TFT, except those at the opposite ends, through a gate signal line independent from a row select signal line. CONSTITUTION: When the potential on a row select signal line makes a transition to a negative level, TFTs 103, 104 are turned off. Since the potential on a gate signal line 107 is positive, a TFT 105 is turned on. The TFT mainly functions as a capacitor and the source-drain potential of the TFT 105 is equal to that of a pixel cell 106. When the potential on the gate signal line 107 makes a transition to a negative level, capacitance of the TFT 105 decreases abruptly. Consequently, the source-drain voltage of the TFT 105 is increased in order to hold the charges stored in the TFT 105. With such arrangement, potential drop is controlled and the off-current can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit and an element for improving the image quality of a display screen of an active matrix display device. In particular, the present invention uses a circuit having a thin film transistor (TFT) as a switching element,
The active layer of (1) is composed of a silicon semiconductor crystallized using a catalytic element that promotes crystallization of amorphous silicon.

[0002]

2. Description of the Related Art What is an active matrix type display device?
A display device having a mechanism in which a switching element is provided in each pixel and a signal supplied from an image signal line is supplied to the pixel by the switching element, and a large-capacity display can be performed more clearly than a simple matrix display device. it can. Conventionally, a TFT using an amorphous silicon semiconductor has been used as a switching element. However, a TFT using a crystalline silicon semiconductor is
Since the operating speed is 10 times or more, it is suitable for large-capacity display, and recently, development has been advanced in this respect. However, the crystalline silicon semiconductor has some problems.

The first problem was the problem of crystallization of silicon. Crystalline silicon is obtained by crystallizing amorphous silicon. Conventionally, two methods have been known. One is a method of irradiating strong light from a laser or the like to instantaneously crystallize it, which is called optical annealing. The problem with this method is that a stable high-energy laser oscillator cannot be obtained, resulting in poor reproducibility and mass productivity.

Another method is called a thermal annealing method or a solid phase growth method. Usually, thermal annealing is performed at a temperature of 600 ° C. or higher to cause amorphous silicon to be solid phase grown and crystallized. . In this method, the time required for crystallization depends on the annealing temperature, and at a high temperature of about 1000 ° C., crystallization can be completed within 1 hour. However, there is no other substrate than quartz that can be used at such a high temperature, and the substrate cost has increased. Also, the crystallinity of the obtained silicon film was not preferable.

On the other hand, a silicon film having good crystallinity was obtained by annealing at about 600 ° C., which can be used for many borosilicate glasses, but the time required for crystallization was 24 hours or more, and mass productivity was improved. There was a problem with. The second problem is that the TFT using crystalline silicon has a large leak current (OFF current) when a reverse bias voltage is applied to the gate electrode. This is considered to be caused by crystal grain boundaries, which has been the biggest problem in manufacturing an active matrix display device using crystalline silicon.

In the case of an N-channel TFT, an OFF current when V _GS is negatively biased is formed between the P-type layer induced on the surface of the semiconductor thin film and the N-type layers of the source region and the drain region. Defined by the current flowing through the PN junction. Since many traps exist in the semiconductor thin film (especially at grain boundaries), this PN junction is incomplete and a junction leak current easily flows. The OFF current increases as the gate electrode is biased more negatively because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases and the width of the energy barrier of the PN junction narrows, so that electric field concentration occurs. This is because the junction leak current increases.

The OFF current thus generated largely depends on the source / drain voltage. For example, it is known that the OFF current dramatically increases as the voltage applied between the source / drain of the TFT increases. That is, when the voltage of 5 V is applied between the source / drain and when the voltage of 10 V is applied, the OFF current of the latter may be 10 times or 100 times as large as that of the former. Further, such non-linearity also depends on the gate voltage. Generally, when the reverse bias value of the gate electrode is large (a large negative voltage in the N-channel type), the difference between the two is remarkable.

[0008]

With respect to the first problem described above, the present inventors have found that the crystallization of amorphous silicon can be promoted by adding a small amount of nickel, platinum, iron, cobalt, palladium or the like. (JP-A-6-244104). These elements to be added are called catalyst elements, and as a result, it has become possible to achieve crystallization typically by thermal annealing at 550 ° C. for 4 hours or at a lower temperature for a shorter time. In addition, in the conventional thermal annealing method, amorphous silicon was hardly crystallized unless it was thicker than 1000 Å, but when a catalytic element was used, it was 1000 Å or less, typically 300-
It was found that sufficient crystallization occurs even at a thickness of 800Å.

As a result of the research conducted by the present inventor, TF was obtained by using silicon crystallized by using these catalytic elements.
In the case of producing T, from the viewpoint of the crystallization step,
From the viewpoint of characteristics and reliability, it has been clarified that the residual concentration of the catalytic element in silicon is preferably 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ .

Thus, although the first problem has been solved, the second problem has remained unsolved. On the contrary, a silicon film crystallized using a catalytic element has a crystal growth that progresses acicularly (granular growth in the conventional thermal annealing method) and a major axis of the crystal of several μm or more (conventional thermal annealing method). Since it is as large as 1 μm or less), the TFT characteristics are greatly affected by the crystal grain boundaries, and a large variation in the OFF current has emerged as a new problem. Typically, the OFF current fluctuated by three orders of magnitude, from 1000 pA to 1 pA.

FIG. 7A shows a schematic diagram of a conventional example of an active matrix display device. A region (204) surrounded by a broken line in the drawing is a display region, and a TFT (20
1) are arranged in a matrix. The TFT (2
The wiring connected to the source electrode of 01) is the image (data) signal line (206) and the row selection signal line (205) connected to the gate electrode of the TFT (201). The driving principle of this circuit is as shown in FIG.
Row selection is performed by inputting pulses with slightly shifted timings to the row selection signal lines of the Nth row, the (N + 1) th row, and the (N + 2) th row.

In the circuit of FIG. 7A, the switching element is the TFT (201), and data switching is performed according to the signal of the row selection signal line (205).
The liquid crystal cell (203) is driven. Auxiliary capacity (202)
Is a capacitor for reinforcing the capacity of the liquid crystal cell and is used for holding image data. In order to perform a uniform display over the entire surface of the matrix, it is necessary that all TFTs have the same characteristics. Above all, OFF
The current is required to be 10 pA or less, preferably 1 pA or less. If the OFF current of the TFT is 10
Some of them with 00 pA cannot hold enough electric charge, and the video signal is lost instantly.

If there are several such defective TFTs in all the pixels, this is not a problem, but if it reaches several percent, the display becomes very difficult to see. In particular, a display defect is remarkable in a TFT using crystalline silicon obtained by using the above-mentioned catalytic element.

[0014]

The present invention has been made in view of the above problems. That is, the present invention relates to an active matrix circuit, in which at least three TFTs are connected in series to one pixel electrode, and at least one TF except both ends of the series-connected TFTs.
A circuit which is characterized in that T is controlled by a signal line (hereinafter referred to as a gate signal line) that supplies a signal independent of the row selection signal line, while other TFTs are controlled by the row selection signal line. Used as an element.

Here, the fact that the signal on the gate signal line is independent of the signal on the row selection signal line means that it is not the same as the signal on the row selection signal line, and some kind of synchronization with the signal on the row selection signal line is taken. It doesn't matter the signal. Generally, a signal supplied from a circuit different from the circuit (row selection signal circuit) that supplies the signal of the row selection signal line may be used. The circuit may be a signal issued from the row selection signal circuit or a row selection signal circuit. The signal input to the signal circuit may be processed.

In addition to the above, in the present invention, the TFT
The active layer of is composed of crystalline silicon,
¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ of a catalytic element that promotes crystallization of silicon, or a TFT
Is characterized by being crystallized using a catalytic element.

Here, among the TFTs connected in series, one end may be connected to the image signal line and the other end may be connected to the pixel electrode. Further, an LDD region or an offset region may be provided at both ends of the channel of the TFT connected to the pixel electrode among the above TFTs. The basic idea of the present invention is TF
Connect three or more Ts, of which the central TF
At least one of Ts is characterized in that its gate electrode is connected to a gate signal line different from the row selection signal line and is driven by a signal of the signal line.

In the example of FIG. 1A, Ts connected in series are used.
FT of FT (103), (104), (105)
The source of T (103) is connected to the image signal line (101), and the drain of the TFT (104) is connected to the pixel electrode (1).
06). The gate electrodes of the TFTs (103) and (104) are controlled by the row selection signal line (102). The gate electrode of the central TFT (105) is connected to the gate signal line (107) and is driven separately from the TFTs (103) and (104) connected to the row selection signal line (102). In addition, the auxiliary capacitance (10
8) may be added.

An example of an actual circuit shown in the circuit diagram of FIG. 1A is shown in FIG. A method for manufacturing this circuit will be described in an embodiment with reference to FIGS. 4A and 4B, and therefore only an outline will be described here. The circuit consists of three TFTs (103), (10) on one silicon semiconductor film (active layer).
4) and (105) (each of which shows a conceptual region with a dotted line) are formed, and gate electrodes (4
05), (407), (406) are provided across it. Then, in the semiconductor region, the leftmost region (41
1) (= source of TFT (103)) has an image signal line, and the rightmost region (414) (= TFT (104))
The pixel electrodes are connected to the respective drains).

The circuit shown in the circuit diagram of FIG. 1A may have the structure shown in FIG. 1D, but the structure shown in FIG. 3 can reduce the occupied area. Less than,
FIG. 3 will be described. First, a substantially U-shaped, U-shaped, or horseshoe-shaped crystalline silicon semiconductor film (30
1) is formed. The semiconductor film is crystallized using a catalytic element, typically 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms /
It contains cm ³ of catalytic element. (Fig. 3 (A))

A row selection signal line (3
02) and the gate signal line (303) are arranged as shown in FIG. That is, the semiconductor film (301) has two intersections with the row selection signal line (302) and one intersection with the gate signal line (303). Gate signal line (3
03) are formed in parallel with the row selection signal line (302).

On the other hand, the TFT (103) of FIG.
The point (104) corresponds to the intersection of two points formed by the row selection signal line (302) and the semiconductor film (301). If N-type (or P-type) doping is performed on the semiconductor film (301) using the row selection signal line (302) and the gate signal line (303) as a mask, the TFT
A region (304) corresponding to the source of (103) and the TFT
A region (307) corresponding to the drain of (104) is formed, and these are connected to the image signal line and the pixel electrode, respectively.

A region (305) corresponding to the drain of the TFT (103) and a region (306) corresponding to the source of the TFT (104) are also formed. That is, in the semiconductor region, a region having a contact with an image signal line, a region having a contact with a pixel electrode, and two N-type (or P-type) separated by a row selection signal line and a gate signal line.
Type) and a region showing a conductivity type are formed. Note that FIG.
As shown in (C), there is no problem even if the gate signal line (303) and the semiconductor film (301) do not completely overlap with each other and a region (308) that partially protrudes from the semiconductor film is formed. What is required is that the regions (305) and (306) are completely separated by the gate signal line (303) and the row selection signal line (302).

As described above, mainly by devising the shape of the semiconductor film (active layer), the degree of integration of the circuit can be improved. If 5 as shown in FIG.
If a switching element having two TFTs is formed, the semiconductor film may be formed into a substantially N-shape or S-shape, and the row selection signal line and the gate signal line may be superposed on this.

[0025]

The specific operation will be described with reference to FIG.
Similar to FIG. 7A, FIG. 2A shows the whole active matrix circuit using the present invention, and the reference numerals are the same as those in FIG. The row selection signal line is supplied with a signal by the shift register Y as in the conventional circuit (FIG. 7), but the gate signal line added by the present invention is provided by another shift register Z.
(Or equivalent circuit) provides the signal.

The signal applied to each signal line is shown in FIG. That is, as in the conventional case, pulses are input to the row selection signal lines of the Nth row, the (N + 1) th row, and the (N + 2) th row with a staggered timing. On the other hand, the gate signal lines of the Nth row, the (N + 1) th row, and the (N + 2) th row are also
A signal is applied, but it is convenient that these pulses have some overlap and are synchronized with the pulse of the row selection signal line of each row. However, TFT (10
3) and (104), when the gate capacitance of the TFT (105) is large, the pulse width may be made larger than the pulse of the row selection signal line as shown in FIG. 2 (B).

An operation example will be described with reference to FIG. Of course, other operations are also possible. Focusing on the (N + 2) th row, a pulse is first applied to the gate signal line (107), and the central TFT (105) is turned on. At this time, the image data of another row is applied to the image signal line 101. However, the row selection signal line is kept at a negative potential, and the TFTs on both sides of the TFT (105) are
(103) and (104) are in the OFF state, and the data at this time is not taken into the pixel cell (106).
(Period in FIG. 2B, a)

After this state continues for a while, the (N +
2) The potential of the row selection signal line of the row is changed to positive, and only at this time the discharge of the pixel cell (106) and the image signal line (10).
The data of 1) is charged. Here, it is charged to a positive voltage. At this time, the TFT (103)
All of (104) are in the ON state. (Fig. 2
(B), b period)

Then, the potential of the row selection signal line is changed to negative and the TFTs (103) and (104) are turned off. However, since the potential of the gate signal line (107) is still positive, the TFT (105) is in the ON state. Since the TFT at this time mainly functions as an electrostatic capacitance, the potential of the source / drain of the TFT (105) is almost the same as the potential of the pixel cell (106). (Fig. 2
(B), c period)

Next, when the potential of the gate signal line (107) is changed to negative, the electrostatic capacity formed in the TFT (105) is rapidly reduced. Then, the charges accumulated in the TFT (105) (this is the TFT (103), (10
4) is in the OFF state, it is difficult to flow to another), so that the voltage of the source / drain of the TFT (105) becomes high (absolute value becomes large). That is, a region having a very high voltage is formed around the TFT (105), and even if the potential of the image signal line becomes negative due to the existence of this region, the potential of the TFT (105) may decrease. Priority is given to suppressing the electric charge from flowing out from the pixel cell (106) and the potential drop.

On the contrary, from the relationship of the potential difference, the TFT (105)
Current flows from the pixel cell to the pixel cell (106). However, from the ratio of the electric charge accumulated in the TFT (105) and the electrostatic capacity of the pixel cell, even if all the electric charge accumulated in the TFT (105) flows into the pixel cell, the potential fluctuation of the pixel cell hardly occurs. Does not happen. By the above action,
The OFF current can be reduced. (Period of FIG. 2B, d and e) Hereinafter, the same operation is repeated.

As described above, the present invention has an effect that the OFF current can be reduced on average.
It is also possible to drastically reduce the probability of occurrence of a switching element having a large current (defective switching element). For example, in FIG. 1A, the TFT (103) or (10
Even if either one of 4) has a very large OFF current, the other one is normal.
This is to show the effect of suppressing the OFF current as a whole.
That is, both of the TFTs (103) and (104) are O.
The probability of a large FF current defect is very small. As a result, the OFF current of the switching element is 99% of that of the TFT.
Could be 1 pA or less, 99.99% could be 10 pA or less, and the probability of occurrence of a switching element of 100 pA or more that causes an image failure could be 1 ppm or less.

If LDD regions or offset regions are placed in the channels of the TFTs (103) and (104),
Since those regions become drain resistance and source resistance,
It goes without saying that the electric field strength of the drain junction can be relaxed and the OFF current can be further reduced. In particular, it is effective to form LDD (low concentration impurity) regions and offset regions on both ends of the channel of the TFT on the pixel electrode side.

In the example of FIG. 1A, the central TFT has the same conductivity type as the TFTs at both ends thereof (in this case, N-channel type).
However, as shown in FIG. 1B, the conductivity type may be reversed (that is, P-channel type). However, in that case, the signal applied to the gate electrode of the central TFT (115) is opposite to that in the case of FIG. (Fig. 1 (B))

Further, by connecting more TFTs, as shown in FIG.
A circuit as shown in (C) may be configured. In this case, the effect of reducing the OFF current is further increased. Of course, in the case of FIG. 1C, five TFTs are used in total, but even if seven or nine TFTs are used, the effect of reducing the OFF current does not increase so much. Considering the circuit configuration and the like, it is preferable that the number of TFTs is 5 or less.

[0036]

【Example】

[Embodiment 1] This embodiment relates to a manufacturing process of the circuit shown in FIG. In this embodiment, an offset gate is formed by anodizing the gate electrode,
The feature is that the OFF current is further reduced. A technique for anodizing the gate electrode is disclosed in Japanese Patent Laid-Open No. 5-267.
667.

4A to 4D show the steps of this embodiment. First, the substrate (401) (Corning 7059, 1
(00 mm × 100 mm), a silicon oxide film (402) is formed as a base film on the surface of 1000 to 5000 Å, for example, 3000.
Film was formed on Å. The silicon oxide film was formed by decomposing and depositing TEOS by the plasma CVD method. This step may be performed by a sputtering method.

After that, an amorphous silicon film of 300 to 1500 is formed by plasma CVD method or LPCVD method.
Å, for example, 500Å was deposited and crystallized by a thermal annealing method. At that time, according to the technique disclosed in JP-A-6-144204, a small amount of nickel was added as a catalyst element for crystallization. As a method for adding nickel, a 1 ppm nickel acetate aqueous solution was applied and dried on an amorphous silicon film having a thin silicon oxide film formed thereon. Then, this was left to stand at 550 degreeC atmosphere for 4 hours.

After the above thermal annealing process, optical annealing such as laser irradiation may be added to further improve the crystallinity. Then, the crystallized silicon film was etched to form island regions (403). Further, a gate insulating film (404) was formed on this. Here, the thickness is 700 to
A silicon oxide film having a thickness of 1500 Å, for example, 1200 Å was formed. This step may be performed by a sputtering method.

After that, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 Å to 3 μm, for example, 5000 Å, is formed by the sputtering method and is etched. Gate electrodes (405), (406) and (407) were formed. (Fig. 4 (A))

Then, the gate electrode is anodized by passing an electric current in an electrolytic solution to a thickness of 500 to 2500Å, for example,
2000 liters of anodic oxide was formed. The electrolytic solution used was prepared by diluting L-tartaric acid in ethylene glycol to a concentration of 5% and adjusting the pH to 7.0 ± 0.2 using ammonia. The substrate was immersed in the solution, the + side of the constant current source was connected to the gate electrode on the substrate, the platinum electrode was connected to the − side, and voltage was applied at a constant current of 20 mA.
Oxidation was continued until 50V was reached. Furthermore, 150V
Oxidation was continued in the constant voltage state until the current became 0.1 mA or less. As a result, aluminum oxide coatings (408), (409) and (410) having a thickness of 2000Å were obtained.

After that, impurities (phosphorus in this case) are self-alignedly implanted into the island-shaped region (403) by ion doping using the gate electrode portion (that is, the gate electrode and the anodic oxide coating around the gate electrode) as a mask. Then, an N-type impurity region was formed. Here, phosphine (PH ₃ ) was used as the doping gas. The dose amount in this case is 1 ×
10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , acceleration voltage is 60 to 9
0 kV, for example, the dose amount is 1 × 10 ¹⁵ atoms / cm ² ,
The acceleration voltage was 80 kV. As a result, N-type impurity regions (411) to (414) were formed. A state of the element viewed from above at this stage is shown in FIG. (Fig. 4
(B))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurity regions (411) to (414). Laser energy density is 200 ~
400 mJ / cm ² , preferably 250-300 mJ /
cm ² was suitable. This step may be performed by thermal annealing. In particular, it contains a catalytic element (nickel) and can be activated by thermal annealing at a lower temperature than in the usual case (JP-A-6-267989). Although the N-type impurity region was formed in this manner, it can be seen that in the present example, the impurity region is distant from the gate electrode by the thickness of the anodic oxide, forming a so-called offset gate.

Next, plasma CVD is performed as an interlayer insulating film.
A silicon oxide film (415) was formed to a thickness of 5000Å by the method. At this time, TEOS and oxygen were used as source gases. Then, the interlayer insulating film (415) and the gate insulating film (4
04) is etched and the N-type impurity region (41
A contact hole was formed in 1). After that, an aluminum film was formed by a sputtering method and etched to form a source electrode / wiring (416). This is an extension of the image signal line. (Fig. 4 (C))

After that, a passivation film (417) was formed. Here, a silicon nitride film is formed by a plasma CVD method using a mixed gas of NH ₃ / SiH ₄ / H ₂
A film having a film thickness of 0 to 8000 Å, for example, 4000 Å was formed as a passivation film. Then, the passivation film (417), the interlayer insulating film (415) and the gate insulating film (404) were etched to form a contact hole for the pixel electrode in the N-type impurity region (414).
Then, a film of indium tin oxide (ITO) was formed by a sputtering method, and this was etched to form a pixel electrode (418).

In this way, three TFTs connected in series
(421), (420), and (422) were formed. Of these, the gate electrode (406) supplies a signal from the gate signal line, and the gate electrodes (405) and (407).
Is used by supplying a signal from the row selection signal line. (Fig. 4
(D))

As shown in FIG. 4E, the passivation film (417), the interlayer insulator (418) and the gate insulating film (404) are etched to contact the N-type impurity region (414) with the pixel electrode contact. A contact hole may be formed on the gate electrode (406) at the same time when the hole is formed. Anodic oxide (aluminum oxide)
Since the etching rate is extremely low with a hydrofluoric acid-based etchant that etches silicon oxide, etching substantially stops at the anodic oxide (409).

Then, when the pixel electrode (418) is formed so as to cover the hole thus formed, the pixel electrode (418) faces the gate electrode (406) with the anodic oxide film (409) interposed therebetween. Then, the capacitor (419) can be formed. This capacity corresponds to the auxiliary capacity (10
This is equivalent to 8), and the capacitance can be added without increasing the opaque portion of the pixel electrode (that is, without decreasing the aperture ratio). (Fig. 4 (E))

[Embodiment 2] FIG. 5 shows a process of this embodiment. First, a base silicon oxide film (50) is formed on a substrate (501).
2) (thickness 2000 Å) is deposited, and nickel is used as a catalyst element in the same manner as in Example 1, and the crystalline silicon film crystallized by thermal annealing at 550 ° C. for 4 hours is used to form an island region (503). Was formed. Further, a gate insulating film (504) was formed on this.

Thereafter, an aluminum film having a thickness of 5000 Å was formed by the sputtering method. Further, in order to improve the adhesiveness with the photoresist in the subsequent porous anodic oxide film forming step, a thickness of 100 is formed on the surface of the aluminum film.
You may form a thin anodic oxide film of -400 Å. Then, a photoresist having a thickness of about 1 μm was formed by spin coating. Then, the gate electrodes (505), (50
6) and (507) were formed by etching. On the gate electrode, photoresist masks (508), (5
09) and (510) were left. (Figure 5 (A))

Next, the substrate is immersed in an aqueous solution of 10% oxalic acid, and the + side of the constant current source is connected to the gate electrode (505) on the substrate,
It was connected to (507) and a platinum electrode was connected to the negative side to carry out anodization. This technique is disclosed in JP-A-6-33861.
2 is disclosed. That is, 5 to 50 V, for example,
By performing anodization at a constant voltage of 8 V for 10 to 500 minutes, for example, 200 minutes, porous anodic oxides (511) and (512) having a thickness of 5000 Å are formed on the gate electrodes (505) and (507). Formed on the side. The obtained anodic oxide was porous. Since the mask materials (508) and (510) were present on the upper surface of the gate electrode, anodic oxidation hardly proceeded. In addition, the gate electrode (50
No current was passed through 6), so no anodic oxide was formed. (Fig. 5 (B))

After that, the mask material was removed to expose the upper surface of the gate electrode. Then, in the same manner as in Example 1, L-tartaric acid was diluted with ethylene glycol to a concentration of 5%, and the gate electrode (505), (in the electrolytic solution whose pH was adjusted to 7.0 ± 0.2 using ammonia). 506) and (507) were anodized by applying an electric current to form an anodic oxide having a thickness of 500 to 2500Å, for example, 2000Å. As a result, a dense aluminum oxide film with a thickness of 2000Å (51
3), (514) and (515) were obtained.

After that, impurities (boron in this case) are implanted into the island-shaped silicon region (503) in a self-alignment manner by using the gate electrode portion as a mask by an ion doping method, and P
A type impurity region was formed. Here, diborane (B ₂ H ₆ ) was used as the doping gas. In this case, the dose amount is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , the acceleration voltage is 40 to 90 kV, for example, the dose amount is 1 × 10 ¹⁵ c.
m ⁻² , and the acceleration voltage was 65 kV. As a result, P-type impurity regions (516) to (519) were formed. (Fig. 5
(C))

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurity regions (516) to (519). As described in Example 1, this step may be performed by thermal annealing. Next, as a interlayer insulating film, a silicon oxide film (52
0) was deposited to a thickness of 3000Å. Further, the interlayer insulating film (520) and the gate insulating film (504) were etched to form a contact hole in the P-type impurity region (516). After that, an aluminum film was formed by a sputtering method and etched to form an image signal line (521). (FIG. 5 (D))

Then, a passivation film (522) is formed, and a passivation film (522) and an interlayer insulating film (5) are formed.
20), the gate insulating film (504) is etched to form an opening on the anodic oxide film (514), and P
A contact hole for the pixel electrode was formed in the type impurity region (519). Then, after forming an ITO film by a sputtering method, this was etched to form a pixel electrode (523). The pixel electrode (523) faces the gate electrode (506) by using the anodic oxide coating (514) as a dielectric, similarly to FIG. 4 (E), and forms an auxiliary capacitance (524). (Fig. 5 (E))

Through the above steps, the switching element of the active matrix circuit having the P-channel type thin film transistors (526), (527), (525) and the auxiliary capacitance (524) was formed. In this embodiment,
Although the conductivity type of the transistor is opposite, it is the same as the circuit shown in FIG. In this embodiment, the thin film transistors (526) and (52) that need to suppress the OFF current.
Regarding 7), the offset width is made wider than in the case of the second embodiment. On the other hand, the presence of the offset is not necessary in the MOS capacitor, so the offset was made small.

Example 3 FIG. 6 shows how a circuit is formed using the present invention. A publicly known technique (or the technique shown in the first and second embodiments) may be used for a specific process, and thus will not be described in detail here. First,
By the means shown in Example 1, the amorphous silicon film is crystallized using a catalytic element, and this is etched to form a substantially U-shaped (or U-shaped or horseshoe-shaped) semiconductor region (active layer) ( 601) to (604) were formed. Here, when the active layer (601) is used as a reference, the active layer (602) means the next row and the next row, the active layer (603) means the next row and the current row, and the active layer (604) means the next row and the next row.
(Fig. 6 (A))

After that, a gate insulating film (not shown) is formed, and the same film is further etched to obtain row selection signal lines (605) and (606) and gate signal lines (607) and (608). Was formed. Here, the positional relationship between the row selection signal line and the gate signal line and the active layer is the same as in FIG. (FIG. 6B) Then, after doping the active layer, a contact hole (for example, shown in (611)) is formed at the left end of each active layer, and the image signal lines (609), ( 6
10) was formed. (Fig. 6 (C))

After that, pixel electrodes (612) and (613) were formed in the region surrounded by the row selection signal line and the image selection signal line. In this way, the TFT (614) is formed in the gate signal line (607) and the active layer (601). At this time, the gate signal line (607) is different from the pixel electrode (613) in the row. It is arranged so as not to overlap and to overlap the pixel electrode (612) on one row. That is, in the case of the pixel electrode (613), the gate signal line (608) one row below overlaps with the pixel electrode (613), and the capacitance (6
15) was formed. Gate signal lines (607), (60
8) is supplied with a pulse signal synchronized with the row selection signal line, but is maintained at a constant voltage for most of the time (FIG. 2).
(See (B)), an electrostatic capacitance is formed between the gate signal line and the pixel electrode. (Figure 6 (D))

In this way, by arranging the gate signal line so as to overlap the pixel electrode one row above (or below) the row, the circuit as shown in FIG. 6E is constructed.
The capacitor (615) corresponds to the capacitor (108) in FIG. 1A, and a capacitor can be added without substantially lowering the aperture ratio, which improves the integration degree of the circuit. It was effective. By the way, FIG. 6F shows a conventional unit pixel (see FIG. 7A) formed in a region surrounded by row selection signal lines and image signal lines at the same intervals. 205), the area blocked by this embodiment is shown in FIG.
(D)), and in this embodiment, the semiconductor region (6
01) are almost the row selection signal lines (605), (60)
Since the structure is covered with 7), the aperture ratio is not reduced. On the contrary, in the conventional one (FIG. 6 (F)),
A decrease in the aperture ratio is recognized due to the gate electrode separated from the row selection signal line.

[0061]

As described above, according to the present invention, a plurality of T
By properly connecting the FT, the voltage drop of the liquid crystal cell could be suppressed. The present invention is effective in applications in which higher image display is required. That is,
In the case of expressing extremely delicate shades of 256 gradations or more, it is necessary to suppress the discharge of the liquid crystal cell to 1% or less during one frame. None of the conventional methods are suitable for this purpose.

In the above description, the liquid crystal display was mainly described, but the active matrix circuit of the present invention is not limited to the liquid crystal display.
Since it is necessary to hold the voltage even in a display using electroluminescence (EL) and a display using plasma emission (plasma display = PDP), it is obvious that it can be used for these. As described above, the present invention is industrially useful.

[Brief description of drawings]

FIG. 1 shows an example of a switching element of an active matrix circuit according to the present invention.

FIG. 2 shows a circuit diagram and an operation example of a switching element of an active matrix circuit of the present invention.

FIG. 3 shows an arrangement example of semiconductor regions and gates of switching elements of an active matrix circuit of the present invention.

FIG. 4 shows a manufacturing process of a switching element of the active matrix circuit according to the first embodiment.

FIG. 5 shows a manufacturing process of a switching element of an active matrix circuit according to a second embodiment.

FIG. 6 shows a manufacturing process of a switching element of an active matrix circuit according to a third embodiment.

FIG. 7 shows a circuit diagram and an operation example of a switching element of a conventional active matrix circuit.

[Explanation of symbols]

101 ... Image signal line 102 ... Row selection signal line 103 to 105 ... Thin film transistor (N-channel type) 106 ... Pixel cell 107 ... Gate signal line 108 ... Auxiliary capacitance 111 ... Image signal line 112 ... Row selection signal line 113, 114 ... Thin film transistor (N-channel type) 115 ... Thin film transistor (P-channel type) 116 ... Pixel cell 117 ··· Gate signal line 118 ··· Auxiliary capacitance 121 ··· Image signal line 122 ··· Row selection signal line 123 to 127 ··· Thin film transistor (N-channel type) 128 ··· Pixel cell 129 ・ ・ ・ ・ Gate signal line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/12 R H01L 29/78 617 A 627 G

Claims (13)

[Claims] 1. An active matrix display device having pixel electrodes and image signal lines arranged in a matrix, wherein at least three thin film transistors are connected in series to one pixel electrode, and the series connection is made. Among the thin film transistors, at least one thin film transistor other than the one connected to the image signal line is controlled by a gate signal line supplying a signal independent of the row selection signal line, and a circuit is defined as a switching element. An active matrix display device comprising: 2. The active layer of the thin film transistor according to claim 1, wherein the active layer is made of crystalline silicon.
An active matrix display device comprising a catalytic element that promotes crystallization of silicon in an amount of 0 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ . 3. The active matrix display device according to claim 1, wherein the gate signal line is arranged in parallel with the row selection signal line and between the row selection signal lines. 4. The LD according to claim 1, wherein LDs are provided at both ends of a channel of the thin film transistor connected to the pixel electrode.
An active matrix display device having a D region. 5. An active matrix display device according to claim 1, wherein offset regions are provided at both ends of a channel of the thin film transistor connected to the pixel electrode. 6. An active matrix display device having pixel electrodes arranged in a matrix, and having three or more gate electrodes on one island-shaped crystalline silicon semiconductor film provided for each pixel electrode. The semiconductor film is provided with an N-type or P-type region doped using the gate electrode as a mask, and one of regions at both ends of the N-type or P-type region provided in the semiconductor region is provided. Is connected to a pixel electrode, and the other is connected to an image signal line. One or two of the gate electrodes adjacent to any one gate electrode connected to the row selection signal line of the pixel
2. The active matrix display device according to claim 1, wherein each of the gate electrodes is controlled by a gate signal line independent of a row selection signal line of the pixel. 7. The semiconductor film according to claim 6, wherein the semiconductor film is 1
× 10 ¹⁵ An active matrix display device characterized by containing a catalyst element that promotes crystallization of to 1 × 10 ¹⁹ atoms / cm ³ of silicon. 8. The active matrix display device according to claim 6, wherein the crystalline silicon semiconductor film is approximately U-shaped, U-shaped, or horseshoe-shaped. 9. In an active matrix display device, a plurality of image signal lines, a plurality of row selection signal lines arranged substantially parallel to the image signal lines, and one row selection signal line in parallel with each other. A gate signal line arranged, a pixel electrode provided in a region surrounded by the row selection signal line and the image signal line, and a switching element provided so as to be connected to each of the pixel electrodes, Each of the switching elements has one crystalline silicon semiconductor film having a substantially U-shape, a U-shape, or a horseshoe shape, and at least two intersections with the row selection signal line,
An active matrix display device having at least one intersection with the gate signal line. 10. In an active matrix display device, a plurality of image signal lines, a plurality of row selection signal lines arranged substantially parallel to the image signal lines, and one row selection signal line in parallel with each other. A gate signal line arranged, a pixel electrode provided in a region surrounded by the row selection signal line and the image signal line, and a switching element provided so as to be connected to each of the pixel electrodes, Each of the switching elements has one crystalline silicon semiconductor film and has a region having a contact with the image signal line, a region having a contact with the pixel electrode, the row selection signal line and the gate signal line. An active matrix display device, characterized in that two or more regions separated by means of N-type or P-type conductivity type. 11. The semiconductor film according to claim 9, wherein the semiconductor film contains 1 × 10 ¹⁵ to 1 × 10 ¹⁹ atoms / cm ³ of a catalytic element that promotes crystallization of silicon. Active matrix display device. 12. The active matrix display device according to claim 6, wherein the row selection signal line is made of a material containing aluminum as a main component, and a side surface and an upper surface thereof are covered with anodic oxide. 13. The active matrix display device according to claim 9, wherein the gate signal line does not overlap with the pixel of the row but overlaps with the pixel of the row adjacent to the row.