JPH06188419A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPH06188419A JPH06188419A JP4335720A JP33572092A JPH06188419A JP H06188419 A JPH06188419 A JP H06188419A JP 4335720 A JP4335720 A JP 4335720A JP 33572092 A JP33572092 A JP 33572092A JP H06188419 A JPH06188419 A JP H06188419A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- aluminum
- film transistor
- metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims abstract description 24
- 239000012212 insulator Substances 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 238000007743 anodising Methods 0.000 claims description 3
- 229910052758 niobium Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 9
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 abstract description 8
- 229910001936 tantalum oxide Inorganic materials 0.000 abstract description 8
- 150000002739 metals Chemical class 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 239000010936 titanium Substances 0.000 description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- 239000010407 anodic oxide Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 239000011159 matrix material Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000018044 dehydration Effects 0.000 description 2
- 238000006297 dehydration reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000788 chromium alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- -1 molybdenum silicide Chemical compound 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000623 nickel–chromium alloy Inorganic materials 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
- H01L21/31687—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures by anodic oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/118—Oxide films
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、カラー液晶表示装置等
に応用される薄膜トランジスタの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor applied to a color liquid crystal display device or the like.
【０００２】[0002]
【従来の技術】一般に、薄膜トランジスタ等の素子を形
成した半導体装置は二層以上の多層配線を行うことが多
い。特にスイッチング用トランジスタをマトリクス状に
設けたアクティブマトリクス型液晶表示装置の場合に
は、Ｘ方向及びＹ方向の配線が必須となり、しかも大画
面を得るためには信号遅延を少なくするため可能な限り
低抵抗の配線が必要とされる。信号遅延を少なくするた
め第一の導電層、すなわち下層の配線やゲート電極にア
ルミニウムが用いられる。更に第二の導電層、すなわち
上層の配線やソース・ドレーン電極と第一の導電層を電
気的に絶縁するため、およびゲート絶縁体を形成するた
め下層の配線やゲート電極上に絶縁層を何らかの手段で
積層する。次に半導体層を形成してゲート電極上の特定
領域に加工した後、第二の導電層を形成して薄膜トラン
ジスタのマトリックスを完成する。2. Description of the Related Art In general, a semiconductor device having an element such as a thin film transistor is often provided with a multilayer wiring of two or more layers. In particular, in the case of an active matrix type liquid crystal display device in which switching transistors are provided in a matrix, wiring in the X direction and the Y direction is indispensable, and in order to obtain a large screen, the signal delay is reduced as much as possible. Resistor wiring is required. To reduce the signal delay, aluminum is used for the first conductive layer, that is, the lower wiring and gate electrode. Further, in order to electrically insulate the second conductive layer, that is, the upper wiring or the source / drain electrode from the first conductive layer, and to form a gate insulator, an insulating layer may be formed on the lower wiring or the gate electrode. Laminate by means. Next, a semiconductor layer is formed and processed in a specific region on the gate electrode, and then a second conductive layer is formed to complete the matrix of the thin film transistor.
【０００３】[0003]
【発明が解決しようとする課題】 従来の技術の項で説
明した薄膜トランジスタのマトリックスにおいては、第
一の導電層（下層配線とゲート電極）と第二の導電層
（上層配線とソース・ドレーン電極）の間で短絡すると
いう問題がいままで一番大きな課題であった。特に、ゲ
ート電極や下層配線としてＡｌ金属を用いた場合、その
加熱工程、たとえば電極や配線パターン形成のフォトリ
ソ工程でレジスト塗布前に、約１６０℃、５分のデハイ
ドレーションを行うことによって、Ａｌ薄膜にヒロック
と呼ばれる突起が発生する。In the matrix of the thin film transistor described in the section of the prior art, the first conductive layer (lower layer wiring and gate electrode) and the second conductive layer (upper layer wiring and source / drain electrode) are used. Until now, the problem of short-circuiting has been the biggest issue. In particular, when Al metal is used for the gate electrode and the lower layer wiring, dehydration is performed at about 160 ° C. for 5 minutes before resist coating in the heating step, for example, the photolithography step of forming the electrode and the wiring pattern, so that an Al thin film is formed. A protrusion called a hillock occurs on the.
【０００４】このヒロックは更に絶縁体層、半導体層、
第二の導電層、すなわちソース・ドレーン電極や上層配
線を形成して最終的に薄膜トランジスタのマトリックス
を作成し駆動した時、上層と下層配線間ショート不良の
原因になる。ヒロックが絶縁体層の膜厚均一性を損ね、
局部的な電界集中によってショート不良を引き起こすと
考えられる。これに対処するために、Ａｌに少量のＴａ
やＴｉを添加したゲート電極が検討されているが、これ
らはヒロックに対して効果はあるものの、電気抵抗が純
粋なＡｌの約５倍と高くなり、ゲート信号遅延の観点か
ら好ましくない。従って、純粋なＡｌと同程度の低い電
気抵抗を持ち、かつヒロックのない下層配線やゲート電
極を作成する方法が望まれている。This hillock further includes an insulator layer, a semiconductor layer,
When the second conductive layer, that is, the source / drain electrodes and the upper layer wiring are formed and finally the matrix of the thin film transistor is formed and driven, it causes a short circuit between the upper layer and the lower layer wiring. Hillocks impair the thickness uniformity of the insulator layer,
It is considered that short circuit failure is caused by local electric field concentration. To deal with this, a small amount of Ta is added to Al.
Although gate electrodes added with Ti and Ti have been studied, they are effective against hillocks, but their electric resistance is about 5 times higher than that of pure Al, which is not preferable from the viewpoint of gate signal delay. Therefore, there is a demand for a method of forming a lower layer wiring and a gate electrode which have a low electric resistance comparable to pure Al and are free of hillocks.
【０００５】本発明はかかる点に鑑み、多層配線間の短
絡を防止し、歩留まりの高い信頼性に優れた薄膜トラン
ジスタを得るため、第一の導電層に対してヒロック発生
を効果的に抑制する製造方法を提供するものである。In view of the above points, the present invention effectively suppresses hillock generation in the first conductive layer in order to prevent short circuit between multilayer wirings and to obtain a thin film transistor having high yield and high reliability. It provides a method.
【０００６】[0006]
【課題を解決するための手段】薄膜トランジスタの第一
の導電層、すなわち下層配線やゲート電極を、まず低抵
抗のアルミニウム系金属で形成し、続いてアルミニウム
系金属のヒロック発生を防ぐために他の陽極酸化可能な
金属を積層した。下層配線やゲート電極のパターンをエ
ッチング加工により形成した後、その表面を陽極酸化し
て陽極酸化可能な金属全部とアルミニウム系金属の一部
を絶縁体層に変換した。したがって、この段階で下層配
線とゲート電極の上に酸化アルミニウムと他の陽極酸化
可能な金属の酸化物薄膜が形成された積層構造ができ
る。更に、一般に行われているように窒化珪素薄膜を積
層してゲート絶縁体層を完成する。結局薄膜トランジス
タのゲート絶縁体層は酸化アルミニウム、陽極酸化可能
な金属の酸化物および窒化珪素の３層膜となり、かつ下
地のゲート電極にヒロックがないので、従来の２層膜で
下地にヒロックが発生している場合と比較して欠陥やピ
ンホールの少ない絶縁体層が形成され、下層配線、ゲー
ト電極と上層配線、ソース・ドレーン電極の間の短絡不
良，すなわち一般にゲート・ソース短絡を効果的に防止
できる。A first conductive layer of a thin film transistor, that is, a lower wiring or a gate electrode is first formed of a low resistance aluminum-based metal, and then another anode is formed to prevent hillock generation of the aluminum-based metal. Laminated oxidizable metal. After the pattern of the lower wiring and the gate electrode was formed by etching, the surface thereof was anodized to convert all the anodizable metal and part of the aluminum-based metal into an insulator layer. Therefore, at this stage, a laminated structure in which an oxide thin film of aluminum oxide and another anodizable metal is formed on the lower wiring and the gate electrode can be obtained. Further, a silicon nitride thin film is laminated as is generally done to complete the gate insulator layer. After all, the gate insulator layer of the thin film transistor becomes a three-layer film of aluminum oxide, an oxide of anodizable metal, and silicon nitride, and there is no hillock in the underlying gate electrode. Insulator layer with fewer defects and pinholes is formed compared to the case of the case where the lower layer wiring, the gate electrode and the upper layer wiring, and the short circuit defect between the source and drain electrodes, that is, the gate-source short circuit is generally effective. It can be prevented.
【０００７】[0007]
【作用】本発明の薄膜トランジスタの製造方法によれ
ば、ヒロックのない低抵抗の下層配線やゲート電極と、
欠陥のない絶縁性に優れたゲート絶縁体層を形成できる
ので、大型高精細度の薄膜トランジスタのマトリックス
の製造に適し、同時に下層配線、ゲート電極と上層配
線、ソース・ドレーン電極間の短絡を防止できる。たと
えば、大型液晶表示パネルに応用して薄膜トランジスタ
ーアレイのゲート・ソース短絡を効果的に防止でき、高
い歩留まりで信頼性の高いパネルを製造することができ
る。According to the method of manufacturing a thin film transistor of the present invention, a hillock-free low resistance lower layer wiring and a gate electrode,
Since it is possible to form a gate insulator layer with excellent insulation without defects, it is suitable for manufacturing a matrix of a large-scale, high-definition thin film transistor, and at the same time can prevent a short circuit between lower layer wiring, gate electrode and upper layer wiring, and source / drain electrodes. . For example, when applied to a large-sized liquid crystal display panel, a gate-source short circuit of a thin film transistor array can be effectively prevented, and a panel with high yield and high reliability can be manufactured.
【０００８】[0008]
【実施例】（実施例１）（図１）は本発明の製造法によ
る液晶ディスプレイ等に応用される透光性基板上の薄膜
トランジスタの断面図と製造過程を示したもので、この
図を中心に用いて説明する。EXAMPLE (Example 1) (FIG. 1) shows a cross-sectional view and a manufacturing process of a thin film transistor on a transparent substrate applied to a liquid crystal display or the like according to the manufacturing method of the present invention. Will be used to explain.
【０００９】（図１（ａ））に示したように、基板１上
に純粋なアルミニウム（Ａｌ）金属、または熱やストレ
ス等によるマイグレーションやヒロックを防止させるた
め不純物として、例えばシリコンを０．５〜２％程度含
んだアルミニウム金属２を２００ｎｍの膜厚に、スパッ
タ法を用いて全面に形成した。さらにその上にタンタル
（Ｔａ）金属３を３０ｎｍの厚さに積層して、そして通
常のドライエッチング法を用いて、所望のゲート電極パ
ターンを形成した。As shown in FIG. 1A, pure aluminum (Al) metal on the substrate 1 or, for example, silicon 0.5 as an impurity for preventing migration or hillock due to heat or stress is used. Aluminum metal 2 containing about 2% was formed to a thickness of 200 nm on the entire surface by sputtering. Further, tantalum (Ta) metal 3 was laminated thereon to a thickness of 30 nm, and a desired gate electrode pattern was formed by using a normal dry etching method.
【００１０】一般に、純粋なアルミニウムではフォトリ
ソ工程のデハイドレーションで１６０℃程度に加熱され
ると、薄膜表面にヒロックと呼ばれる突起が発生する。
上記のように、アルミニウムに少量のシリコン（Ｓｉ）
を添加すると、ヒロックの発生はかなり軽減されるもの
の、完全ではない。Ｓｉの代わりに少量のＴａを添加し
ても同様である。Generally, when pure aluminum is heated to about 160 ° C. by dehydration in the photolithography process, protrusions called hillocks are generated on the surface of the thin film.
As mentioned above, aluminum has a small amount of silicon (Si)
The addition of OH significantly reduces the occurrence of hillocks, but it is not complete. The same applies when a small amount of Ta is added instead of Si.
【００１１】しかし、上記のようにアルミニウム薄膜の
上にさらに重金属のＴａを３０ｎｍの厚さ以上に積層す
ると、ヒロックの発生が効果的に抑制されることを見い
だした。この効果は他の重金属、Ｔｉ、Ｚｒ、Ｎｂ、
Ｗ、およびＭｏによっても実現できた。これらの金属
は、さらに後の工程でゲート絶縁膜の一部を陽極酸化法
によって形成する必要があるため、陽極酸化可能な金属
から選ばれた。However, it has been found that, when the heavy metal Ta is further laminated on the aluminum thin film to a thickness of 30 nm or more as described above, the generation of hillocks is effectively suppressed. This effect is achieved with other heavy metals such as Ti, Zr, Nb,
It could also be realized by W and Mo. These metals were selected from the metals that can be anodized because it is necessary to form a part of the gate insulating film by the anodizing method in a later step.
【００１２】つぎに、（図１（ｂ））に示すようにＴａ
金属の全部とＡｌ金属の一部を陽極酸化してゲート絶縁
体とした。陽極酸化は化成液として酒石酸を１％含む水
溶液とエチレングリコールを容量比で３：７に混合し、
かつアンモニア水でｐＨ７に調節した液を用いた。３０
ｎｍの厚さのＴａ金属は陽極酸化することによって、厚
さが増加し７５ｎｍの酸化タンタル絶縁体４になる。化
成電圧をコントロールして、アルミニウム金属まで化成
を行い、アルミニウム金属表面に厚さ１００ｎｍの酸化
アルミニウム絶縁体５を形成した。結局、ゲートアルミ
ニウム金属の上に酸化アルミニウムと酸化タンタルの積
層膜からなるゲート絶縁体を陽極酸化法により形成し
た。Next, as shown in FIG. 1 (b), Ta
All of the metal and part of the Al metal were anodized to form a gate insulator. The anodization was carried out by mixing an aqueous solution containing 1% tartaric acid and ethylene glycol at a volume ratio of 3: 7 as a chemical conversion liquid,
A liquid whose pH was adjusted to 7 with aqueous ammonia was used. Thirty
The Ta metal with a thickness of nm is anodized to increase the thickness to a 75 nm tantalum oxide insulator 4. By controlling the formation voltage, formation of aluminum metal was performed to form an aluminum oxide insulator 5 having a thickness of 100 nm on the surface of the aluminum metal. Eventually, a gate insulator made of a laminated film of aluminum oxide and tantalum oxide was formed on the gate aluminum metal by the anodic oxidation method.
【００１３】次に、（図１（ｃ））に示すように、プラ
ズマＣＶＤ法により２２５ｎｍの厚さの窒化シリコン
（ＳｉＮx）薄膜６と半導体活性層となるアモルファス
シリコン（ａ-Ｓｉ）７とエッチングストッパとなる窒
化シリコン（ＳｉＮx）８を連続堆積し、エッチングス
トッパのＳｉＮxを島状に加工した。最終的にゲート絶
縁層は酸化アルミニウム１００ｎｍ、酸化タンタル７５
ｎｍ、および窒化シリコン２２５ｎｍの３層膜で構成さ
れ、その全体の厚さを４００ｎｍとした。Next, as shown in FIG. 1C, a silicon nitride (SiN x ) thin film 6 having a thickness of 225 nm and an amorphous silicon (a-Si) 7 to be a semiconductor active layer are formed by a plasma CVD method. Silicon nitride (SiN x ) 8 serving as an etching stopper was continuously deposited, and the etching stopper SiN x was processed into an island shape. Finally, the gate insulating layer is aluminum oxide 100 nm, tantalum oxide 75
nm and a silicon nitride 225 nm three-layer film, and the total thickness thereof was 400 nm.
【００１４】そして、（図１（ｃ））に示すようにａ-
Ｓｉと金属とのオーミック接触を確保するため、ｎ型不
純物としてリンをドープしたアモルファスシリコン（ｎ
+-ａ-Ｓｉ）９及びソース・ドレーンとなる金属薄膜と
して例えばチタン（Ｔｉ）を堆積した。Then, as shown in FIG. 1 (c), a-
In order to ensure ohmic contact between Si and a metal, amorphous silicon (n
+ -a-Si) 9 and, for example, titanium (Ti) was deposited as a metal thin film to be a source / drain.
【００１５】そして、図示はしないがゲート電極を取り
出すための開口部を設けた後、ソース・ドレーンのレジ
ストパターンとエッチングストッパのＳｉＮxをマスク
としてＴｉ、ｎ+-ａ-Ｓｉ、ａ-Ｓｉを一括エッチングし
て、（図１（ｃ））に示すようにソース電極１０とドレ
ーン電極１１を形成した。最後に、（図１（ｃ））に示
すように透明電極１２として例えばインジウム・スズ酸
化物（ＩＴＯ）をドレイン電極に電気的に接触するよう
選択的に被着形成して薄膜トランジスタを完成した。After forming an opening for taking out the gate electrode (not shown), Ti, n + -a-Si and a-Si are formed by using the resist pattern of the source / drain and SiN x of the etching stopper as a mask. Batch etching was performed to form a source electrode 10 and a drain electrode 11 as shown in FIG. 1 (c). Finally, as shown in FIG. 1 (c), for example, indium tin oxide (ITO) was selectively deposited as the transparent electrode 12 so as to make electrical contact with the drain electrode to complete the thin film transistor.
【００１６】尚、本実施例では、ソース・ドレイン電極
材料としてＴｉを用いたが、ソース・ドレイン電極材料
としてはモリブデンシリサイドのような金属珪化物、あ
るいはアルミニウム、クロム、モリブデン、タンタル、
ニッケル、ニッケル−クロム合金などのような金属材料
を用いることも可能である。Although Ti is used as the source / drain electrode material in the present embodiment, the source / drain electrode material is a metal silicide such as molybdenum silicide, or aluminum, chromium, molybdenum, tantalum, or the like.
It is also possible to use metallic materials such as nickel, nickel-chromium alloys and the like.
【００１７】透明電極形成には、透明電極形成工程は必
ずしも薄膜トランジスタ製造工程の最後である必要はな
く、初期の工程で形成し、絶縁層に開口部を設けてドレ
イン電極と電気的に接触させてもよい。In forming the transparent electrode, the transparent electrode forming step does not necessarily have to be the final step of the thin film transistor manufacturing step, and it is formed in the initial step, and an opening is formed in the insulating layer to electrically contact the drain electrode. Good.
【００１８】以上のようにして作成した薄膜トランジス
タ７３７万個（６４０ｘ４８０個からなるトランジスタ
アレイを２４枚作成）のゲート・ソース短絡の欠陥を調
べた。比較のために、ゲート絶縁層としていままでよく
使われてきた２００ｎｍの厚さの酸化アルミニウム陽極
酸化膜と２００ｎｍの窒化シリコン膜の２層膜を用いた
薄膜トタンジスタも同数作成した。The defect of gate-source short circuit of 7.37 million thin film transistors (24 transistor arrays consisting of 640.times.480) prepared as described above was examined. For comparison, the same number of thin film transistors using a two-layer film of an aluminum oxide anodic oxide film having a thickness of 200 nm and a silicon nitride film having a thickness of 200 nm, which has been often used as a gate insulating layer, were prepared.
【００１９】これら２種類の薄膜トランジスタでゲート
・ソース間短絡の数を相対的に比較した結果、２００ｎ
ｍの酸化アルミニウム陽極酸化膜と２００ｎｍの窒化シ
ィコンの２層膜ゲート絶縁層の場合を１００とすると、
本発明の製造法による上記１００ｎｍの酸化アルミニウ
ム陽極酸化膜と７５ｎｍの酸化タンタル陽極酸化膜およ
び２２５ｎｍの窒化シリコンの３層膜でゲート絶縁体層
を構成した薄膜トランジスタアレイは２０の割合であっ
た。また、本発明の方法でアルミニウム金属にシリコン
を１％添加した薄膜トランジスタアレイは１３の割合で
あった。As a result of relatively comparing the number of gate-source short circuits between these two types of thin film transistors, it was found that
When the aluminum oxide anodic oxide film of m and the double-layer gate insulating layer of 200 nm silicon nitride are 100,
The ratio of the thin film transistor array in which the gate insulator layer was composed of the above-mentioned 100 nm aluminum oxide anodic oxide film, 75 nm tantalum oxide anodic oxide film, and 225 nm silicon nitride three-layer film by the manufacturing method of the present invention was 20. In the thin film transistor array in which 1% of silicon was added to aluminum metal by the method of the present invention, the ratio was 13.
【００２０】この結果から明かなように本発明の製造法
を用いて作成した薄膜トランジスタアレイはゲート・ソ
ース短絡の欠陥を従来より１／５ないし１／７に低減す
ることが出来た。この欠陥低減は主にアルミニウム系下
層配線およびゲート電極パターンに発生する熱によるヒ
ロックを、本発明による製造方法によって低減したため
である。またゲート絶縁体層が３層で従来よりも多い多
層膜からなっていることも、多層の積層効果に基づいて
絶縁体層のピンホールや欠陥の低減に寄与していると考
えられる。As is clear from these results, the thin film transistor array produced by the manufacturing method of the present invention can reduce the defects of gate-source short circuit to 1/5 to 1/7 of the conventional one. This reduction in defects is mainly because hillocks due to heat generated in the aluminum-based lower layer wiring and the gate electrode pattern are reduced by the manufacturing method according to the present invention. It is also considered that the fact that the gate insulator layer is composed of three layers and is composed of more multilayer films than in the past contributes to the reduction of pinholes and defects in the insulator layer based on the multilayer stacking effect.
【００２１】（実施例２）実施例１とほとんど同様に薄
膜トランジスタを作成し比較した。ただし、実施例１の
場合とは異なり、アルミニウム金属の上にＴａ金属を１
００ｎｍの厚さに積層した。下層配線とゲート電極パタ
ーンをドライエッチング法で形成した後、Ｔａ金属全部
と、更にアルミニウム表面まで陽極酸化して、アルミニ
ウム下層配線とゲート電極の上に１００ｎｍの厚さの酸
化アルミニウム陽極酸化膜と２５０ｎｍの酸化タンタル
陽極酸化膜を積層した。１００ｎｍのＴａ金属は２５０
ｎｍの酸化タンタルに陽極酸化によって変換される。Example 2 A thin film transistor was prepared and compared in almost the same manner as in Example 1. However, unlike the case of Example 1, 1 Ta metal is deposited on the aluminum metal.
Laminated to a thickness of 00 nm. After forming the lower layer wiring and the gate electrode pattern by the dry etching method, anodizing up to the entire surface of the Ta metal and the aluminum surface to form an aluminum oxide anodic oxide film having a thickness of 100 nm and 250 nm on the aluminum lower layer wiring and the gate electrode. The tantalum oxide anodic oxide film of was laminated. 100 nm Ta metal is 250
converted to nm nm tantalum oxide by anodic oxidation.
【００２２】さらに実施例１と同じプラズマＣＶＤ法で
窒化シリコン膜を５０ｎｍを積層して、全体として実施
例１と同じ厚さ４００ｎｍのゲート絶縁体層を形成し
た。以下、実施例１と同様にして薄膜トランジスタアレ
イを完成し、実施例１と同じ従来の薄膜トランジスタア
レイと比較した。Further, a silicon nitride film having a thickness of 50 nm was laminated by the same plasma CVD method as in Example 1 to form a gate insulator layer having a thickness of 400 nm as in Example 1 as a whole. Hereinafter, a thin film transistor array was completed in the same manner as in Example 1 and compared with the same conventional thin film transistor array as in Example 1.
【００２３】その結果、ゲート・ソース短絡の割合は従
来１００に対して１０の割合であった。実施例１のＴａ
金属の厚さが３０ｎｍの場合より、その厚さが１００ｎ
ｍの実施例２の方がゲート・ソース短絡に対して効果的
であるが、一般によく設計され用いられるゲート絶縁体
層の厚さ４００ｎｍにたいして、半導体層に接する窒化
シリコンの膜厚は、少なくとも５０ｎｍは必要であるの
でＴａの膜厚は１００ｎｍ以下にした方がよい。As a result, the ratio of gate-source short circuit was 10 compared to 100 in the prior art. Ta of Example 1
Compared to the case where the metal thickness is 30 nm, the thickness is 100 n
Example 2 of m is more effective for gate-source short circuit, but the thickness of the silicon nitride in contact with the semiconductor layer is at least 50 nm in comparison with the thickness of 400 nm of the gate insulator layer which is generally well designed and used. Therefore, the film thickness of Ta is preferably 100 nm or less.
【００２４】（実施例３）実施例１とほとんど同じ方法
でＴａ金属を他の陽極酸化可能なＴｉ、Ｚｒ、Ｎｂ、
Ｗ、およびＭｏに置き換えて、薄膜トランジスタアレイ
を作成した。それらの金属の膜厚をすべて５０ｎｍと
し、陽極酸化して１００ｎｍの酸化チタン、１００ｎｍ
の酸化ジルコニウム、１２５ｎｍの酸化ニオブ、１５０
ｎｍの酸化タングステンおよび酸化モリブデンに変換し
た。前もって５０ｎｍの上記金属をアルミニウム金属に
積層することによって、アルミニウム金属の熱によるヒ
ロック発生がＴａ同様に抑えられることを確認してい
る。(Embodiment 3) Ti, Zr, Nb, which can anodize Ta metal in the same manner as in Embodiment 1, is used.
A thin film transistor array was prepared by substituting W and Mo. The thickness of each of these metals is set to 50 nm and anodized to 100 nm titanium oxide, 100 nm
Zirconium oxide, 125 nm niobium oxide, 150
nm tungsten oxide and molybdenum oxide. It has been confirmed in advance that hillock generation due to heat of aluminum metal can be suppressed in the same manner as Ta by laminating the above metal of 50 nm on aluminum metal.
【００２５】陽極酸化した後、酸化アルミニウム陽極酸
化膜１００ｎｍを含む３層からなるゲート絶縁体層の全
体の厚さが４００ｎｍになるように窒化シリコン膜を積
層し、以下、実施例１と同様に薄膜トランジスタを作成
して、実施例１と同じ従来例とゲート・ソース短絡の割
合を比較した。その結果、いずれにおいても従来１００
に対し３５以下の割合であった。After anodic oxidation, a silicon nitride film was laminated so that the total thickness of the gate insulator layer consisting of three layers including the aluminum oxide anodic oxide film of 100 nm was 400 nm, and thereafter, as in Example 1. A thin film transistor was prepared and the ratio of gate-source short circuit was compared with the same conventional example as in Example 1. As a result, the conventional 100
The ratio was 35 or less.
【００２６】[0026]
【発明の効果】以上説明したように、本発明の製造方法
によれば下層配線とゲート電極膜のヒロック発生を抑制
し、かつ３層積層膜からなるゲート絶縁体層を用いてい
るので、ゲート・ソース短絡欠陥を効果的に防止した薄
膜トランジスタを得ることができる。さらに一般に、本
発明の絶縁体薄膜を用いて、多層配線を有する半導体装
置の下層配線と上層配線の短絡を防止し、歩留まりの高
い信頼性に優れた半導体装置を製造できる。As described above, according to the manufacturing method of the present invention, the generation of hillocks in the lower wiring and the gate electrode film is suppressed, and the gate insulator layer composed of the three-layer laminated film is used. It is possible to obtain a thin film transistor that effectively prevents a source short circuit defect. Further, generally, by using the insulating thin film of the present invention, it is possible to prevent a short circuit between a lower layer wiring and an upper layer wiring of a semiconductor device having a multilayer wiring, and manufacture a semiconductor device having a high yield and excellent reliability.
【図１】本発明における逆スタガ型の薄膜トランジスタ
の製造工程を示す断面図FIG. 1 is a sectional view showing a manufacturing process of an inverted stagger type thin film transistor according to the present invention.
１ 基板ガラス ２ アルミニウムゲート電極薄膜 ３ タンタル金属薄膜 ４ 酸化タンタル陽極酸化膜 ５ 酸化アルミニウム陽極酸化膜 ６ 窒化シリコン薄膜 ７ アモルファスシリコン半導体薄膜 ８ エッチングストッパー窒化シリコン薄膜 ９ ｎ+アモルファスシリコン半導体薄膜 １０ チタンソース電極 １１ チタンドレーン電極 １２ ＩＴＯ透明電極1 Substrate glass 2 Aluminum gate electrode thin film 3 Tantalum metal thin film 4 Tantalum oxide anodized film 5 Aluminum oxide anodized film 6 Silicon nitride thin film 7 Amorphous silicon semiconductor thin film 8 Etching stopper silicon nitride thin film 9 n + Amorphous silicon semiconductor thin film 10 Titanium source electrode 11 Titanium drain electrode 12 ITO transparent electrode
Claims (4)
被着形成した第一の導電層と、前記基板表面の露出面及
び前記第一の導電層を覆う絶縁体層と、前記絶縁体層上
の特定領域を覆う半導体層と、前記半導体層と一部重な
り合う一対の第二の導電層と、前記第二の一対の導電層
の一方と電気的に接触する透明導電層から少なくともな
る薄膜トランジスタの製造において、まずアルミニウム
系の金属薄膜とその上にアルミニウム系以外の陽極酸化
可能な金属薄膜を積層した２層膜を形成し、陽極酸化可
能な金属薄膜の全部とアルミニウム系薄膜の一部を陽極
酸化して、前記第一の導電層と前記絶縁体層の一部を形
成することを特徴とする薄膜トランジスタの製造方法。1. A first conductive layer in which a conductive material is selectively deposited on a translucent insulating substrate, and an insulating layer covering the exposed surface of the substrate surface and the first conductive layer. From a semiconductor layer that covers a specific region on the insulator layer, a pair of second conductive layers that partially overlap with the semiconductor layer, and a transparent conductive layer that electrically contacts one of the second pair of conductive layers In the manufacture of at least a thin film transistor, first, a two-layer film is formed by laminating an aluminum-based metal thin film and an anodizable metal thin film other than an aluminum-based thin film, and the entire anodizable metal thin film and the aluminum-based thin film are formed. A method of manufacturing a thin film transistor, characterized in that a part of the first conductive layer and the insulator layer is formed by anodizing a part of the first conductive layer and the insulator layer.
ｒ、Ｎｂ、Ｗ、およびＭｏから選ばれた１種であること
を特徴とする請求項１記載の薄膜トランジスタの製造方
法。2. A metal thin film capable of being anodized is Ta, Ti, Z.
The method of manufacturing a thin film transistor according to claim 1, wherein the method is one kind selected from r, Nb, W, and Mo.
少量のＳｉを含んだＡｌのいずれかであることを特徴と
する請求項１記載の薄膜トランジスタの製造方法。3. An aluminum-based metal thin film is pure Al,
2. The method of manufacturing a thin film transistor according to claim 1, wherein the thin film transistor is any one of Al containing a small amount of Si.
００ｎｍであることを特徴とする請求項１記載の薄膜ト
ランジスタの製造方法。4. The thickness of the anodizable metal thin film is 30 to 1.
It is 00 nm, The manufacturing method of the thin-film transistor of Claim 1 characterized by the above-mentioned.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4335720A JPH06188419A (en) | 1992-12-16 | 1992-12-16 | Manufacture of thin-film transistor |
| US08/099,460 US5334544A (en) | 1992-12-16 | 1993-07-30 | Method of making thin film transistors |
| EP93112304A EP0602315A3 (en) | 1992-12-16 | 1993-07-31 | Method of making thin film transistors. |
| KR93027534A KR970004449B1 (en) | 1992-12-16 | 1993-12-14 | Method of making thin film transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4335720A JPH06188419A (en) | 1992-12-16 | 1992-12-16 | Manufacture of thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06188419A true JPH06188419A (en) | 1994-07-08 |
Family
ID=18291718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4335720A Pending JPH06188419A (en) | 1992-12-16 | 1992-12-16 | Manufacture of thin-film transistor |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5334544A (en) |
| EP (1) | EP0602315A3 (en) |
| JP (1) | JPH06188419A (en) |
| KR (1) | KR970004449B1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5811318A (en) * | 1995-12-28 | 1998-09-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| US6008065A (en) * | 1995-11-21 | 1999-12-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| KR100524873B1 (en) * | 1998-04-02 | 2005-12-30 | 엘지.필립스 엘시디 주식회사 | LCD and its manufacturing method |
| JP2016522570A (en) * | 2013-04-28 | 2016-07-28 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Diffusion prevention layer, manufacturing method thereof, thin film transistor, array substrate, and display device |
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|---|---|---|---|---|
| TW425637B (en) * | 1993-01-18 | 2001-03-11 | Semiconductor Energy Lab | Method of fabricating mis semiconductor device |
| KR970004885B1 (en) * | 1993-05-12 | 1997-04-08 | 삼성전자 주식회사 | Flat display device and its making method |
| JP3105409B2 (en) * | 1994-10-24 | 2000-10-30 | シャープ株式会社 | Metal wiring board, semiconductor device, and manufacturing method thereof |
| KR0163526B1 (en) * | 1995-05-17 | 1999-02-01 | 김광호 | Semiconductor device fabrication method involving formation step of protection layer on a contact pad by irradiate ultraviolet rays/ozone |
| GB2338105B (en) * | 1997-03-04 | 2000-04-12 | Lg Electronics Inc | Method of making a thin film transistor |
| KR100248123B1 (en) | 1997-03-04 | 2000-03-15 | 구본준 | Thin-film transistor and method for manufacturing thereof |
| US5943559A (en) * | 1997-06-23 | 1999-08-24 | Nec Corporation | Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process |
| US6333518B1 (en) | 1997-08-26 | 2001-12-25 | Lg Electronics Inc. | Thin-film transistor and method of making same |
| TWI226470B (en) * | 1998-01-19 | 2005-01-11 | Hitachi Ltd | LCD device |
| JP3980156B2 (en) * | 1998-02-26 | 2007-09-26 | 株式会社半導体エネルギー研究所 | Active matrix display device |
| US6297538B1 (en) | 1998-03-23 | 2001-10-02 | The University Of Delaware | Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate |
| JP3403949B2 (en) * | 1998-09-03 | 2003-05-06 | シャープ株式会社 | Thin film transistor, liquid crystal display device, and method of manufacturing thin film transistor |
| KR100726132B1 (en) * | 2000-10-31 | 2007-06-12 | 엘지.필립스 엘시디 주식회사 | A method for fabricating array substrate for liquid crystal display device and the same |
| US20060003485A1 (en) * | 2004-06-30 | 2006-01-05 | Hoffman Randy L | Devices and methods of making the same |
| US20060088962A1 (en) * | 2004-10-22 | 2006-04-27 | Herman Gregory S | Method of forming a solution processed transistor having a multilayer dielectric |
| US7768080B2 (en) * | 2007-07-30 | 2010-08-03 | Hewlett-Packard Development Company, L.P. | Multilayer dielectric |
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| CN102386237A (en) * | 2011-11-23 | 2012-03-21 | 深圳市华星光电技术有限公司 | Thin-film transistor, array substrate and device and preparation method |
| US9368360B2 (en) * | 2013-04-28 | 2016-06-14 | Boe Technology Group Co., Ltd | Anti-diffusion layer, preparation method thereof, thin-film transistor (TFT), array substrate, display device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58100461A (en) * | 1981-12-10 | 1983-06-15 | Japan Electronic Ind Dev Assoc<Jeida> | Manufacture of thin-film transistor |
| JPS58147069A (en) * | 1982-02-25 | 1983-09-01 | Sharp Corp | Thin film transistor |
| JPH061314B2 (en) * | 1987-07-30 | 1994-01-05 | シャープ株式会社 | Thin film transistor array |
| JP2786628B2 (en) * | 1987-10-15 | 1998-08-13 | シャープ株式会社 | Liquid crystal panel electrode structure |
| JPH01217325A (en) * | 1988-02-25 | 1989-08-30 | Sharp Corp | Liquid crystal display device |
| JPH0814669B2 (en) * | 1988-04-20 | 1996-02-14 | シャープ株式会社 | Matrix type display device |
| JPH03227068A (en) * | 1990-02-01 | 1991-10-08 | Casio Comput Co Ltd | Thin film transistor and manufacture thereof |
| JPH03248568A (en) * | 1990-02-27 | 1991-11-06 | Fuji Xerox Co Ltd | Thin-film semiconductor device |
| JP2940689B2 (en) * | 1990-03-23 | 1999-08-25 | 三洋電機株式会社 | Thin film transistor array of active matrix display device and method of manufacturing the same |
| JPH03283540A (en) * | 1990-03-30 | 1991-12-13 | Oki Electric Ind Co Ltd | Manufacture of thin film transistor |
| US5126283A (en) * | 1990-05-21 | 1992-06-30 | Motorola, Inc. | Process for the selective encapsulation of an electrically conductive structure in a semiconductor device |
-
1992
- 1992-12-16 JP JP4335720A patent/JPH06188419A/en active Pending
-
1993
- 1993-07-30 US US08/099,460 patent/US5334544A/en not_active Expired - Fee Related
- 1993-07-31 EP EP93112304A patent/EP0602315A3/en not_active Withdrawn
- 1993-12-14 KR KR93027534A patent/KR970004449B1/en not_active IP Right Cessation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6008065A (en) * | 1995-11-21 | 1999-12-28 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| US6331443B1 (en) | 1995-11-21 | 2001-12-18 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| US6661026B2 (en) | 1995-11-21 | 2003-12-09 | Samsung Electronics Co., Ltd. | Thin film transistor substrate |
| USRE41363E1 (en) * | 1995-11-21 | 2010-06-01 | Samsung Electronics Co., Ltd. | Thin film transistor substrate |
| US5811318A (en) * | 1995-12-28 | 1998-09-22 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| USRE39211E1 (en) | 1995-12-28 | 2006-08-01 | Samsung Electronics Co., Ltd. | Method for manufacturing a liquid crystal display |
| KR100524873B1 (en) * | 1998-04-02 | 2005-12-30 | 엘지.필립스 엘시디 주식회사 | LCD and its manufacturing method |
| JP2016522570A (en) * | 2013-04-28 | 2016-07-28 | 京東方科技集團股▲ふん▼有限公司Ｂｏｅ Ｔｅｃｈｎｏｌｏｇｙ Ｇｒｏｕｐ Ｃｏ．，Ｌｔｄ． | Diffusion prevention layer, manufacturing method thereof, thin film transistor, array substrate, and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0602315A2 (en) | 1994-06-22 |
| EP0602315A3 (en) | 1997-02-19 |
| KR970004449B1 (en) | 1997-03-27 |
| US5334544A (en) | 1994-08-02 |
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