JPH11167128A - Production of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation in an aperture ratio without increasing the exclusive area rate of additive capacitors even if the additive capacitors are increased by using a material contg. an oxide of a metal consisting essentially of Ta as a dielectric film of the superposed parts constituting the additive capacitors. SOLUTION: An SiO2 ground surface film 20 for protection of a translucent glass substrate 14 is formed on this glass substrate. Next, the metal Ta is deposited and is etched to form desired gate wiring patterns 22, 23. The difference in level at the ends of the Ta patterns is provided with a taper. The Ta gate wiring patterns 22, 23 are anodically oxidized to form an anodically oxidized Ta film 24. Next, an SiN gate insulating film 21, an a-SiH(i) film 8 and an SiN channel protective film 25 are continuously deposited and is etched, by which island-shaped patterns of the SiN channel protective film 25 are formed. Next, the island-shaped patterns of a-Si:H(n-) 15 and a-Si: H(i) 8 are formed. Signal line patterns 1 and source electrode patterns 5 are formed. Finally, a protective film 12 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a method of manufacturing a liquid crystal display device having a structure capable of increasing an additional capacitance without lowering an aperture ratio of a pixel.

[0002]

2. Description of the Related Art The prior art relating to providing an additional capacitor between a pixel corresponding to a certain gate line and a gate line of the next stage is disclosed in JP-A-59-119329 and JP-A-60-8.
No. 7393, JP-A-62-152157, and the like.

FIG. 2 is a view showing one pixel of an active matrix liquid crystal display panel having an additional capacitor according to the prior art, wherein (a) is a plan view, (b) is a cross-sectional view, and (c) is equivalent. It is a circuit diagram. A thin film transistor (hereinafter abbreviated as TFT) 4 for selecting one pixel is shown in FIG.
As shown in (b), the gate line 2, the gate insulating film 11,
a-Si: H (i), a-Si: H (n ⁺ ) layer 15, signal line 1, source electrode 5, pixel electrode 9. The additional capacitance (7 in FIG. 2C) is formed by overlapping the pixel electrode 9 and the next-stage gate line 3 as shown in FIG. 2A. As shown in FIG. 2B, the same material as the gate insulating film 11 is used for the dielectric layer as it is. here,
Reference numeral 13 denotes a low-resistance metal wiring for reducing gate wiring resistance, and reference numeral 12 denotes a protective film.

The purpose of providing the additional capacitance 7 will be outlined below. Since the TFT has a parasitic capacitance (6 in FIG. 2A) due to the overlapping portion of the gate line and the source electrode 5, the scanning pulse of the gate line 2 leaks through the parasitic capacitance 6 and the pixel electrode 9 Is varied. This leakage voltage component usually has a form in which a DC component is added to the pixel potential since the duty ratio of the scanning pulse is (1 / number of gate lines) and the pulse is asymmetric in the positive and negative directions. This DC component degrades the image sticking and afterimage characteristics of the liquid crystal panel.

When the OFF resistance of the TFT decreases or the specific resistance of the liquid crystal decreases, the pixel capacitance formed by the pixel electrode 9 and the counter electrode 17 via the liquid crystal (FIG. 2C) If (16) is not sufficiently large, there arises a problem that the pixel potential Vs once written via the TFT 4 cannot be held within the period until the next writing. This causes image defects such as black spots, white spots, and black spots on the liquid crystal panel. At this time, the additional capacity 7
Has the effect of increasing the pixel capacitance 16, so that the above-mentioned defects in image quality are less likely to occur.

As described above, providing an additional capacitor is an effective method for improving the image quality of an active matrix liquid crystal panel in which pixels are selected by using TFTs.

In addition to the additional capacitance, a gate line as shown in FIG. 2 is used as one electrode of the additional capacitance, and another additional capacitance is provided separately from the gate line as shown in Japanese Patent Application Laid-Open No. 62-148929. Some of them have the same function in terms of holding the signal voltage of the pixel electrode.

[0008]

In the above prior art, as shown in FIG. 2B, TF is used as a dielectric film of an additional capacitor.
The same material as that of the T gate insulating film 11 is used. a
When using a -Si TFT, SiN is usually used as a gate insulating film. The thickness of the SiN gate insulating film is 0.32
μm approximately, when the relative dielectric constant is 6.9, the area occupied by the additional capacitor becomes 5000μm ² / 1pF. For example, if the pixel area is 200 × 250 μm ² , the additional capacitance of 1 pF occupies 10% of the area of one pixel. However, in order to accelerate the response characteristics of the liquid crystal cell and improve the viewing angle characteristics, it is necessary to reduce the gap interval between the liquid crystal cells as much as possible, and accordingly, it is necessary to increase the additional capacitance. I got the knowledge. As a result of various studies by the present inventors, it has been found that the required additional capacitance is about 2 pF to 3 pF at a gap interval of about 5 μm, for example. In this case, the occupation ratio of the additional capacitance in one pixel reaches 20% to 30%, so that it becomes difficult to absorb the additional capacitance in the black matrix region in one pixel. Here, the black matrix portion refers to a light-shielded area outside the red, green, and blue color filter patterns provided on the counter electrode substrate side corresponding to the ITO (Indium Tin Oxide) pixel electrodes in a one-to-one correspondence. . Usually, an additional capacitor having an occupied area of about 10% in one pixel is arranged so as to be contained in this black matrix area.
Although it is possible not to lower the aperture ratio,
When the area occupied by the additional capacitance is 20 to 30%, it is difficult to arrange the additional capacitance without lowering the aperture ratio per pixel.

It is an object of the present invention to provide a liquid crystal display panel which does not increase the occupied area ratio even when the size of the additional capacitance is increased, and therefore does not cause a decrease in the aperture ratio.

A known example in which an anodic oxide film of one electrode of an additional capacitor is used as a dielectric film of the additional capacitor is disclosed in Japanese Patent Application Laid-Open No. 58-1983.
There is 93092 gazette (prior art 1). However, the prior art 1 does not disclose a configuration of the present invention in which the dielectric film of the additional capacitor is formed of a composite film of a tantalum oxide film and a silicon nitride film.

Japanese Patent Application Laid-Open No. 1-217325 (Prior Art 2) discloses a prior application in which a dielectric film of an additional capacitor is formed of a composite film of a tantalum oxide film and a silicon nitride film.
And JP-A-1-267618 (prior art 3). However, neither the prior art 2 nor the prior art 3 describes a configuration of the present invention in which anodization is performed after tapering the step at the end of the tantalum wiring.

Therefore, in the techniques disclosed in the prior arts 2 and 3, there is no recognition that the signal line is disconnected when the signal line is formed thereon after the surface of the tantalum wiring is anodized. There has been a problem that the signal electrode and the source and drain electrodes are easily disconnected due to the step formed by the anodic oxide film of the wiring.

[0013]

The above object is achieved by using a material containing at least a metal oxide containing Ta as a main component as a dielectric film of an overlapped portion constituting the additional capacitance.

That is, a step of depositing a tantalum film on a translucent substrate, a step of etching the tantalum film to form a pattern of a plurality of tantalum wirings, and tapering a step at an end of the tantalum wiring pattern. Anodizing the tantalum wiring to form a tantalum oxide film having a thickness of 800 ° to 3200 ° on the surface of the tantalum wiring;
Depositing a gate insulating film made of silicon nitride, an i-type amorphous silicon film and a channel protective film made of silicon nitride, forming a pattern of the channel protective film, and forming an n ⁺ type amorphous silicon film. Depositing, patterning the n ⁺ -type amorphous silicon film and i-type amorphous silicon film, and forming a signal line pattern and a source electrode pattern that intersect the tantalum wiring with a metal film;
A method of manufacturing a liquid crystal display device, comprising: forming a pixel electrode with a transparent electrode so as to overlap a pixel electrode with an adjacent tantalum wiring.

The tantalum film is etched by C
A method for manufacturing a liquid crystal display device, wherein the method is performed by a dry etching method using a -Cl-F-based gas.

Further, in the step of forming the tantalum oxide film, anodizing is performed after performing a formation photoresist step on the tantalum wiring pattern.
It is a manufacturing method of the liquid crystal display device described.

Further, in the step of depositing a tantalum film on the translucent substrate, a tantalum film is deposited after depositing a base film for protecting glass on the glass substrate. This is a method for manufacturing a liquid crystal display device.

As a more specific example, FIGS.
This can be achieved by installing an additional capacitor as shown in FIG. 4, FIG. 8, FIG. 9 or FIG.

That is, as is apparent from the cross-sectional view of FIG. 2B, the additional capacitance of the conventional example shown by 7 in FIG. 2A is equivalent to that of Si which is the gate insulating film of the a-Si TFT as the dielectric film. Although the nitride or oxide 11 is used, an oxide of a Ta-based metal having a larger relative dielectric constant is used as a main dielectric film in the additional capacitance of the present invention. As the Ta-based metal oxide, metal T as a gate electrode and gate wiring material is used.
a, and a Ta ₂ O ₅ film obtained by anodizing this can be used.

In the embodiment shown in FIG. 1, the additional capacitance is constituted by Ta gate wiring 23 / oxide of Ta (Ta ₂ O ₅ ) 24 / pixel electrode 9. In the embodiment shown in FIG. 3, the additional capacitance is an oxide (Ta) of the Ta gate line 23 / Ta.
₂ O ₅ ) 24 / metal electrode 2 electrically connected to pixel electrode
6. In the embodiment shown in FIG. 4, the additional capacitance is an oxide of Ta gate line 23 / Ta (Ta ₂ O).
₅ ) 24 / Very thin Si nitride or oxide 21 /
It is composed of a pixel electrode 9.

The relative permittivity of the oxide of Ta (Ta ₂ O ₅ ) is about 26, and the relative permittivity of the SiN film is 3.9 or 3.8.
Twice as _{high as} the relative dielectric constant of 4.2 of the SiO ₂ film.

In a liquid crystal display panel with an additional capacitor, a SiN film formed by a plasma CVD method having a relatively large dielectric constant is used as a gate insulating film of an a-Si TFT for selecting a pixel. Is also used as an additional capacitance portion to obtain an additional capacitance of 3 pF with a thickness of 0.32 μm in order to obtain 1500 μm ² (200 × 250 μm ² per pixel).
Occupied area of 30%). Here, if the dielectric film is replaced with a Ta ₂ O ₅ film having the same thickness, the area occupied by the additional capacitance can be reduced to 1 / 3.8.
At this time, since the additional capacitance of 3 pF is 10% or less of the area of one pixel, the additional capacitance pattern can be arranged so as to be absorbed in the black matrix region in one pixel. Therefore, it is possible to prevent a decrease in the brightness of the liquid crystal display panel due to a decrease in the aperture ratio of one pixel.

The above-mentioned Ta ₂ O ₅ film is usually obtained by using metal Ta as a gate electrode and anodizing it. The anodic oxidation voltage and the thickness of the formed Ta ₂ O ₅ anodic oxide film have a linear relationship as shown in FIG. Ta ₂
The O ₅ anodic oxide film is a film having excellent withstand voltage and insulating properties. This is because the anodic oxidation reaction proceeds selectively from the electrically leaky portion of the Ta ₂ O ₅ film (called a self-healing effect). Therefore, the Ta ₂ O ₅ anodic oxide film can be used not only at the additional capacitance portion but also at the intersection of the gate wiring and the signal line and the gate insulating film portion of the TFT, which is preferable. As a result, it is possible to greatly reduce an electrical short circuit between the gate wiring and the signal line and an electrical short circuit between the gate electrode and the source / drain electrodes.

Further, when only an anodized Ta ₂ O ₅ film is used as a gate insulating film of an a-Si TFT and an a-Si: H (i) layer is directly deposited on Ta ₂ O ₅ , the effective TFT can be formed. Mobility is greatly reduced. Therefore, as a gate insulating film of an a-Si TFT, a second layer of a gate insulating film made of a SiN film deposited by a plasma CVD method is stacked on a first layer of a Ta ₂ O ₅ gate insulating film. It is desirable to use a layer film.

Also, at the intersection of the gate wiring and the signal line, a Ta ₂ O ₅ / SiN bilayer film is formed to reduce the capacitance between the gate line and the signal line and to reduce the short-circuit rate between the lines. It is desirable to use.

The thickness of the Ta ₂ O ₅ anodic oxide film is 32
When the thickness is more than 00 °, the film thickness together with the gate wiring, which is usually formed to a thickness of about 1800 to 2000 °, is 5000 °.
Since the probability of disconnection of the step at the crossing portion of the signal line at the gate line / signal line crossing portion increases, Ta
The thickness of ₂ O ₅ is desirably 3200 ° or less.

Further, by tapering the step at the end of the gate wiring made of Ta, the probability of the step breakage at the crossing portion of the signal line at the intersection of the gate line and the signal line is more desirably reduced.

The Ta ₂ O ₅ film in the additional capacitance portion is 80
When the thickness is less than 0 °, the leak current increases, and the insulating property deteriorates. This thin Ta ₂ O ₅ film is made of SiN or Si
Leakage current can be suppressed by forming a two-layer structure with the O ₂ film. However, reliability deteriorates in terms of long-term life as an additional capacity. Therefore, the thickness of the Ta ₂ O ₅ film is 80
Desirably, it is 0 ° or more.

By setting the optimum film thickness condition as described below in the additional capacitance portion, Ta ₂ O ₅ /
A two-layer structure of SiN or Ta ₂ O ₅ / SiO ₂ can be performed. FIG. 6 shows that the dielectric film of the additional capacitance portion is made of Ta _2.
O ₅ / SiN composite film (a) and Ta ₂ O ₅ / SiO ₂
It is a figure showing the combination of the film thickness when using the composite film (b). In FIGS. 6A and 6B, as described above, Ta
It is desirable that the thickness of ₂ O ₅ be selected in the range of 800 ° to 3200 °. When the area is constant, the line segment a ₁ -b ₁ is ₁ pF, the line segment a ₂ -b ₂ is ₂ pF, and min a ₃ -b ₃ corresponds to the thickness of the composite film when installed the additional capacity of 3 pF.

The ₁ pF line segment a ₁ − in FIGS. 6 (a) and 6 (b)
While left area than b ₁ is a region where the capacitance per unit area than the additional capacitance formed by the conventional SiN film increases,
The combination of film thickness included in the area indicated by hatching on the left side of the line a ₂ -b ₂ of 2pF if the value of more than 2pF is needed as additional capacity is particularly effective.

From FIG. 6, it is particularly effective that the thickness of the SiN film is 1000 ° in the Ta ₂ O ₅ / SiN composite film (a), and that the thickness in the Ta ₂ O ₅ / SiO ₂ composite film (b) is S.
It is particularly effective that the iO ₂ film thickness is 600 ° or less.

In addition, the etching of the tantalum film is performed by a C-C
The use of a dry etching method using an l-F gas is particularly effective because the step at the end of the tantalum wiring can be easily tapered.

Further, a tantalum oxide film can be selectively formed on the tantalum wiring by subjecting the tantalum wiring pattern to a formation photoresist step and then performing anodic oxidation.

After depositing a base film for protecting glass on the glass substrate, depositing a tantalum film, and etching the tantalum film with a taper, the surface of the glass substrate is protected in the tantalum film etching step. You.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to embodiments.

Embodiment 1 Example 1 will be described with reference to FIG. Si for protecting the glass substrate on the translucent glass substrate 14
An O ₂ underlayer 20 is deposited to a thickness of about 3000 °. Next, metal Ta was sputtered to a thickness of 3000
And a desired gate wiring pattern is formed by photoetching. In order to taper the step at the end of the Ta pattern, a dry etching method using a C-Cl-F-based gas is used for the etching. Next, a substrate whose portions other than the portion to be subjected to anodization were coated with photoresist was 0.1% H _3.
When immersed in an aqueous solution of PO ₄ and anodized at an anodizing voltage (combination voltage) of 180 V using a platinum electrode as a cathode and a Ta gate wiring pattern as an anode, about 3000 ° C. is applied to completely cover the Ta gate wiring. A thick Ta anodic oxide film (Ta ₂ O ₅ ) is formed. That is, in FIG.
The a ₂ O ₅ film 24 is a Ta gate electrode 22 of an a-Si TFT.
Above, it becomes the gate insulating film of the first layer of the TFT, and on the adjacent Ta gate wiring 23, it becomes the dielectric film of the additional capacitance.
The formation voltage and the thickness of the formed Ta ₂ O ₅ film have a linear relationship as shown in FIG. 7, and the gradient is 16.5 ° / V.
Therefore, at a formation voltage of 180 V, Ta ₂ O ₅ having a thickness of 3000 ° is obtained from FIG. Anodizing is 0.5m at first
When the constant current formation is performed at a constant current density of A / cm ² and the formation voltage is set to 180 V (= constant) for 30 minutes from the time when the formation voltage reaches 180 V, highly reliable Ta ₂ O _{5 is obtained.}
A film is obtained. In order to form Ta ₂ O ₅ having a thickness of 3000 °, Ta having a thickness of about ３ of the Ta ₂ O ₅ is consumed. Therefore, the Ta gate electrode 22 and the additional capacitance portion 23 of the adjacent Ta gate wiring are formed. The remaining Ta film thickness is about 2000 °.

Next, an ITO (Indium Tin Oxide) transparent electrode is deposited to a thickness of 1200 ° by a sputtering method, and a pixel electrode pattern 9 is formed by a photo-etching method using an aqueous solution of HCl. At this time, the pixel electrode 9 is patterned so as to overlap with the adjacent Ta gate wiring 23. The area of the superposed portion was 170 × 25 μm ² , and the additional capacitance was 3 pF. Here, the width of 25 μm of the additional capacitance is easily absorbed in the 250 μm (V) × 200 μm (H) black matrix region of one pixel, and does not cause a decrease in the aperture ratio of one pixel.

Next, the SiN gate insulating film (second layer gate insulating film) 21, a-SiH
(I) The film 8 and the SiN channel protective film 25 are each 3
It is continuously deposited to a thickness of 2,000, 250, and 2000 degrees. Next, the SiN channel protective film 25 is formed by a photo-etching method using an HF-NH ₄ F-based etchant.
Is formed.

Next, a-Si:
H (n ⁺ ) is deposited to a thickness of 400 °.

Next, a-Si: H (n ⁺ ) 15 and a
-Si: H (i) An eight island pattern is formed. At this time,
The photoresist pattern is a-Si: H (n ⁺ ), using a pattern divided into two parts, a source part and a drain part.
(I) When the island pattern is formed, the a-Si: H (n ⁺ ) film on the SiN channel protective film 25 is separated between the source and the drain, and the SiN channel protective film pattern 25 is formed.
In the a-Si: H (i) film below, the SiN channel protective film is left as an etching stopper.

Next, SiN which is a second-layer gate insulating film is used.
On the gate insulating film 21, the ITO pixel electrode 9 and the source electrode 5
Is formed by a photo-etching method.

Next, metal Al is deposited to a thickness of 3000.degree., And a signal line pattern 1 and a source electrode pattern 5 are formed by photoetching.

Finally, a protective film 12 is formed so as to cover the entire screen area of the TFT substrate, and a TFT substrate for a liquid crystal display panel is completed. A liquid crystal display panel is completed by combining this TFT substrate with a normal counter substrate, liquid crystal, and the like.

Embodiment 2 FIG. A second embodiment will be described with reference to FIG. a-Si: H (n ⁺ ) 15 and a-Si: H
(I) Fabrication is performed in the same manner as in Example 1 up to the eight island patterning step. However, Ta deposited by the sputtering method
The film thickness of 2700 ° is used, the formation voltage is 120 V, and the thickness of the formed Ta ₂ O ₅ is 2000 ° from FIG.
And the remaining thickness of the Ta gate line after formation is about 2,000 mm.
It has become. Further, the pixel electrode pattern 9 made of the ITO transparent electrode does not overlap with the adjacent gate line 23. As in the first embodiment, the SiN
Gate insulating film (second layer gate insulating film) 21, a-S
i: H (i) 8 and SiN channel protective film 25 are successively deposited to a film thickness of 2000, 200 and 1800, respectively.
A-Si: H (n ⁺ ) film formation by VD (thickness 300)
Å), a-Si: H (n ⁺ ) 15 and (i) 8-island pattern formation is performed by a source / drain two-division photoresist pattern.

Next, a Ta ₂ O ₅ dielectric film 2 for additional capacitance formed on the ITO pixel electrode 9 and the next-stage gate wiring 23 is formed on the SiN gate insulating film (second layer gate insulating film) 21.
Photoetching is performed so that 4 is exposed. At this time, as in the first embodiment, photoetching for extracting terminals is also performed at the same time.

Next, metal Al is deposited to a thickness of 3000.degree., And the signal line pattern 1, the source electrode pattern 5, and the upper electrode pattern 2 for the additional capacitance are formed by photoetching.
6 is formed. In the first embodiment, the additional capacitance is provided so that the ITO pixel electrode 9 and the next-stage gate wiring 23 directly form an overlapping portion via the Ta ₂ O ₅ 24.
The Al electrode 26 electrically connected to the TO pixel electrode 9 becomes an upper electrode for additional capacitance. The structure of the additional capacitance of this embodiment is different from the structure of the first embodiment using ITO in that Ta ₂ O _{5 is used.}
There is an advantage that disconnection hardly occurs at a step at the end of the dielectric pattern 24. However, since it is necessary to form a contact with the metal Al on the ITO pixel electrode 9, there is a slight problem that the aperture ratio is easily reduced. But T
By reducing the thickness of the a ₂ O ₅ anodic oxide film to 2000 °, the area of the superposed portion is 200 even with an additional capacitance of 3 pF.
It is possible to reduce the occupied area to × 14 μm ² .
Therefore, the overlap of the contact with the ITO pixel electrode 9 is 6 μm.
If the Al electrode pattern 26 of 200 × 25 μm ² is formed with the gap between the pixel electrode 9 and the gate wiring 23 set to 5 μm, the Al electrode pattern 26 can be accommodated in the black matrix area of one pixel, and the aperture ratio of one pixel is reduced. Never.

Finally, a protective film 12 is formed so as to cover the entire screen area of the TFT substrate, thereby completing a TFT substrate for a liquid crystal display panel.

Embodiment 3 FIG. Embodiment 3 will be described with reference to FIG. Using the same process as in Example 1, a T
a The process is performed up to the gate wiring patterning step.

Next, after performing a photoresist process for formation, constant current and constant voltage formation are performed at a formation voltage of 50V. The thickness of the formed Ta ₂ O ₅ is 800 ° from FIG.
Anodizing conditions are the same as those in Example 1, except that the formation voltage is set to 50V. The remaining film thickness of the Ta gate after the formation is about 2000 °.

Next, unlike the first and second embodiments, the SiN gate insulating film (the second-layer gate insulating film) 21, a is formed by the plasma CVD method without performing the ITO transparent electrode deposition and processing steps.
-Si: H (i) 8 and a SiN channel protective film 25 are successively deposited to a thickness of 600 °, 250 ° and 1500 °, respectively. Next, an island pattern of the SiN channel protective film 25 is formed using an HF-NH ₄ F-based etchant.

Next, a-Si:
An H (n ⁺ ) film is deposited to a thickness of 400 °.

Next, a-Si: H (n ⁺ ) 15 and a
-Si: H (i) 8 island-like patterns were formed in the same manner as in Example 1.
When the source / drain portion is formed using a photoresist pattern divided into two, the a-Si: H (n ⁺ ) film becomes
It is separated between the drain of the lower SiN channel protective film 25 a-Si: H (i ) film _a-Si 2: left when H (i) island pattern 8 is complete.

Next, the SiN gate insulating film is subjected to photoetching for taking out a terminal.
The iN gate insulating film is left.

Next, metal Al is deposited to a thickness of 2000.degree., And a signal line pattern 1 and a source electrode pattern 5 are formed by photoetching.

Next, an ITO transparent electrode is deposited to a thickness of 1200 ° by a sputtering method, and the pixel electrode pattern 9 and the Al signal line coating pattern electrode 5 are covered by a photo-etching method using an aqueous solution of HCl, and are adjacent to each other. Is patterned so as to overlap with the Ta gate wiring 23 to be formed. At this time, the superposed dielectric film is made of Ta _{2 having} a thickness of 800 °.
O ₅ film is a composite film of the SiN film 21 of 24 and a thickness of 600 Å. The area of the superposed portion is 170 × 25 μm ² and the additional capacitance is 3 pF. Here, the additional capacity width 2
5 μm is the size of one pixel 250 μm (H) × 200 μm
(H) is absorbed in the black matrix region, and does not cause a decrease in the aperture ratio of one pixel.

Since the ITO transparent electrode is deposited after the plasma CVD process, the ITO transparent electrode is exposed to reducing plasma during the deposition of the SiN gate insulating film 21 using a SiH ₄ —NH ₃ —N ₂ based source gas. The ITO is not reduced and deteriorated. The Al and Ta ₂ O ₅ film thicknesses of 2000 and 1000 mm, respectively, can be applied to the stepped edge of the ITO pixel electrode at the ends of the Al source electrode pattern 5 and the Ta ₂ O ₅ dielectric film pattern 24.
And 800 ° can be dealt with by the thin film.

At this time, when the thickness of the single-layer film of Ta ₂ O ₅ was less than 800 °, the insulating film was deteriorated. FIG.
Is a graph showing the voltage-current characteristics of the Ta ₂ O ₅ anodic oxide film having a thickness of 800 ° when the maximum voltage condition of 21 V applied to the additional capacitance is applied. , A leak current close to 10 ⁻¹¹ A at point C flowed. The composite film of Ta ₂ O ₅ (800 °) / SiN (600 °) has a voltage-current characteristic as shown by a curve b.
Even when 1 V was applied, the leakage current was sufficiently low at 5 × 10 ⁻¹⁴ A or less. However, a Ta ₂ O ₅ single layer film
It has been found that, in a film in which the leak current at the time of applying 1 V exceeds the point C (10 ⁻¹¹ A), even if a composite film is formed by superposing SiN or SiO ₂ , the reliability is slightly lowered in terms of long-term life.

Therefore, the thickness of the Ta ₂ O ₅ anodic oxide film is 80
0 ° or more, and from FIG.
V or more is preferable. On the other hand, it is necessary to set the additional capacitance of 3 pF because the aperture ratio is not reduced, and to prevent disconnection of the step at the signal line crossing the gate line.
It is desirable that the thickness of a ₂ O ₅ be 3200 ° or less.

Further, by tapering the step at the end of the gate wiring made of Ta, the probability of step breakage at the crossing portion of the signal line at the intersection of the gate line and the signal line is more desirably reduced.

[0060] Further, after the tapered stepped end of the Ta gate wiring, since the anodized surface of the Ta gate wiring forming the _{the Ta} 2 _{O 5} film, _Ta at the end of the Ta gate wiring 2 O _The stress is not concentrated on the _five films and no crack occurs, and the breakdown voltage between the Ta gate wiring and the signal line does not decrease.

FIG. 6 shows the case where the film thickness is 3000
The Ta ₂ O ₅ / SiN composite film (a) and Ta required to realize a capacity equal to the capacity of the Ta ₂ O ₅ single layer film of Å
FIG. 3 is a diagram showing combinations of thicknesses of a ₂ O ₅ / SiO ₂ composite film (b). For example, Ta ₂ O ₅ / SiN in FIG.
Considering the condition that the thickness of the Ta ₂ O ₅ film is 800 ° or more in the composite film, a point on the line segment a ₃ -b ₃ shown by a solid line is a preferable range as a combination of the film thicknesses of the composite film,
It can be seen that the range of the thickness of the SiN film is about 600 ° or less. Similarly, in the case of the Ta ₂ O ₅ / SiO ₂ composite film shown in FIG. 6B, the line segment a ₃ -b ₃ is a preferable range, and
The range of the thickness of the O ₂ film is about 350 ° or less.

Finally, a protective film 12 is formed so as to cover the entire screen area of the TFT substrate, thereby completing the TFT substrate for a liquid crystal display panel.

According to the embodiment shown in FIG. 4, since the dielectric film of the additional capacitance is formed of a multilayer film of the Ta ₂ O ₅ film and the SiN film, the Ta ₂ O ₅ film is made thin to temporarily increase the capacitance. Even if it is formed, since the SiN film suppresses the leak current, the leak current does not increase between the upper electrode and the lower electrode of the additional capacitor, and the signal voltage holding characteristics of the pixel electrode can be completely completed. I can do it.

Further, the metal film of the signal line is covered with a transparent electrode formed simultaneously with the pixel electrode to form a multi-layer structure, thereby preventing the signal line from being disconnected and reducing the resistance of the signal line with a simple structure. I can do it.

Therefore, according to the embodiment shown in FIG. 4, even if a liquid crystal display device having a large display screen is formed, the brightness of the screen does not differ on the side opposite to the power supply side of the signal line.

In particular, in a liquid crystal display device in which an additional capacitance is provided in a pixel electrode, power supply to the pixel electrode becomes more problematic as the capacitance of the additional capacitance is increased.

However, as in the present embodiment, the metal film of the signal line is covered with a transparent electrode to form a multilayer structure to reduce the resistance of the signal line. There is no problem that the power supply to the pixel electrode cannot be made in time on the side opposite to the power supply side.

In a liquid crystal display device having a structure in which a surface oxide film is provided by oxidizing the surface of a gate electrode and a gate line, the amount of deposition is increased by the amount of oxidation of the metal film. There is a possibility that a step formed at an end portion becomes severe and a signal line, a source, and a drain electrode formed on the step are disconnected.

However, as in the present embodiment, the signal line and the source and drain electrodes are covered with a transparent electrode to form a multi-layer structure. In addition, the drain electrode is not disconnected.

Embodiment 4 FIG. A fourth embodiment will be described with reference to FIG.

After coating the SiO ₂ underlayer 20 in the same manner as in the first embodiment, the Cr gate wiring patterns 32 and 33 are formed.
To form Next, the TaCl ₅ -O ₂ system material gas subjected to optical CVD as the substrate temperature of 400 ° C under a mercury lamp irradiation, allowed to deposited _{the Ta} 2 _{O 5} film 28 having a thickness of 800 Å. At this time, the Ta ₂ O ₅ film 28 may be deposited by a plasma CVD method using a TaCl ₅ —O ₂ source gas.

Next, steps subsequent to the step of successively forming the SiN gate insulating film 21, the a-Si: H (i) film 8, and the SiN channel protective film by the plasma CVD method are the same as those of the third embodiment. A TFT substrate for a liquid crystal display panel as shown in FIG. In the embodiment of FIG. 8, a metal other than Ta can be used for the gate wiring, and Ta ₂ O
_{Since the} film ₅ does not use the anodic oxide film of the Ta gate wiring, the entire screen of the liquid crystal display panel is Ta ₂ O ₅ 28 /
The SiN gate insulating film 21 has a two-layer structure.

Embodiment 5 FIG. A fifth embodiment will be described with reference to FIG.

A film thickness of 2000 was obtained in the same manner as in Example 4.
A Ta ₂ O ₅ CVD film 28 of Å is deposited, and then an a-Si: H (i) film 8 of 250） and a SiN channel protective film 25 of 2,000 Å are continuously deposited without breaking vacuum. I do.

Next, through the same steps as in the third embodiment, FIG.
TFT for liquid crystal display panel with cross section as shown in
Make a substrate.

In the TFT substrate as shown in FIG.
Although a-Si: H (i) 8 is directly deposited on a part of the gate insulating film 28 made of the Ta ₂ O ₅ CVD film, the Ta ₂ O ₅ CVD Since the a-Si: H (i) film is continuously subjected to plasma CVD without breaking the vacuum from the film, deterioration of the mobility of the a-Si: H (i) film can be controlled.

Embodiment 6 FIG. Embodiment 6 will be described with reference to FIG.

Using the same method as in the second embodiment,
The process is performed up to the step of forming a Ta ₂ O ₅ anodic oxide film 27 of 00 °.

Next, in the steps after the Ta ₂ O ₅ CVD film 28 deposition step, the same method as in the fifth embodiment is used to operate the TFT substrate for a liquid crystal display panel having a sectional view as shown in FIG. Here, the thickness of the Ta ₂ O ₅ CVD film is 10
00 °.

The TFT substrate as shown in FIG. 10 has an advantage that a short circuit between the signal line 1 and the gate wirings 22 and 23 is reduced.

[0081]

According to the present invention, since the oxide of Ta having a large dielectric constant is used for the additional capacitance portion, the occupied area ratio of the additional capacitance portion in one pixel can be reduced, and the aperture ratio of one pixel can be reduced. (Accordingly, high brightness) can be obtained. In addition, since a sufficiently large additional capacitance can be installed, the retention characteristics of the signal voltage written to one pixel are improved, the image sticking and afterimage characteristics are excellent, and image defects such as black spots, white spots, and black spots are observed. A liquid crystal display panel free from defects is obtained.

When the dielectric film has a double structure of Ta ₂ O ₅ / SiN or Ta ₂ O ₅ / SiO ₂ , the insulating property and the reliability can be improved without increasing the area occupancy of the additional capacitance. Excellent additional capacity can be installed.

Since the thickness of the Ta ₂ O ₅ film is set to 800 ° or more, the insulating property of the Ta ₂ O ₅ film does not deteriorate.

Further, since the thickness of Ta ₂ O ₅ is set to 3200 ° or less, the probability of disconnection of a step at a portion where a signal line crosses a gate line does not increase.

Further, by making the step at the end of the gate wiring made of Ta tapered, the probability of disconnection of the step at the crossing portion of the signal line at the intersection of the gate line and the signal line is reduced.

[0086] Further, after the tapered stepped end of the Ta gate wiring, since the anodized surface of the Ta gate wiring forming the _{the Ta} 2 _{O 5} film, _Ta at the end of the Ta gate wiring 2 O _The stress is not concentrated on the _five films and no crack occurs, and the breakdown voltage between the Ta gate wiring and the signal line does not decrease.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of one pixel of a liquid crystal display panel according to a first embodiment of the present invention.

FIG. 2A is a plan view showing one pixel portion of an active matrix liquid crystal display panel according to the related art. (B) is a sectional view taken along the _A 2 -A ₂ 'in (a). (C) is an equivalent circuit diagram of one pixel section shown in (a).

FIG. 3 is a sectional view of a main part of one pixel of a liquid crystal display panel according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a main part of one pixel of a liquid crystal display panel according to a third embodiment of the present invention.

FIG. 5 is a diagram showing voltage dependence of leakage current of an additional capacitor.

FIG. 6: Ta ₂ O ₅ / SiN or Ta ₂ O ₅ / SiO
FIG. 4 is a diagram showing conditions of the film thickness of the _two composite dielectric films.

FIG. 7 is a diagram showing the anodic oxidation voltage dependence of the thickness of the Ta ₂ O ₅ anodic oxide film.

FIG. 8 is a sectional view of a main part for one pixel of a liquid crystal display panel according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a main part for one pixel of a liquid crystal display panel according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a main part of one pixel of a liquid crystal display panel according to a sixth embodiment of the present invention.

[Explanation of symbols]

1 ... signal line, 2, 32 ... gate line, 3, 33 ... adjacent gate line, 4 ... TFT, 5 ... source electrode, 6 ... gate
Source-to-source capacitance, 7: additional capacitance, 8: a-Si: H
(I), 9: pixel electrode, 10: signal line cover ITO, 1
DESCRIPTION OF SYMBOLS 1 ... Gate insulating film, 12 ... Protective film, 13 ... Low resistance metal,
14: translucent glass substrate, 15: a-Si: H (n ⁺ )
Layer, 16: pixel capacitance, 17: common electrode terminal, 20: base film, 21: nitride or oxide of Si, 22: Ta gate line, 23: adjacent Ta gate line, 24: Ta oxide, 25 ... Channel protective film, 26: metal upper electrode for additional capacitance, 27: Ta ₂ O ₅ anodic oxide film, 28: Ta ₂ O
₅ CVD film.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 626C (72) Inventor Hideaki Yamamoto 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. (72) Invention Person Haruo Matsumaru 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (72) Inventor Ken Tsutsui 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (4)

[Claims] A step of depositing a tantalum film on a translucent substrate; a step of etching the tantalum film to form a plurality of tantalum wiring patterns; and a step of tapering a step at an end of the tantalum wiring pattern. Anodizing the tantalum wiring to form a tantalum oxide film having a thickness of 800 ° to 3200 ° on the surface of the tantalum wiring; a gate insulating film made of silicon nitride; an i-type amorphous silicon film and silicon nitride depositing a channel protective film made from the object, a step of patterning the channel protection film, depositing an n ⁺ -type amorphous silicon film, the n ⁺ -type amorphous silicon film, i-type amorphous silicon film pattern Forming a signal line pattern intersecting with the tantalum wiring and a metal Process and method of manufacturing become more liquid crystal display device and process for patterning so as to overlap with the tantalum wire adjacent pixel electrodes by a transparent electrode forming the source electrode pattern. 2. The tantalum film is etched by C-Cl.
2. The method for manufacturing a liquid crystal display device according to claim 1, wherein the method is performed by a dry etching method using a -F type gas. 3. The method for manufacturing a liquid crystal display device according to claim 1, wherein said step of forming said tantalum oxide film is performed by subjecting said tantalum wiring pattern to a photoresist process for forming and then performing anodic oxidation. 4. The method according to claim 1, wherein the step of depositing a tantalum film on the translucent substrate comprises depositing a tantalum film after depositing a base film for protecting glass on the glass substrate.
The manufacturing method of the liquid crystal display device according to the above.