JPH03179777A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To prevent a MOSFET in which a thin SOI layer is used from deteriorating in drain breakdown strength by a method wherein an ion implantation process is carried out for the formation of a source and a drain region before a gate electrode is formed. CONSTITUTION:A gate oxide film is formed through oxidation in an electric oven to serve as a gate insulating film 5. Then, to form a source.drain region 4, boron ions are implanted for a P channel MOSFET and arsenic ions are implanted for an N channel MOSFET. Boron ions are implanted on such a condition that the implantation range of ions are made nearly equal to the thickness of a silicon single crystal 3 of a recess. By this setup, impurity is hardly introduced into a silicon single crystal 3 of a protrusion. Therefore, a MOSFET does not change in threshold voltage. Then, a polycrystalline silicon is deposited as a gate electrode 6, and a wiring process is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MO5FET semiconductor device.

[Conventional technology]

In conventional SOI devices, the thickness of the 301 layer is approximately 4
There were 000 people. However, recently, the thickness of the 301 layer has been reduced to 1
It is becoming clear that by reducing the thickness to 000 Å or less, the current drive capability of the device can be improved and the short channel effect can be prevented. However, at this time, only the channel region of the device needs to be thinned, and if the source/drain regions are also thinned, there is a problem that the train withstand voltage decreases. In order to prevent this,
Shomi et al. (Digest of VLS I Technology Symposium) found that the SOI layer only in the channel region is thin and the SOI layer in the source/drain regions is thin, as shown in Figure 2.
A structure with a thick I layer is proposed. In FIG. 2, 1 is a silicon substrate, 2 is a silicon oxide film, 4 is a source/train region, and 6 is a gate'! It has four poles.

[Problem to be solved by the invention]

However, as shown in FIG. 2, the gate 'f4If! If the pattern No. 6 is misaligned, the drain region becomes thinner and the withstand voltage deteriorates.

The purpose of the present invention is to create a MOSFET using a thinned 301 layer.
An object of the present invention is to provide a method for manufacturing a semiconductor device that does not deteriorate drain breakdown voltage in ET.

[ff! Means to solve the problem]

In order to achieve the above object, in the method for manufacturing a semiconductor device according to the present invention, the 800 layers of only the channel region are thinner than the 800 layers of the source/drain region.
This is a method of manufacturing an ET semiconductor device, in which ion implantation is performed to form source and drain regions before forming a gate electrode.

〔Example〕

The present invention will be explained below using Examples.

FIGS. 1A to 1C are cross-sectional views showing the method for manufacturing a semiconductor device according to the present invention in order of steps. In FIG. 1(a), irregularities are created on the surface of a silicon substrate 1 by dry etching. The song part will become the channel area of the device in the future.

Thereafter, silicon oxide WA2 is grown to about 3000λ, and silicon single crystal 3 is formed thereon. This single crystal formation method is performed by a laser annealing method or an electron beam annealing method, and the film thickness of the silicon single crystal 3 in the convex portion is about 500 Å. Furthermore, the film thickness of the silicon single crystal 3 in the recessed portion is approximately 300 mm.
Next, as shown in FIG. 1(b), about 200 people formed a gate oxide film, which will become a gate insulating film, by electric furnace oxidation. Thereafter, in order to form source/drain regions 4, boron is ion-implanted for the P-channel MOSFET, and arsenic is ion-implanted for the N-channel MOSFET. The conditions for boron implantation are 110 ke.
V, 5 x 10” aJ, arsenic implantation conditions were 240 ke
V, 5 x 10"aa. This condition is to make the range of ion implantation almost the same as the film thickness of the silicon single crystal 3 in the concave part. As a result, the thickness of the silicon single crystal 3 in the convex part is 5 is a gate insulating film, in which almost no impurities need to be introduced, so that the threshold voltage of the MOSFET does not change.

Thereafter, as shown in FIG. 1C, polycrystalline silicon is formed as the gate electrode 6 and a wiring process is performed, thereby completing the present embodiment.

According to the present invention, even if the gate electrode 6 is misaligned, as shown in FIG.
Therefore, the train withstand voltage does not deteriorate.

〔Effect of the invention〕

As described above, according to the present invention, s is made into a thin film.

A semiconductor element can be obtained in which deterioration of drain breakdown voltage, which is a problem with I devices, is prevented.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) are cross-sectional views showing the method of manufacturing a semiconductor device according to the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a conventional example. 1... Silicon substrate 2... Silicon oxide film 3
...Silicon single crystal 4...Source/drain region 5...Gate insulation 1i16...Gate electrode ((L) (b> (C)

Claims (1)

[Claims] (1) A method for manufacturing a MOSFET semiconductor device in which the SOI layer only in the channel region is thinner than the SOI layer in the source/drain regions, in which ion implantation for forming the source/drain regions is performed before forming the gate electrode. A method for manufacturing a semiconductor device, characterized in that: