JPS63304668A - Manufacture of insulated-gate transistor - Google Patents

Abstract

PURPOSE:To make it possible to form a deformed LDD type S/D diffusion region by a method wherein, after a gate electrode structure has been formed by performing an ordinary process, an insulating material is deposited in such a manner that a gate electrode is coated in trapezoidal cross-section, and an S/D diffusion region having shallowly-formed gate electrode side is formed by implanting ions using said insulating material as a mask. CONSTITUTION:The state shown by the diagram (a) is obtained using the publicly known manufacturing method, and then an SiO2 24 is deposited by conducting a bias-sputtering method. The SiO2 24 is deposited in trapezoidal shape covering a gate electrode 23 as shown in the diagram (b) by conducting the above- mentioned treatment, and P<+> is ion-implanted using the trapezoidally deposited SiO2 24 and the electrode 23 as a mask. A deep S/D diffusion region 25 and an inclined S/D diffusion region 26 are formed simultaneously by conducting an ion-implanting method, and the structure shown by the diagram (c) is accomplished. As a result, the impurity density of the inclined S/D region is relatively made lower, and the impurity density distribution approximate to an LDD structure can be accomplished.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing an insulated gate transistor (hereinafter referred to as MO3Tr) having a structure similar to an LDD structure, comprising:
After forming the gate electrode, a layer of SiO□ is deposited by sputtering, typically bias sputtering, with simultaneous ion etching.

In that case, the SiOz layer forms a trapezoidal cross section and covers the gate electrode, so when ion implantation is performed using this as a mask, as shown in Figure 1, the SiOz layer is shallow near the gate electrode and is separated from the gate electrode. Accordingly, a deep S/D diffusion region is formed.

The MOS) transistor formed by the method is LD
Similar to the D-type MOS Tr, the occurrence of short channel effects is suppressed.

[Industrial application field]

The present invention relates to a method for manufacturing MO3Tr, and particularly to a method for manufacturing MO3Tr in which the short channel effect is suppressed by adopting an LDD-like structure.

As integrated circuits become more highly integrated and miniaturized, the short channel effect of MO3Tr becomes a problem.

In other words, even though the S/D distance of the MOS TR has become smaller, the supplied power supply voltage does not decrease accordingly, so the electric field between S/D increases and hot carriers are Failures such as the generation of Vth and the resulting fluctuations in VTH or the occurrence of punch-through are becoming more likely to occur.

As an MO3 element that solves this problem, an LDD structure whose cross-sectional structure is schematically shown in FIG. 3 is known. This makes the S/D region shallow and low concentration region 3.
6 and is composed of a deep and highly concentrated region 35,
This is intended to avoid punch-through by alleviating the high electric field in the channel region and increasing the distance between S/D in the deep portion. In the figure, 30 is p-type S
1 substrate, 31 is a field oxide film, 32 is a gate oxide film, and 34 is a sidewall.

Although a MOS transistor having this shape is effective in suppressing the short channel effect, the manufacturing process is complicated as will be described later.

On the other hand, in recent years, as a method for depositing insulators such as SiO2, anisotropic etching has been carried out simultaneously with the deposition. A technique commonly called bias sputtering is typical of this processing method, and is carried out, for example, as follows.

Sputtering of insulators such as SiO□ is performed at several mtorr.
A high-frequency electric field is applied to the Ar atmosphere, and SiO2 molecules are driven out from the Si○2 target by Ar ions and deposited on a Si substrate or the like. If an appropriate DC electric field is applied at this time, ion etching will also proceed at the same time, but etching progresses effectively when accelerated particles collide obliquely with the target surface, whereas deposition occurs when particles collide obliquely with the target surface. Since the maximum speed is reached when hitting the surface at right angles, as a result, the deposition progresses quickly in the direction perpendicular to the substrate, but only slowly in the diagonal direction.

That is, in bias sputtering, it is possible to give anisotropy to the deposition rate, and the degree of this can be adjusted by changing the DC bias.

[Conventional technology]

As mentioned above, an LDD structure element is known as a method for solving the problem of the short channel effect of MO3Tr. This LDD structure element is formed by the steps schematically shown in FIG.

Here, the process will be explained with reference to the same figure.

First, with a field oxide film 41 and a gate electrode 43 formed on a p-type Si substrate 40, ion implantation of P is performed to form a shallow S/D diffusion 46 (FIG. 3(a)).

A SiOz layer 44 is deposited thereon and subjected to RIE (Figure (b)), and sidewalls 44' are formed on the sides of the gate electrode.
(Figure (C)).

Using the gate electrode and sidewall as a mask, As'' is ion-implanted to form a deep S/D diffusion 45 (see (d)).

In this way, to form an MO3 element with an LDD structure,
A process for forming the sidewalls must be added.

[Problem that the invention seeks to solve]

Although the LDD type MOS transistor is effective in suppressing the short channel effect, the manufacturing process becomes complicated as described above, resulting in an increase in manufacturing cost.

The purpose of the present invention is to manufacture a MOS transistor with a structure equivalent to an LDD structure through a simplified process, to enable higher integration and miniaturization of MO8 type integrated circuits, and to lower manufacturing costs. It is.

[Means for solving problems]

In order to achieve the above object, in the manufacturing method of the present invention, after forming a gate electrode structure through a normal process, an insulating material is deposited to cover the gate electrode with a trapezoidal cross section by, for example, bias sputtering, and this is used as a mask. The ion implantation is performed to form an S/D diffusion region that is shallower on the gate electrode side.

[Operation] In bias sputtering, as mentioned above, rapid deposition occurs on a plane perpendicular to the DC electric field, and etching progresses effectively on an inclined surface, so the deposition rate is small or negative. . As a result, the insulating layer covers the gate electrode in a trapezoidal shape, and if ion implantation is performed using this as a mask, the modified LDD type S shown in FIG.
/D diffusion region is formed.

〔Example〕

FIG. 1 is a schematic cross-sectional view of a modified LDD type MOS Tr according to the present invention. In the figure, 10 is a p-type Si substrate, 13 is a gate pole, 14 is 5 iOz, and 15 is a deep S/D diffusion. The shallow sloped S/D diffusion 16 on the gate electrode side of this structure prevents short channel effects from occurring.

Hereinafter, the manufacturing process of the embodiment of the present invention will be explained with reference to FIG.

First, the state shown in figure fa1 is obtained by a known manufacturing method.

Here, 20 is a p-type Si substrate, 21 is a field oxide film,
22 is a gate oxide film, and 23 is a gate electrode.

Next, SiO□ 24 is deposited by bias sputtering. This processing condition is, for example, as follows.

Ar atmosphere, pressure crab 5-10 mtorr high frequency electric crab 13.56MHz, 5KW substrate DC bias knee 1
00 to -300■ By this treatment, SiOz is deposited in a trapezoidal shape covering the gate electrode as shown in (b1).

P'' is ion-implanted using the trapezoidally deposited SiO2 and the gate electrode as a mask.The accelerating voltage is, for example, about 40 KeV if the thickness of the gate electrode is 200 people.This ion implantation creates a deep S/D diffusion 15. Incline S/D
Diffusion 16 is formed at the same time, realizing the structure of the fci diagram.

Considering the distribution of ions implanted in this process, the central plane in the depth direction (line in the cross-sectional view) is trapezoidal in the sloped region.
Since it falls within 2, the impurity concentration in the inclined S/D region is relatively low, and an impurity concentration distribution close to that of the LDD structure is realized.

In addition to the above embodiments, it is also possible to form a MOS transistor by ion-implanting other elements such as As", Sb", etc. Furthermore, the present invention can be applied when forming a p-channel transistor on an n-type substrate. It is also possible to do so.

〔Effect of the invention〕

As explained above, an MO3Tr having an inclined S/D region is formed according to the present invention, and as can be easily inferred from its cross-sectional shape, punch-through is not only suppressed, but also an inclined S/D region is formed. The impurity concentration in the D region is relatively low, making it difficult for hot carriers to be generated.

Furthermore, the number of steps in the process of the present invention is significantly reduced compared to the manufacturing process of a normal LDD structure MO3Tr.

[Brief Description of the Drawings] Fig. 1 is a schematic cross-sectional view of a modified LDD structure MO3Tr according to the present invention. Fig. 2 is a schematic cross-sectional view showing the manufacturing process of the present invention. Fig. 3 is a schematic cross-section of a known LDD type MO3Tr. Cross-sectional view, FIG. 4 is a schematic cross-sectional view showing the manufacturing process of the conventional technology,
In the figure, 10.20, 30.40 are p-type S1 substrates, 11.21.
3L41 is field oxide film, 13.23.33.43
is the gate electrode, 14.24.44 is S i 02. 15.25, 35.45 are deep S/D diffusion, 16.26
is a sloped S/D diffusion, 22.32 is a gate oxide film, 34.44' is a sidewall, and 36.46 is a shallow S/D diffusion. Schematic sectional view 1 of a modified LDD type MO3Tr according to the present invention
Figure 3 Schematic sectional view of LDD type MO3Tr according to conventional technology Figure 4

Claims (1)

[Claims] In manufacturing an insulated gate transistor, weak anisotropic deposition and strong anisotropic etching are performed on the surface of the first conductivity type semiconductor substrate (20) on which the gate electrode structures (22, 23) are formed. The insulator layer (24
), and then ion-implanting impurities of a second conductivity type to form source/drain regions (25, 26). .