JP2856166B2 - MOSFET and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device (MO)
SFET) and its manufacturing method.

[0002]

2. Description of the Related Art To improve the switching speed of a MOSFET, it is important to improve the on-current. To improve the on-current, it is necessary to increase the carrier speed and the carrier concentration. For this purpose, the lateral electric field is generally increased by reducing the gate length, and the carrier concentration is increased by reducing the thickness of the gate insulating film, according to the scaling rule. The improvement of the on-current realized in this way is based on MOS
This corresponds to the evolution of the generation due to the miniaturization of the FET.

However, a technique for improving the on-current in MOSFETs of the same generation having the same gate length and gate insulating film thickness is extremely important in terms of improving the operation speed without relying on miniaturization. To do so, it is necessary to improve the speed of the carrier. As a method for this, a method of increasing the lateral electric field of the channel has been proposed. The structure is as shown in FIG.
i et al., “A High Performance 0.1μm MOSFET with Asymm
etric Channel Profile ", Digest of IEDM 95, pp.439-4
42). With this structure, the internal electric field in the lateral direction of the channel portion was increased, and the on-current was increased by about 20% as compared with a case where the impurity concentration distribution in the channel lateral direction was constant and no internal electric field was present.

[0004]

As shown in FIG. 4A, the channel impurity distribution in the prior art for improving the on-current without reducing the gate length is that the channel impurity region 41 is formed of boron in the lateral direction. It consisted of B1 having a uniform concentration distribution and B2 having a boron distribution in which the concentration decreased in the lateral direction from the source to the drain. As a result, as shown in FIG. 4B, the conduction band energy at the interface between the substrate and the gate insulating film was high on the source side and low on the drain side, and an internal electric field was formed. Then, the electrons are accelerated by the internal electric field, and the on-current is improved.

However, a problem with such a channel impurity distribution structure is that since the impurity concentration on the source side of the channel is increased in order to form an internal electric field, the channel is perpendicular to the substrate near the interface between the gate insulating film and the substrate. That is, the electric field in the various directions (longitudinal electric field) was strong. Usually, the mobility depends on this vertical electric field, and when the vertical electric field is large, the gate insulating film 4
2 and a decrease in mobility due to the roughness of the substrate interface is observed. For this reason, as shown in FIG. 4C, the mobility of the channel near the source is small reflecting the large vertical electric field, becomes larger as approaching the drain, and the electron velocity is lower than expected. Was.

An object of the present invention is to reduce the vertical electric field on the source side, improve the mobility on the source side,
MOSFET with a structure that can increase on-current
And a method for manufacturing the same.

[0007]

Means for Solving the Problems In the following description,
The impurity of the opposite type to the impurity that forms the conduction carrier is the first conductivity type impurity, and the impurity that forms the conduction carrier is the second impurity.
Conductive impurities. Also, specifically, an n-type MOSFE
In T, boron, gallium, aluminum, indium, or the like, which can generate holes, is used as the first conductivity type impurity, and phosphorus, which can generate electrons, is used as the second conductivity type impurity. , Arsenic, antimony, bismuth and the like. In the p-type MOSFET, contrary to the n-type, the first conductivity type impurities include phosphorus, arsenic, antimony, bismuth, etc., which can generate electrons, and the second conductivity type impurities are holes. Capable of producing boron, gallium, aluminum,
And indium.

According to a first aspect of the MOSFET structure of the present invention, in a region away from the interface with the gate insulating film, the first conductivity type impurity has a distribution in which the concentration decreases from the source to the drain, and The channel portion near the interface has a structure in which the second conductivity type impurity has a distribution that decreases from the source to the drain.

According to a second aspect of the MOSFET structure of the present invention, in the MOSFET of the first aspect, the potential at the interface between the gate insulating film and the substrate is an n-type MOSFET.
Has a structure in which the impurity distribution of the channel region is formed so as to be constant or increased from the source to the drain, and to be constant or decreased from the source to the drain.

In a first aspect of the method for manufacturing a MOSFET according to the present invention, in forming a channel impurity region of a MOSFET, a step of removing the resist in the channel impurity forming region through a resist coating, exposure, and developing steps; Performing a first ion implantation of a conduction type impurity using the resist as a mask; and performing a second ion implantation at a lower energy than the first ion implantation by inclining the first conduction type impurity from a drain direction to a source direction. And forming a channel impurity region by performing third ion implantation such that the second conductivity type impurity is inclined from the drain direction to the source direction so that the impurity distribution becomes shallower than the second ion implantation. .

In a second aspect of the method of manufacturing a MOSFET according to the present invention, in forming a channel impurity region of a MOSFET, the resist in the channel impurity forming region is removed through a resist coating, exposure, and development steps to form a first conductive type. Performing a first ion implantation of impurities using the resist as a mask, forming a gate insulating film and a gate electrode material, applying resist, exposing and developing, and etching the gate electrode; Performing a second ion implantation at a lower energy than the first ion implantation by inclining from the direction to the drain direction, and performing the second ion implantation by inclining the second conductivity type impurity from the source direction to the drain direction. Forming a channel impurity region by performing third ion implantation so that the impurity distribution becomes shallow. .

In the above-described method for manufacturing a MOSFET, the first ion implantation step may be omitted.
The method according to the above aspect may include a step of forming a thin sidewall insulating film on the side surface of the gate before the second ion implantation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The improvement of the ON current of a MOSFET according to the present invention will be described below. There are two factors for increasing the on-current, the first is an increase in carrier concentration, and the second is an increase in carrier speed. The present invention is concerned with increasing carrier speed. There are two methods for increasing the carrier velocity, namely, increasing the carrier mobility and increasing the lateral acceleration electric field from the source to the drain. Although the increase in the acceleration electric field on the source side has been described in the section of the prior art, it has not been possible to achieve compatibility with an improvement in carrier mobility as a problem. The method of the present invention improves the carrier mobility in addition to the lateral acceleration electric field,
Carrier speed can be increased to improve on-current.

In general, the mobility of Si electrons or holes (carriers) at room temperature is determined by the concentration of impurities and the like. However, in the case of a surface channel type MOSFET having a fine gate length of 0.25 μm or less, since the vertical electric field is strong, the carrier is strongly pressed against the gate insulating film, and the roughness due to the roughness of the interface between the gate insulating film and silicon. Scattering reduces carrier mobility. For this reason,
In an actually used MOSFET, the carrier mobility is mainly determined by interface roughness scattering. In order to improve the carrier mobility by reducing the influence of the interface roughness scattering, a structure which reduces the vertical electric field may be employed. As a result, the influence of roughness scattering is reduced and carrier mobility is improved.

A method for weakening the vertical electric field is to introduce a second conductivity type impurity near the gate insulating film interface. As a result, for example, in the case of an n-type MOSFET, the dependence of the energy at the bottom of the conduction band on the depth decreases near the interface, and the vertical electric field decreases. However, in this case, simply introducing the second conductivity type impurity into the surface lowers the threshold value. Therefore, the target threshold value is achieved by setting the first conductivity type impurity to a high concentration in the lower portion. Design is necessary.

In the present invention, the channel impurity distribution is designed so that the threshold is set high on the source side and low on the drain side in order to form a lateral electric field in the channel in addition to increasing the carrier mobility. With such a threshold distribution, for example, the conduction band energy of electrons decreases from the source to the drain, so that a lateral electric field can be formed. In order to design in this way, in addition to the introduction of the normal channel impurity (first conductivity type impurity), the first conductivity type impurity is introduced so that the concentration decreases from the source to the drain, and further, the vicinity of the surface of the channel is introduced. Introduces the second conductivity type impurity so as to decrease from the source to the drain. Thus, the threshold value is high on the source side and the vertical electric field is weak, and the threshold value is low on the drain side and the vertical electric field is slightly high. In this method, the carrier mobility is small on the drain side, but pinch-off occurs near the drain during operation of the MOSFET, and since the lateral electric field is very strong in this portion, the electron velocity is not significantly affected. On the source side, carrier mobility is improved and lateral electric field is increased, so more current can flow and MOSFET
Switching speed can be improved. For example, if the vertical electric field during operation is set to zero, the mobility is 800 cm ^{2 for} electrons.
/ Vs, about 200 cm ² / Vs for holes,
The improvement is about four times as much as usual. In addition to the improvement of carrier mobility, the lateral electric field on the source side is reduced to 50 kV / c.
If the value of m is set to about 1.5 times the conventional value, the on-current can be improved at least twice or more.

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a schematic sectional view of the structure of a MOSFET, a first embodiment of the present invention is an n-type MOSFET.
The case of OSFET is as follows. p-type MO
In the case of an SFET, the impurities may be reversed.

The channel impurity region 1 is formed by overlapping three impurity regions B1, B2 and As, and a sufficiently deep portion is doped so that p-type impurities are uniform under the gate (B1). The slightly deeper portion has a distribution (B2) in which the concentration of the p-type impurity decreases from the source to the drain, and the shallower portion has a distribution (As) in which the concentration of the n-type impurity decreases from the source to the drain. In FIG. 1A, the impurity concentration distribution at the depth A is such that, as shown in FIG. 1B, in addition to the distribution of the p-type impurity in the B1 region uniformly, the impurity in the B2 region has The n-type impurity in the As region is increased on the source side and decreased on the drain side. On the other hand, at the depth B, as shown in FIG. 1C, the concentration of the impurities in the B1 and As regions is lower than that in the depth A, and only the impurity in the B2 region is increased. When no voltage is applied to any of the electrodes, the energy at the bottom of the conduction band at the interface between the substrate and the gate insulating film temporarily increases when entering from the source to below the gate as shown in FIG. The impurity concentration is set so as to be constant (α) or lower (β) toward the drain under the gate. As shown in FIG. 1E, the vertical electric field is small on the source side and large on the drain side, and the mobility is large on the source side and small on the drain side. B1, B2, A
The concentration distribution of s is designed so as to satisfy FIGS. 1D and 1E and a desired threshold value.

A second embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 2 which is a schematic cross-sectional view of a method for manufacturing a MOSFET, a second embodiment of the present invention
The case of a type MOSFET is as follows. In the case of a p-type MOSFET, the impurity may be reversed.

In forming the channel impurity region of the MOSFET, as shown in FIG. 2A, a positive resist 12 is applied on the substrate 11, and the exposure and development steps are performed to remove the positive resist 12 in the channel impurity forming region. . Thereafter, using the resist as a mask, a p-type impurity is ion-implanted (first impurity ion implantation) to form a first channel impurity region 13. Next, as shown in FIG. 2B, p-type impurities are implanted obliquely at a lower energy than the first impurity ion implantation, and a second impurity ion is implanted at a lower depth than the first channel impurity region 13. A channel impurity region 14 is formed. Since this region is implanted at an angle, the concentration is high on one side of the channel (to the left of the channel impurity region in the figure and the source will be formed later), and becomes lower as it approaches the opposite side. Concentration. Next, as shown in FIG. 2C, an n-type impurity is ion-implanted obliquely from the drain side (third impurity ion implantation) to form a third channel impurity region 15.
At this time, the third channel impurity region is shallower than the second channel impurity region 14, and has a higher concentration on one side (to the left of the channel impurity region in the figure) and a lower concentration as approaching the other. Thereafter, the positive resist 12 is peeled off, and gate oxidation, gate formation, and a normal MOSFET formation step are performed.

Although the channel impurity implantation is performed three times in total here, the first impurity ion implantation may be omitted.

A third embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 3, which is a schematic cross-sectional view of a method for manufacturing a MOSFET, a third embodiment of the present invention is as follows for an n-type MOSFET. In the case of a p-type MOSFET, the impurity may be reversed.

In forming the MOSFET, as shown in FIG. 3A, a p-type first channel impurity region 22 is formed.
After forming the gate insulating film 23 and the gate electrode 24, FIG.
As shown in (b), a p-type impurity is ion-implanted obliquely from the direction in which the source is to be formed, and the second channel impurity region 2 is formed.
5 is formed. Next, as shown in FIG. 3C, an n-type impurity is ion-implanted obliquely from a direction in which the source is to be formed, to form a third channel impurity region 26. Thereafter, a MOSFET is formed through a normal source / drain forming process. In this method, since the second channel impurity region 25 and the third channel impurity region 26 are formed by oblique ion implantation from the direction in which the source is to be formed, a structure having a high concentration on the source side and a low concentration on the drain side is formed. it can.

Although the first channel impurity region is provided here, it can be omitted. Further, a thin gate sidewall insulating film may be formed before the second ion implantation.

[0027]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 Referring to FIG. 1, which is a schematic sectional view of the structure of a MOSFET, the present embodiment is as follows for an n-type MOSFET. In the case of a p-type MOSFET, the impurity may be reversed. In the region of the channel impurity 1, boron is uniformly distributed in the lateral direction of the channel at a concentration of 1 × 10 ¹⁸ cm ⁻³ at a depth of about 200 nm from the interface of the gate insulating film 2. At a depth of about 100 nm (depth B), the boron concentration has a distribution in which the concentration monotonically decreases from 1 × 10 ¹⁸ cm ⁻³ near the source to 1 × 10 ¹⁷ cm ⁻³ near the drain, and is as shallow as 20 nm. In the portion (depth A), arsenic is changed from 1.3 × 10 ¹⁸ cm ⁻³ near the source to 1 × 10 ¹⁸ cm ⁻³ near the drain.
The distribution is such that the concentration decreases toward × 10 ¹⁷ cm ⁻³ .

When no voltage is applied to any electrode, the energy at the bottom of the conduction band at the interface between the substrate and the gate insulating film is as shown in FIG.
As shown in (d), the energy once rises by about 0.4 eV when entering from below the gate to the source, but thereafter becomes constant (α) toward the drain below the gate or decreases by about 0.2 eV at the drain end. (Β). As shown in FIG. 1E, the vertical electric field is as small as 100 kV / cm or less on the source side and 1 MV on the drain side.
/ Cm, and the mobility is 800 cm ² on the source side.
/ Vs and 200 cm ² / Vs on the drain side.

Embodiment 2 Referring to FIG. 2, which is a schematic cross-sectional view of a method for manufacturing a MOSFET, a second embodiment of the present invention is as follows for an n-type MOSFET. In the case of a p-type MOSFET, the impurity may be reversed.

In forming a channel impurity region of the MOSFET, as shown in FIG. 2A, a positive resist 12 is applied to a thickness of 1 μm on a p-type silicon substrate 11 and exposed to light and developed to form a positive portion of the channel impurity region. The resist is removed. Then, boron is applied at 40 keV and 5 × 10 ¹²
First ion implantation is performed at cm ^{−2 using the} resist 12 as a mask to form a first channel impurity region 13. next,
As shown in FIG. 2B, boron is applied at 20 keV and 5 × 10 ¹² cm ⁻² from an oblique direction of 45 degrees to form the second channel impurity region 14. Since this region is ion-implanted from an oblique direction, the concentration is high on one side of the channel (to the left of the channel impurity region in the figure and the source will be formed later), and becomes lower as it approaches the opposite side. Concentration. Next, as shown in FIG.
Ion implantation is performed at 15 keV and 5 × 10 ¹² cm ⁻² from a diagonal direction of 5 degrees (third impurity ion implantation) to form a third channel impurity region 15. At this time, the third channel impurity region is shallower than the second channel impurity region 14, and has a higher concentration on one side (the left side of the channel impurity region in the figure) and a lower concentration as approaching the other. Thereafter, the positive resist 12 is peeled off, and gate oxidation, gate formation, and a normal MOSFET formation step are performed.

Embodiment 3 Referring to FIG. 3, which is a schematic cross-sectional view of a method for manufacturing a MOSFET, a third embodiment of the present invention is as follows for an n-type MOSFET. In the case of a p-type MOSFET, the impurity may be reversed.

In the formation of the MOSFET, as shown in FIG. 3A, a p-type first channel impurity region 22 is formed.
After forming the gate insulating film 23 and the gate electrode 24, FIG.
As shown in (b), boron is added to the side where the source is to be formed.
The second channel impurity region 25 is formed at 20 keV and 5 × 10 ¹² cm ⁻² from an oblique direction of 5 degrees. After that, as shown in FIG.
Ion implantation is performed at 5 keV and 5 × 10 ¹² cm ⁻² (third impurity ion implantation) to form a third channel impurity region 26. Thereafter, a MOSFET is formed through a normal source / drain forming process (FIG. 3D). In this method, since the second channel impurity region 25 and the third channel impurity region 26 use oblique ion implantation from the direction in which the source is to be formed, a structure in which the concentration is high on the source side and the concentration is low on the drain side is formed. it can.

[0034]

According to the structure and manufacturing method of the MOSFET of the present invention, the Beon current can be improved to about twice that of the conventional method without changing the gate length and the gate oxide film thickness.
As a result, the switching speed can be improved about twice.

[Brief description of the drawings]

1A is a schematic cross-sectional view of a channel structure according to a first embodiment of the present invention, FIG. 1B is a diagram showing a change in channel impurity concentration at a depth A, and FIG. (C), (d) showing the change in conduction band energy at the interface of the substrate gate insulating film, and (e) showing the relationship between the mobility in the channel direction and the vertical electric field.

FIGS. 2A to 2C are schematic sectional views showing a channel manufacturing method according to a second embodiment of the present invention.

FIGS. 3A to 3D are schematic sectional views showing a channel manufacturing method according to a third embodiment of the present invention.

4A is a schematic cross-sectional view of a channel structure of a conventional MOSFET, FIG. 4B is a diagram showing a change in channel impurity concentration at a depth A, and FIG. 4C is a diagram showing a change in conduction band energy at an interface of a substrate gate insulating film. FIG. 4D) and a diagram (d) showing the relationship between the mobility in the channel direction and the vertical electric field.

[Explanation of symbols]

 1, 41 channel impurity region 2, 23, 42 gate insulating film 3, 24, 43 gate electrode 4, 27, 44 source 5, 28, 45 drain 11, 21 substrate 12 positive resist 13, 22, first channel impurity region 14, 25 second channel impurity region 15, 26 third channel impurity region 41 channel impurity region

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78

Claims (7)

(57) [Claims] In a region away from an interface with a gate insulating film, an impurity of a first conductivity type opposite to an impurity generating a conduction carrier has a distribution in which the concentration decreases from a source to a drain, and the impurity is distributed at the interface. A MOSFET having a distribution in which a concentration of a second conductivity type impurity that generates a conduction carrier in a near channel portion decreases from a source to a drain. 2. The MOSFET according to claim 1, wherein the potential at the interface between the gate insulating film and the substrate is constant or increases from a source to a drain in an n-type MOSFET, and increases from a source to a drain in a p-type MOSFET. A MOSFET characterized in that an impurity distribution in a channel region is formed so as to be constant or decreased in the opposite direction. 3. A step of forming a channel impurity region of a MOSFET by applying a resist to a silicon substrate, removing the resist in the channel impurity forming region through exposure and development steps, and a step opposite to an impurity forming a conductive carrier. Performing a first ion implantation of the first conductivity type impurity using the resist as a mask, and tilting the first conductivity type impurity from the drain direction to the source direction at a lower energy than the first ion implantation. A step of performing ion implantation, and performing a third ion implantation such that an impurity distribution is shallower than that of the second ion implantation by inclining a second conductivity type impurity for generating a conduction carrier from a drain direction to a source direction; Forming an impurity region. 4. The MOS according to claim 3, wherein the first ion implantation step is omitted.
Manufacturing method of FET. 5. In forming a channel impurity region of a MOSFET, the resist in a channel impurity forming region is removed through a resist coating, exposure and development process, and a first conductivity type impurity which is opposite to an impurity which forms a conduction carrier is formed. Performing a first ion implantation using the resist as a mask, forming a gate insulating film and a gate electrode material, applying resist, exposing and developing, and etching the gate electrode; Performing a second ion implantation with a lower energy than the first ion implantation with an inclination in the drain direction, and a second ion implantation in which the second conductivity type impurity for generating the conduction carrier is inclined from the source direction to the drain direction. Third ion implantation is performed so that the impurity distribution becomes shallower than the ion implantation, thereby forming a channel impurity region. And a method for manufacturing a MOSFET. 6. The manufacturing method according to claim 5, wherein the first ion implantation step is omitted.
Manufacturing method of FET. 7. The manufacturing method according to claim 5, further comprising the step of forming a thin sidewall insulating film on the side of the gate before the second ion implantation.
Manufacturing method of T.