JPS63131576A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain LDD structure having precise size through a simple method by forming a gate electrode having the different length of upper and lower sides in a cross section parallel with the direction of gate length, implanting the ions of an impurity in low concentration so as to be passed through the longer side and implanting the ions of an impurity in high concentration so as not to be passed through the longer side. CONSTITUTION:A gate oxide film 2 is formed onto the surface of a p-type Si substrate 1, a polycrystalline Si layer 3 is grown, and a photo-resist layer 5 is applied and patterned. The polycrystalline Si layer 3 is etched in an isotropic manner, using the photo-resist layer 5 as a mask, and the polycrystalline Si layer 3 is formed to a tapered shape. When an SiO2 layer 2' is grown on the surface of the polycrystalline Si layer 3 through thermal oxidation and P<+> ions are implanted to shape n<-> regions, implanted ions pass through one part of the oxide film of the side wall of a gate electrode, thus forming an n<-> ion implantation regions to a shape that an upper end intrudes to the gate electrode side. When As<+> ions are implanted to shape n<+> source-drain regions, the acceleration voltage of ions is controlled, and the n<+> regions are not brought into contact with the n<-> regions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention uses ion implantation to create an LDD (Light Device).
The present invention relates to a method for forming a yDoped Drain structure with good controllability.

[Summary of the invention]

The present invention provides a method for manufacturing a transistor with an LDD structure, in which a gate electrode is formed with different lengths of an upper side and a lower side in a cross section parallel to the gate length direction, and the gate electrode passes through the longer side of the upper side and the lower side. By implanting low-concentration impurity ions while preventing the ions from passing through the long sides, high-concentration impurity ions are implanted without passing through the long sides of the LD.
This makes it possible to obtain the D structure using a simpler method than conventional manufacturing methods.

[Conventional technology]

As the integration level of VLSI improves, transistors are becoming smaller and finer, but when the channel length becomes 11 m or less, short channel effects, channel hot electron injection effects, carrier collision ionization near the drain, etc. Avalanche destruction, photoelectron generation near the drain,
Various problems have occurred, such as dielectric breakdown between the source and drain, punch-through between the source and drain, and signal transmission delay due to increased drain resistance.

These problems occur because the drain electric field is large, and an LDD structure is used to prevent this. This weakens the drain electric field by forming the drain into an n-1n9 double structure and expanding the void layer of the drain not only in the channel region but also on the n- side.

A conventional method for manufacturing an LDD structure will be explained based on FIG.

A transistor is formed inside the field oxide film 2 on the p-type Si substrate 1 in the same manner as in the usual method. Polycrystalline S
After patterning the gate electrode 3 of i, using this as a mask, Po ions are implanted to form an n- region for electric field relaxation (FIG. 2A).

A SiO□ layer 4 is grown on the entire surface by CVD method (second
Figure B).

C until the upper surface of the gate electrode 3 is exposed by the RIH method.
Back etch the VD 5iOzJW 4 to leave a SiO□ layer 4' on the sidewall (Figure 2C).

Source and drain regions of n" are formed by ion implantation of As" (FIG. 2D). (“Nikkei Microdevice J
Summer 1985 issue P, 43) [Problems to be solved by the invention] In the conventional manufacturing method of LDD structure, the sidewall is C
Since it is formed by back-etching the VD SiO□ layer, it has been difficult to precisely control the width of the sidewall.

Furthermore, it is difficult to detect the end point of RIH etching, resulting in the problem of unnecessary etching of the 5i02 film on the substrate.

Furthermore, there was a problem in that the RIE treatment caused damage to the oxide film.

[Means for solving the invention]

The present invention forms a gate electrode with different lengths of the upper side and lower side in a cross section parallel to the gate length direction, and implants low concentration impurity ions through the longer side of the upper side and the lower side,
The above-mentioned problem was solved by implanting high-concentration impurity ions while not allowing them to pass through the long sides.

[Effect]

The present invention takes advantage of the fact that ions pass through the thin part of the oxide film on the slope and that the depth of the ion implantation region can be precisely controlled by accelerating voltage.

In other words, as shown in Figure 1C, ions pass through the thin part of the oxide film in the tapered part of the gate electrode, forming an n-mW region whose upper end penetrates into the gate electrode side. As shown in the first diagram, an optimal LDD structure is formed by providing an n'' region within an n- region by appropriately selecting the accelerating voltage for As'' ions.

In the conventional manufacturing method, the width of the n layer was determined by the width of the sidewall as shown in FIG. The LDD structure is determined by the control of .

〔Example〕

The present invention will be described in detail based on FIGS. 1A to 1D.

A gate oxide film 2 is formed on the surface of an Ap type Si substrate 1 by thermal oxidation. That 5iOzJ! Polycrystalline S on top of lf2
A t-layer 3 is grown, and a photoresist layer 5 is further formed on it.
and pattern it. Using this patterned photoresist N5 as a mask, polycrystalline Si
Layer 3 is isotropically etched by plasma etching. By this isotropic etching, the polycrystalline Si layer 3 is formed into a tapered shape as shown in the figure.

B: Several hundred SiO□ layers 2' are grown on the surface of the polycrystalline Si layer 3 by thermal oxidation.

CP+ ions are implanted to form an nUI region. On this occasion,
Since the implanted ions pass through a portion of the oxide film on the side wall of the gate electrode, the n- ion implantation region is formed with its upper end penetrating into the gate electrode side.

D As,'' is ion-implanted to form n' source and drain regions. At this time, the ion acceleration voltage is controlled to prevent the ion region from penetrating into the gate side and contacting the n- region. do.

Thereafter, annealing is performed in an N2 atmosphere to recover damage caused by ion implantation.

In this example, in the cross section of the gate electrode, a forward tapered gate electrode was used where the bottom side was longer than the top side, but a reverse tapered gate electrode was used where the top side was longer than the bottom side. However, an LDD structure with a similar impurity concentration distribution can be obtained.

Further, although a polycrystalline Si layer is used for the gate electrode in this embodiment, a high melting point metal or the like may also be used.

〔Effect of the invention〕

The following effects can be expected from the manufacturing method of the present invention.

(i) The process is simple because there is no step of back-etching the CVD 5iOz layer by RIE to form a sidewall.

(ii) Since the impurity distribution is determined by two ion implantations and the tapered shape of the gate electrode without requiring side walls whose thickness is difficult to control, the impurity concentration distribution can be accurately controlled.

(iii) Problems such as damage to the oxide film on the substrate surface or etching of the oxide film itself due to RIE do not occur.

[Brief explanation of the drawing]

1A to 1D show a method of manufacturing a semiconductor device according to the present invention. 2A-2D illustrate a conventional method of manufacturing an LDD structure. l...p-type substrate 2.2'...SiO□ layer 3
...Polycrystalline Si layer 4.4'...CvDSiO
□Layer 5...Photoresist layer

Claims (1)

[Claims] A process of forming a gate electrode with different lengths on the top and bottom sides in a cross section parallel to the gate length direction, and a process of forming a low concentration impurity by passing through the long side of the top and bottom sides and the part that does not overlap with the short side. A method for manufacturing a semiconductor device comprising the steps of: implanting ions; and implanting highly concentrated impurity ions under conditions that the ions do not pass through the long sides.