JPH03175696A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH03175696A
JPH03175696A JP31582989A JP31582989A JPH03175696A JP H03175696 A JPH03175696 A JP H03175696A JP 31582989 A JP31582989 A JP 31582989A JP 31582989 A JP31582989 A JP 31582989A JP H03175696 A JPH03175696 A JP H03175696A
Authority
JP
Japan
Prior art keywords
thermosetting resin
multilayer
laminate
laminates
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31582989A
Other languages
Japanese (ja)
Inventor
Keisuke Okada
岡田 圭祐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31582989A priority Critical patent/JPH03175696A/en
Publication of JPH03175696A publication Critical patent/JPH03175696A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve wiring storing properties so as to enable high density wiring by arranging two sheets of laminates, where thermosetting resin is filled in through holes and conductive circuit patterns are made only on one side each, with the conductive circuit patterns respectively directed inward, and interposing a prepreg between them thereby molding them into a multilayer. CONSTITUTION:Drill processing and panel plating are performed to the optional position of a laminate 2a so as to form a via hole 3a, and the thermosetting resin 4a is filled in the via hole 3a, and baking treatment is done to harden it. Next, belt sander polishing is done to remove the thermosetting resin remaining at the obverse and the reverse of the laminate 2a, whereby a desired conductor circuit pattern 5a is made only at the one side layer. Next, conductor circuit patterns 5a and 5b formed at one side each are directed inward, and a prereg is interposed, and after going through a heating pressurizing process, a multilayer molded substrate 7, where laminates 2a and 2b are integrated through the prepreg layer 6a, is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線板の製造方法に関し、特に高密度実装
のために同一格子上のヴイアホールの一部の導体層が分
割されたヴイアホールを一部に有する多層印刷配線板の
製造方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer wiring board, and in particular, for high-density packaging, the present invention relates to a method for manufacturing a multilayer wiring board, and in particular, for the purpose of high-density packaging, some conductor layers of the via holes on the same grid are divided into one via hole. The present invention relates to a method for manufacturing a multilayer printed wiring board.

〔従来の技術〕[Conventional technology]

LSI、IC等の高S積化、電子機器の高性能化と経済
性向上のために多層印刷配線板(以下多層板と称す〉の
高密度化が進展している。
BACKGROUND ART Multilayer printed wiring boards (hereinafter referred to as multilayer boards) are becoming more dense in order to increase the S stack of LSIs, ICs, etc., and to improve the performance and economic efficiency of electronic devices.

多層板の高密度化に対して、主に2つの対応が図られて
いる。第1に導体層数の増加、すなわち高多層化であり
、第2の対応が基本格子間への多配線化である。しかし
ながら第1の対応では、層間の導体層を接続するヴイア
ホールの増加になり、第2の対応の多配線化、しいては
、配線の収容性を著しく制限する。そのため特にこのヴ
ノアホールを小径化する事で対応しているが板I¥/孔
径比〈アスペクト比〉が増加し多層板の製造性を著しく
阻害している。
Two main measures are being taken to address the increasing density of multilayer boards. The first response is to increase the number of conductor layers, that is, to increase the number of layers, and the second response is to increase the number of interconnects between basic lattices. However, in the first approach, the number of via holes that connect the conductor layers between layers increases, which significantly limits the number of wiring lines in the second approach, and hence the wiring capacity. Although this problem has been dealt with by reducing the diameter of the venoa holes, the plate I/hole diameter ratio (aspect ratio) increases, which significantly impedes the productivity of multilayer plates.

この問題を解決する方法としてサーフェスヴイアホール
、ブラインドヴイアホール等のヴイアホールを有する多
層印刷配線板が考案されている。
As a method to solve this problem, a multilayer printed wiring board having via holes such as surface via holes and blind via holes has been devised.

以下に代表的な製造方法を第3図(A)〜(C)を例に
とり示す。
A typical manufacturing method will be described below using FIGS. 3(A) to 3(C) as examples.

まず、積層板2aにドリル加工、パネルめっきを施しヴ
イアホール3aを形成し、フォト印刷法により片面のみ
に導体回路パターン5aを形成する(第3図(A))。
First, a via hole 3a is formed in the laminate 2a by drilling and panel plating, and a conductor circuit pattern 5a is formed on only one side by photo printing (FIG. 3(A)).

次に、先の積層板2aを2組導体回路パターン5a、5
bを内/fi17に向けて配置しプリプレグ(図示時〉
を介挿させて、加熱加圧工程を経て、積層板2a、2b
がプリプレグ層6によって一体化した多層成型基板7を
得る(第3図(B))。
Next, the previous laminate 2a is attached to two sets of conductor circuit patterns 5a, 5.
Place b towards the inside/fi17 and prepreg (as shown)
The laminates 2a and 2b are formed through a heating and pressurizing process.
A multilayer molded substrate 7 is obtained in which the components are integrated by the prepreg layer 6 (FIG. 3(B)).

次に、多層成型基板7の所望の箇所に貫通孔を穿孔し、
パネルめっき層8を施し貫通スルーホール9を形成しf
S後、フォト印刷法により、外層導体回路パターン10
a、10bを形成して従来法による多層印刷配線板11
を得ていた(第3図(C))。
Next, through holes are bored at desired locations on the multilayer molded substrate 7,
A panel plating layer 8 is applied and a through hole 9 is formed.
After S, an outer layer conductor circuit pattern 10 is formed by photo printing method.
A, 10b are formed to form a multilayer printed wiring board 11 by a conventional method.
(Figure 3 (C)).

〔発明が解決しようとする課題〕 上述した従来の製造方法は、以下の様な欠点がある。[Problem to be solved by the invention] The conventional manufacturing method described above has the following drawbacks.

まず、ヴイアホール内の樹脂充填はプリプレグに含まれ
る樹脂のみに依存している。従って積層板の厚みはプリ
プレグ層と同一の厚み程度しか得られずこの種の積層板
の厚みは最大でも0.3〜0.4mm位であり多層構成
の積層板を更に多層化する事はほぼ不可能であった。
First, filling the via hole with resin depends only on the resin contained in the prepreg. Therefore, the thickness of the laminate can only be about the same thickness as the prepreg layer, and the maximum thickness of this type of laminate is about 0.3 to 0.4 mm, and it is almost impossible to make a laminate with a multilayer structure even more layered. It was impossible.

従って通常10層板を超える多層板で同一格子上にヴイ
アホールを形成する場合は両面構成での内層としてヴイ
アホールと、貫通スルーホールを形成するかの2方法し
かなく、後者の貫通スルーホールも積層板間の1対1の
接続が主となり高多層化する程ヴイアホールネック問題
を生じていた。
Therefore, when forming via holes on the same lattice in a multilayer board with more than 10 layers, there are usually only two methods: forming via holes as the inner layer in a double-sided structure, and forming through holes, and the latter through holes can also be formed using laminated boards. The more the number of layers increases, the more the connection becomes mainly one-to-one, and the problem of via hole neck occurs.

本発明の目的は、従来の欠点を除去し、厚い積層板又は
厚い内層導体を有するfJI層板をプリプレグにより多
層化することが出来、配線収容性を向上させ高密度配線
が可能となる多層印刷配線板の製造方法を提供すること
にある。
The purpose of the present invention is to eliminate the drawbacks of the conventional methods, to make thick laminates or fJI laminates with thick inner layer conductors multilayered by prepreg, and to improve wiring accommodation and enable high-density wiring through multilayer printing. An object of the present invention is to provide a method for manufacturing a wiring board.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の多層印刷配線板の製造方法は、両面又は多層構
成からなる積層板にドリル加工、パネルめっきを施して
スルーホールを形成する工程と、前記スルーホールに熱
硬化性樹脂を充填した後、熱硬化させる工程と、前記熱
硬化された熱硬化性樹脂の71層板の表裏に残存する部
分を除去する工程と、前記スルーボール部に熱硬化性樹
脂の充填された積層板の片面のみに導電回路パターンを
形成する工程と、前記片面に導電パターンの形成された
積層板2枚をそれぞれ導電回路パターンを内側に向けて
配置し、プリプレグを介挿させて加熱・加圧し多層化成
型する工程とを含むことを特徴として構成される。
The method for manufacturing a multilayer printed wiring board of the present invention includes the steps of forming through-holes by performing drilling and panel plating on a laminate having a double-sided or multilayer structure, and filling the through-holes with a thermosetting resin. a step of thermosetting, a step of removing the portions remaining on the front and back sides of the 71-layer board of the thermosetting resin, and a step of removing only one side of the laminate with the through-ball portion filled with the thermosetting resin. A step of forming a conductive circuit pattern, and a step of arranging the two laminates each having a conductive pattern formed on one side with the conductive circuit pattern facing inside, inserting a prepreg, and heating and pressurizing it to form a multilayer. It is characterized by including the following.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
(A)〜(F)は本発明の一実施例を説明するために工
程順に示した多層印刷配線板の縦断面図である。
Next, the present invention will be explained with reference to the drawings. FIGS. 1A to 1F are vertical cross-sectional views of a multilayer printed wiring board shown in order of steps to explain an embodiment of the present invention.

予め任意の内層導体1aを有する8層成型した積層板2
aの任意の箇所にN/Cドリル加工を行ない貫通孔を穿
孔し、次いでパネルめっきを行ないヴイアホール3aを
形成する(第1図(A))。次に、ビスフェノール型エ
ポキシ樹脂に水酸化アルミニウムを20〜50%配合さ
せた熱硬化性樹脂4aをロールコータ−により、ヴイア
ホール3a内に充填し、150’C,90分間ベーキン
グ処理を行ない熱硬化させる(第1図(B))。次にベ
ルトサンダー研磨を行ない積層板2aの表裏の残存熱硬
化性樹脂を除去し、片面層のみ所望の導体回路パターン
5aを形成する〈第1図(C))、次に、71層板を2
枚2a。
8-layer molded laminate 2 having an arbitrary inner layer conductor 1a in advance
N/C drilling is performed to form a through hole at an arbitrary location of a, and then panel plating is performed to form a via hole 3a (FIG. 1(A)). Next, a thermosetting resin 4a made by blending 20 to 50% aluminum hydroxide with bisphenol type epoxy resin is filled into the via hole 3a using a roll coater, and baked at 150'C for 90 minutes to heat cure it. (Figure 1 (B)). Next, the remaining thermosetting resin on the front and back sides of the laminate 2a is removed by belt sander polishing, and a desired conductor circuit pattern 5a is formed on only one layer (Fig. 1(C)).Next, the 71-layer board is 2
Sheet 2a.

2bを準備し、片面に形成した導体回路パターン5a、
5bを内側に向けて、プリプレグ(図示時〉を介挿して
、加熱加圧工程を経て積層板2a、2bがプリプレグ層
6aによって一体化された多層成型基板7を得る(第1
図(D〉〉。
2b, and a conductor circuit pattern 5a formed on one side,
A prepreg (as shown) is inserted with the laminates 2a and 2b facing inward through a heating and pressing process to obtain a multilayer molded substrate 7 in which the laminates 2a and 2b are integrated by the prepreg layer 6a (the first
Figure (D〉〉.

次に、先の多層成型基板7aの所望の箇所に貫通孔を穿
孔し、パネルめっき層8aを施し貫通スルーホール9a
を形成しく第1図(E))、次に、フォト印刷法によっ
て外層導体回路パターン10a、10bを形成する事に
より本発明による多層印刷配線板11aを得る(第1図
(F〉〉。
Next, through holes are bored at desired locations on the multilayer molded substrate 7a, a panel plating layer 8a is applied, and the through holes 9a are formed.
Next, outer layer conductor circuit patterns 10a and 10b are formed by a photoprinting method to obtain a multilayer printed wiring board 11a according to the present invention (FIG. 1(F)).

第2図(A)〜(C)は本発明の他の実施例の縦断面図
である。まず、第1の実施例と同一の製造方法により中
間多層板12を形成する(第2図(A))。但しこの場
合導体回路パターン5Cは表裏共に形成する。次に、第
1の実施例で形成した積層板2a、2bを中間多層板1
2の外側に配置しプリプレグ(図示路)を介挿して加熱
、加圧成型し積層板2a、2bと中間多層板12がプリ
プレグM6a、6bによって一体化された多層成型基板
7bを得る(第2図(B)〉。その後、貫通スルーホー
ル9bを形成し多層印刷配線板11bを得る(第2図(
C))。
FIGS. 2(A) to 2(C) are longitudinal cross-sectional views of other embodiments of the present invention. First, the intermediate multilayer board 12 is formed by the same manufacturing method as in the first embodiment (FIG. 2(A)). However, in this case, the conductive circuit pattern 5C is formed on both the front and back sides. Next, the laminated plates 2a and 2b formed in the first embodiment are attached to the intermediate multilayer plate 1.
The multilayer molded substrate 7b in which the laminate plates 2a, 2b and the intermediate multilayer plate 12 are integrated by the prepregs M6a, 6b is obtained by inserting a prepreg (path shown in the figure) on the outside of the laminate plate 2a, 2b and the intermediate multilayer plate 12 by heating and pressure molding. (B)>. Thereafter, through-holes 9b are formed to obtain a multilayer printed wiring board 11b (Fig. 2 (B)).
C)).

この実施例では中間多層板12の使用によりさらに同一
格子点上にさらにヴイアホールを形成出来るため、より
高密度実装が可能である。
In this embodiment, by using the intermediate multilayer board 12, more via holes can be formed on the same lattice point, so higher density packaging is possible.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は以下の様な効果がある。 As explained above, the present invention has the following effects.

(1〉貫通スルーホールをヴイアホールとして使用する
際、同一格子点上に分割されたヴイアホールとして配置
でき配線収容性が向上し、高密度配線が可能となる。
(1> When using a through-hole as a via hole, it can be arranged as a divided via hole on the same lattice point, improving wiring accommodation and enabling high-density wiring.

(2)板厚の厚い高多層板を任意に祝数枚−括成型する
事が可能となり、特に両面に表面実装部品が大量に搭載
される場合には同一層面の配線は分割されたヴイアホー
ル配線を施し、゛表裏間の配線は貫通スルーホール型の
ヴイアホールで配線を施す事により比略的に配線収容性
と向上させる事が可能である。
(2) It is now possible to collectively mold any number of thick multi-layer boards, and especially when a large number of surface mount components are mounted on both sides, the wiring on the same layer is divided into via-hole wiring. It is possible to relatively improve the wiring accommodation capacity by providing wiring between the front and back sides using through-hole type via holes.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)〜(F)は本発明の一実施例を説明するた
めに工程順に示した多層印刷配線板の縦断面図、第2図
(A)〜(C)は本発明の他の実施例を説明するために
工程順に示した多層印刷配線板の主要工程の縦断面図、
第3図(A)〜(C)は従来の多層印刷配線板の製造方
法の一例を説明するために工程順に示した縦断面図であ
る。 la、lb、  1cm 内層導体、2a、2b・・・
積層板、3a、3b、3c=・ヴイアホール、4a。 4b、4cm−−熱硬化性樹脂、5a、5b、 5c=
・導体回路パターン、6.6a、6b・・・プリプレグ
層、7 7a、7b・−多層成型基板、8.8a。 8b・・・パネルめっき層、9.9a、9b・・・貫通
スルーホール、10a、10b・・・外層導体回路パタ
ーン、11.lla、  11b−・−多層印刷配線板
、12・・・中間多層板。
FIGS. 1(A) to (F) are longitudinal cross-sectional views of a multilayer printed wiring board shown in the order of steps to explain one embodiment of the present invention, and FIGS. A vertical cross-sectional view of the main steps of a multilayer printed wiring board shown in order of steps to explain an example of
FIGS. 3(A) to 3(C) are longitudinal cross-sectional views shown in order of steps to explain an example of a conventional method for manufacturing a multilayer printed wiring board. la, lb, 1cm inner layer conductor, 2a, 2b...
Laminated board, 3a, 3b, 3c = Via hole, 4a. 4b, 4cm--thermosetting resin, 5a, 5b, 5c=
- Conductor circuit pattern, 6.6a, 6b...Prepreg layer, 7 7a, 7b...Multilayer molded board, 8.8a. 8b... Panel plating layer, 9.9a, 9b... Penetration through hole, 10a, 10b... Outer layer conductor circuit pattern, 11. lla, 11b--Multilayer printed wiring board, 12... Intermediate multilayer board.

Claims (1)

【特許請求の範囲】[Claims] 両面又は多層構成からなる積層板にドリル加工,パネル
めっきを施してスルーホールを形成する工程と、前記ス
ルーホールに熱硬化性樹脂を充填した後熱硬化させる工
程と、前記熱硬化された熱硬化性樹脂の積層板の表裏に
残存する部分を除去する工程と、前記スルーホール部に
熱硬化性樹脂の充填された積層板の片面のみに導電回路
パターンを形成する工程と、前記片面に導電パターンの
形成された積層板2枚をそれぞれ導体回路パターンを内
側に向けて配置し、プリプレグを介挿させて加熱・加圧
し多層化成型する工程とを含むことを特徴とする多層印
刷配線板の製造方法。
A process of forming through-holes by performing drilling and panel plating on a laminate having a double-sided or multilayer structure, a process of filling the through-holes with a thermosetting resin and then thermosetting it, and a process of thermosetting the thermosetting resin. a step of removing remaining portions on the front and back sides of the thermosetting resin laminate, a step of forming a conductive circuit pattern on only one side of the laminate with the through-hole portion filled with thermosetting resin, and a conductive pattern on the one side. The manufacturing of a multilayer printed wiring board comprising the steps of arranging two laminates each having a conductor circuit pattern facing inward, interposing a prepreg, and heating and pressurizing the two laminates to form a multilayered structure. Method.
JP31582989A 1989-12-04 1989-12-04 Manufacture of multilayer printed wiring board Pending JPH03175696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31582989A JPH03175696A (en) 1989-12-04 1989-12-04 Manufacture of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31582989A JPH03175696A (en) 1989-12-04 1989-12-04 Manufacture of multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH03175696A true JPH03175696A (en) 1991-07-30

Family

ID=18070068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31582989A Pending JPH03175696A (en) 1989-12-04 1989-12-04 Manufacture of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH03175696A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155953A (en) * 1974-11-11 1976-05-17 Hitachi Ltd KANTSUSETSUZOKUKONAIGA JUTEN SARETA TASOPURINTOKAIROBANTOSONO SEIHO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5155953A (en) * 1974-11-11 1976-05-17 Hitachi Ltd KANTSUSETSUZOKUKONAIGA JUTEN SARETA TASOPURINTOKAIROBANTOSONO SEIHO

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