JPH021391B2 - - Google Patents

Info

Publication number
JPH021391B2
JPH021391B2 JP58209308A JP20930883A JPH021391B2 JP H021391 B2 JPH021391 B2 JP H021391B2 JP 58209308 A JP58209308 A JP 58209308A JP 20930883 A JP20930883 A JP 20930883A JP H021391 B2 JPH021391 B2 JP H021391B2
Authority
JP
Japan
Prior art keywords
forming
laminate
copper
holes
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58209308A
Other languages
Japanese (ja)
Other versions
JPS60101997A (en
Inventor
Masashige Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP20930883A priority Critical patent/JPS60101997A/en
Publication of JPS60101997A publication Critical patent/JPS60101997A/en
Publication of JPH021391B2 publication Critical patent/JPH021391B2/ja
Granted legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

【発明の詳細な説明】 本発明は多層印刷配線板の製造方法に関し、特
に大電流を供給できる厚い導体層を内層に有する
多層印刷配線板に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer printed wiring board, and more particularly to a multilayer printed wiring board having a thick conductive layer as an inner layer capable of supplying a large current.

一般に多層印刷配線板(以下多層板と略称)は
内層に電源等を供給する銅層を有し、従来からフ
オトエツチング法で銅層に導電パターンの形成を
している。
In general, a multilayer printed wiring board (hereinafter abbreviated as multilayer board) has a copper layer in its inner layer for supplying power, etc., and a conductive pattern has conventionally been formed on the copper layer by photo-etching.

近年、大型コンピユータのような情報処理機器
においては、半導体素子の高集積化・高速化に伴
なつて、これらを実装する印刷配線板(以下、配
線板と略称)の配線収容率の向上は勿論である
が、配線板を介して多量の電流を供給する必要上
から、多層板化されると共にその層数も増加して
きている。
In recent years, in information processing equipment such as large computers, as semiconductor elements have become more highly integrated and faster, the wiring capacity of printed wiring boards (hereinafter referred to as wiring boards) on which these devices are mounted has of course improved. However, due to the need to supply a large amount of current through the wiring board, the number of layers has been increasing as the board has become multilayered.

一方、高密度実装に伴なつて配線板上の入出力
用のピンの数も増加し、従来は100ミルの格子間
隔上にスルホールを設けていたが、格子間隔も75
ミルと縮小化されている。
On the other hand, with high-density packaging, the number of input/output pins on wiring boards has also increased, and although through-holes were previously provided on a grid spacing of 100 mils, the grid spacing has also increased to 75 mils.
It has been reduced to a mill.

その結果、多層板の内層に設けられている電源
層やグランド層の銅層の体積が減少して多量の電
流の供給を難しくしている。
As a result, the volumes of the copper layers of the power supply layer and ground layer provided in the inner layer of the multilayer board are reduced, making it difficult to supply a large amount of current.

従つて近年実用化されている大型コンピユータ
用の配線板は高多層化が進み、20層前後の多層構
成が一般的となり、電源層、グランド層が半分以
上を占めるに至つている。これらの電源層、グラ
ンド層は一般的には銅張り積層板にフオト・エツ
チング法で導電パターンを形成するために銅層の
厚さとしては、2〜3オンス銅箔が限界となつて
いる。従つて第1図に示すように厚い銅箔を使え
ばエツチング時のサイド・エツチング量が増大
し、導電パターンの高精度化が困難となり、第1
図のスルーホール8と電源層またはグランド層の
内層銅層1aとの距離精度が悪化し、絶縁性が著
しく損なわれる。
Therefore, wiring boards for large computers that have been put into practical use in recent years have become increasingly multi-layered, with multilayer configurations of around 20 layers now common, with the power supply layer and ground layer accounting for more than half of the board. Generally, conductive patterns are formed on these power supply layers and ground layers by photo-etching on a copper-clad laminate, so the thickness of the copper layer is limited to 2 to 3 ounces of copper foil. Therefore, as shown in Figure 1, if a thick copper foil is used, the amount of side etching will increase during etching, making it difficult to improve the precision of the conductive pattern.
The distance accuracy between the through hole 8 shown in the figure and the inner copper layer 1a of the power supply layer or the ground layer deteriorates, and the insulation property is significantly impaired.

従つて、大電流供給に対しては、電源層等の層
数を増すこととなり、多層板の高多層化が進行
し、その製造性が難しくなつている。この解決の
方法として、厚い銅板を用いて、スルーホールと
非接続部分を機械的に除去する方法もあるが、こ
の銅板を多層板の内層に配した場合には第2図の
ように内層銅層1a,1bが板端に露出し、内層
銅層1a,1b同志または導電パターン99に接
近又は短絡するため、多層板の絶縁性が著しく損
なわれると云う欠点がある。
Therefore, in order to supply a large current, the number of layers such as power supply layers has to be increased, and the number of layers in multilayer boards is increasing, making it difficult to manufacture them. One way to solve this problem is to use a thick copper plate and mechanically remove the through holes and non-connecting parts, but when this copper plate is placed on the inner layer of a multilayer board, the inner layer Since the layers 1a and 1b are exposed at the edge of the board and come close to or short-circuited to the inner copper layers 1a and 1b or to the conductive pattern 99, there is a drawback that the insulation properties of the multilayer board are significantly impaired.

本発明の目的はかかる従来の欠点を解消した多
層板の製造方法を提供することにある。
An object of the present invention is to provide a method for manufacturing a multilayer board that eliminates such conventional drawbacks.

本発明によれば、多層板の内層に使われている
銅箔の2〜20倍程度の厚みを有する銅箔にスルー
ホールと接続しないクリアランスホールを銅層の
厚みに関係なく高精度に形成し、かつ多層板の板
端部にこれらの銅層を露出させないことを特徴と
する多層板の製造方法が得られる。
According to the present invention, clearance holes that are not connected to through holes are formed with high precision in a copper foil that is approximately 2 to 20 times thicker than the copper foil used for the inner layer of a multilayer board, regardless of the thickness of the copper layer. A method for manufacturing a multilayer board is obtained, which is characterized in that the copper layers are not exposed at the ends of the multilayer board.

以下、本発明の実施例を第3図A〜Hを参照し
て説明する。厚さ0.1〜1.6mm程度の銅板10aに
N/Cボール盤による孔明け、プレスによる打抜
き等でクリアランス孔2a〜1,2a〜2をグラ
ンド層と非接続部となる位置に穿設する(第3図
A)。
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 3A to 3H. Clearance holes 2a-1, 2a-2 are bored in a copper plate 10a with a thickness of about 0.1 to 1.6 mm by drilling with an N/C drilling machine, punching with a press, etc. at positions that are not connected to the ground layer (third Figure A).

次にクリアランス孔2a〜1,2a〜2を有す
る銅板10aと同じ方法で製造したクリアランス
孔2a〜1,2a〜2を有する銅板10bをプ
リ・プレグ3aを介して積み重ね(第3図B)、
プレスなどで加圧、加熱して厚い銅層の導電パタ
ーンを上下に有する積層体3を形成する(第3図
C)。次に配線板の外形端に相当する部分の銅層
すなわち積層体3の上下の銅板10a,10bを
フオト・エツチングによつてプリプレグ3aが露
出するまで除去して溝状の外形輪郭パターン4
a,4bを形成する(第3図D)。次にこのエツ
チングで除去された積層体3の外形輪郭パターン
4a,4b及びドリルなどを用いた機械的加工で
形成させたクリアランス孔2a−1,2a−2、
2b−1,2b−2に、例えば液状エポキシ樹脂
の貧溶媒を用いたエポキシ樹脂溶液にポリアミド
ビスマレイミド樹脂粉末を均一に分散させたペー
スト状組成物をロールコーター、ドクターナイフ
コータ等の手段で充填途布した後、温度150℃で
30分間乾燥してBステージ状態にするか、又は温
度150℃で90分間乾燥してCステージ状態とした
充填樹脂部5を形成する(第3図E)。
Next, the copper plate 10a having the clearance holes 2a-1, 2a-2 and the copper plate 10b having the clearance holes 2a-1, 2a-2 manufactured by the same method are stacked via the pre-preg 3a (FIG. 3B),
By pressurizing and heating with a press or the like, a laminate 3 having conductive patterns of thick copper layers on the upper and lower sides is formed (FIG. 3C). Next, the copper layer corresponding to the outer edge of the wiring board, that is, the upper and lower copper plates 10a and 10b of the laminate 3, is removed by photo-etching until the prepreg 3a is exposed, forming a groove-shaped outer contour pattern 4.
a, 4b are formed (Fig. 3D). Next, the outer contour patterns 4a, 4b of the laminate 3 removed by this etching and the clearance holes 2a-1, 2a-2 formed by mechanical processing using a drill or the like,
2b-1 and 2b-2 are filled with a paste composition in which polyamide bismaleimide resin powder is uniformly dispersed in an epoxy resin solution using a poor solvent for liquid epoxy resin using a roll coater, a doctor knife coater, or the like. After being discontinued, the temperature is 150℃.
The filled resin portion 5 is formed by drying for 30 minutes to obtain a B-stage state or by drying at a temperature of 150° C. for 90 minutes to obtain a C-stage state (FIG. 3E).

次に充填樹脂部5を形成した積層体3の上下に
片面銅張り積層板6a,6bの銅張り面を外側に
してプリプレグ層3a,3bの層を介挿して組み
立てる(第3図F)。次にこれを加圧・加熱しし
て一体化し内層に厚い銅層の導電パターンを有す
る積層体7を形成する。(第3図G)。
Next, the prepreg layers 3a and 3b of the single-sided copper-clad laminates 6a and 6b are inserted above and below the laminate 3 on which the filled resin portion 5 has been formed, with the copper-clad surfaces facing outward (FIG. 3F). Next, this is pressurized and heated to be integrated to form a laminate 7 having a conductive pattern of a thick copper layer on the inner layer. (Figure 3G).

次に通常のスルーホール配線板の製造方法によ
り、孔明け・スルーホールめつき・フオトエツチ
ング法でスルーホール8、導電パターン9a,9
bを所定の位置に形成した後、端部に内部導体が
露出しないように機械的加工で溝上の外形輪郭パ
ターン4a,4bの位置で切断して外形を仕上げ
て、本発明による内層に厚い銅層の導電パターン
を有する多層板17を得る(第3図H)。
Next, using the usual manufacturing method for through-hole wiring boards, through-holes 8 and conductive patterns 9a and 9 are formed by drilling, through-hole plating, and photo-etching.
b is formed in a predetermined position, the outer shape is finished by cutting at the outer contour patterns 4a and 4b on the groove by mechanical processing so that the inner conductor is not exposed at the end, and the inner layer according to the present invention is made of thick copper. A multilayer board 17 having a conductive pattern of layers is obtained (FIG. 3H).

以上、本発明によつて次の効果が得られる。 As described above, the following effects can be obtained by the present invention.

(i) 内層に厚い導電パターンを有しているのでエ
ツチングによるサイドエツチは生じることはな
い。
(i) Since the inner layer has a thick conductive pattern, side etching will not occur due to etching.

(ii) しかも、設計的に導体層の厚みを変えても導
電パターンの精度は変らず、高精度化に対応し
た多層板の製造方法が提供できる。
(ii) Moreover, even if the thickness of the conductor layer is changed in terms of design, the accuracy of the conductive pattern does not change, and a method for manufacturing a multilayer board that is compatible with higher accuracy can be provided.

(iii) 板端部に内層の導体層が露出していないの
で、絶縁抵抗の低下を招くことがなくなる。従
つて層間絶縁特性の優れた多層板が提供でき
る。
(iii) Since the inner conductor layer is not exposed at the edge of the board, there is no reduction in insulation resistance. Therefore, a multilayer board with excellent interlayer insulation properties can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は従来の製造方法による多層プ
リント配線板の断面図。第3図A〜Hは本発明多
層プリント配線板の製造工程を示す断面図。 1a,1b……内層銅層、10a,10b……
銅板、2a−1,2a−2,2b−2……クリア
ランス孔、3,7……積層体、3a……プリ・プ
レグ、4a,4b……外形輪郭パターン、5……
充填樹脂層、6a,6b……積層体、8……スル
ーホール、9a,9b……導電パターン、17…
…多層板。
FIGS. 1 and 2 are cross-sectional views of a multilayer printed wiring board manufactured by a conventional manufacturing method. 3A to 3H are cross-sectional views showing the manufacturing process of the multilayer printed wiring board of the present invention. 1a, 1b...inner copper layer, 10a, 10b...
Copper plate, 2a-1, 2a-2, 2b-2...Clearance hole, 3,7...Laminated body, 3a...Pre-preg, 4a, 4b...Outline contour pattern, 5...
Filled resin layer, 6a, 6b... laminate, 8... through hole, 9a, 9b... conductive pattern, 17...
...Multilayer board.

Claims (1)

【特許請求の範囲】 1 次の工程を含むことを特徴とする多層印刷配
線板の製造方法。 (イ) 導電パターンを形成する導電性シートのスル
ホールと非接続部を形成する部分に孔部を設け
る工程; (ロ) 前記孔部を設けた導電性シートの1枚以上か
らなる導体層をプリプレグを介挿して内層に積
み重ねて積層板を形成する工程; (ハ) 前記積層板の導体層に前記プリプレグが露出
する溝状の外形輪郭線を形成する工程; (ニ) 前記外形輪郭線に熱硬化性樹脂を埋め込んだ
後、加熱硬化してBステージ状態に形成する工
程; (ホ) 前記熱硬化性樹脂を埋め込んだ積層板と、通
常の導体パターンを形成した積層板、導体層を
プリプレグを介挿して成型体を形成する工程。 (ヘ) 前記導電性シートが端部に露出しないように
前記溝状の外形輪郭線に沿つて前記成型体を切
断する工程。 2 前記導電性シートを厚さ0.1〜1.6mmの銅箔ま
たは銅板を用いたことを特徴とする特許請求の範
囲第1項記載の多層印刷配線板の製造方法。
[Scope of Claims] 1. A method for manufacturing a multilayer printed wiring board, characterized by including the following steps. (b) A process of forming holes in the through-holes of the conductive sheet forming the conductive pattern and the portions forming the non-connecting parts; (b) Preparing the conductor layer consisting of one or more conductive sheets in which the holes are formed; (c) Forming a groove-shaped outer outline in which the prepreg is exposed in the conductor layer of the laminate; (d) Applying heat to the outer outline. A process of embedding a curable resin and then heating and curing it to form a B-stage state; (e) The laminate in which the thermosetting resin is embedded, the laminate on which a normal conductor pattern is formed, and the conductor layer are made of prepreg. A process of forming a molded body by inserting. (F) A step of cutting the molded body along the groove-like outer contour line so that the conductive sheet is not exposed at the end. 2. The method of manufacturing a multilayer printed wiring board according to claim 1, wherein the conductive sheet is a copper foil or a copper plate having a thickness of 0.1 to 1.6 mm.
JP20930883A 1983-11-08 1983-11-08 Method of producing multilayer printed circuit board Granted JPS60101997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20930883A JPS60101997A (en) 1983-11-08 1983-11-08 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20930883A JPS60101997A (en) 1983-11-08 1983-11-08 Method of producing multilayer printed circuit board

Publications (2)

Publication Number Publication Date
JPS60101997A JPS60101997A (en) 1985-06-06
JPH021391B2 true JPH021391B2 (en) 1990-01-11

Family

ID=16570801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20930883A Granted JPS60101997A (en) 1983-11-08 1983-11-08 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60101997A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0754874B2 (en) * 1986-10-20 1995-06-07 フアナツク株式会社 Multilayer printed wiring board
JP2003332752A (en) * 2002-05-14 2003-11-21 Shinko Electric Ind Co Ltd Metal core substrate and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5418732A (en) * 1977-07-12 1979-02-13 Asahi Chemical Ind Image formation
JPS5435671A (en) * 1977-08-25 1979-03-15 Toyo Electric Mfg Co Ltd Commutation fault detector

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5418732A (en) * 1977-07-12 1979-02-13 Asahi Chemical Ind Image formation
JPS5435671A (en) * 1977-08-25 1979-03-15 Toyo Electric Mfg Co Ltd Commutation fault detector

Also Published As

Publication number Publication date
JPS60101997A (en) 1985-06-06

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