JP4292397B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

Info

Publication number
JP4292397B2
JP4292397B2 JP2003329343A JP2003329343A JP4292397B2 JP 4292397 B2 JP4292397 B2 JP 4292397B2 JP 2003329343 A JP2003329343 A JP 2003329343A JP 2003329343 A JP2003329343 A JP 2003329343A JP 4292397 B2 JP4292397 B2 JP 4292397B2
Authority
JP
Japan
Prior art keywords
electronic component
insulating
wiring board
metal layer
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2003329343A
Other languages
Japanese (ja)
Other versions
JP2005101021A (en
Inventor
卓 石岡
Original Assignee
株式会社トッパンNecサーキットソリューションズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社トッパンNecサーキットソリューションズ filed Critical 株式会社トッパンNecサーキットソリューションズ
Priority to JP2003329343A priority Critical patent/JP4292397B2/en
Publication of JP2005101021A publication Critical patent/JP2005101021A/en
Application granted granted Critical
Publication of JP4292397B2 publication Critical patent/JP4292397B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

本発明は、チップコンデンサ等の電子部品を内蔵する配線板の製造方法に関する。   The present invention relates to a method for manufacturing a wiring board incorporating an electronic component such as a chip capacitor.

配線基板表面に実装されるICチップ等の電子部品に容量性機能を与えることで電源ノイズの影響を低減できるようにした、以下のような容量性印刷配線基板が知られている。   The following capacitive printed wiring board is known in which the influence of power supply noise can be reduced by giving a capacitive function to an electronic component such as an IC chip mounted on the surface of the wiring board.

この容量性印刷配線基板は、エポキシ等の絶縁性樹脂又は誘電性シートの両側に導電性シートを組み合わせ、加熱加圧成型することにより製造されたコンデンサ積層体を持つ。誘電性シートの代表的な例としては、エポキシ樹脂等の絶縁性樹脂と高誘電率フィラのコンポジット材が用いられる。また、導電性シートとしては、金属箔、特に実用的には銅箔が用いられる(例えば、特許文献1参照)。   This capacitive printed wiring board has a capacitor laminated body manufactured by combining a conductive sheet on both sides of an insulating resin such as epoxy or a dielectric sheet and molding it by heating and pressing. As a typical example of the dielectric sheet, a composite material of an insulating resin such as an epoxy resin and a high dielectric constant filler is used. Further, as the conductive sheet, a metal foil, particularly a copper foil is used practically (see, for example, Patent Document 1).

この場合、静電容量は、例えば18pF/mm2 程度と小さく、特に高周波回路に適用した場合におけるデカップリングには不十分である。 In this case, the capacitance is as small as about 18 pF / mm 2 , for example, and is insufficient for decoupling when applied to a high-frequency circuit.

一方、基板表面に実装されたICチップ等の電子部品と電源との間の配線に起因するループインダクタンスの低減を目的としたプリント配線板の製造方法として、以下のような製造方法が知られている。   On the other hand, the following manufacturing method is known as a method for manufacturing a printed wiring board for the purpose of reducing loop inductance caused by wiring between an electronic component such as an IC chip mounted on a substrate surface and a power source. Yes.

プリプレグを積層してなる積層板に、チップコンデンサを収容するための通孔を形成する。この通孔に、電極の表面に導電性ペーストが塗布されているチップコンデンサを収容し、通孔とチップコンデンサとの間に接着剤を充填する。次に、チップコンデンサを収容した積層板の両面に樹脂フィルムをあわせ、両面から加圧して表面を平坦にする。その後、加熱して硬化させることで、チップコンデンサを収容した収容層及び接続層からなるコア基板を完成する。   A through hole for accommodating a chip capacitor is formed in a laminated board formed by laminating prepregs. A chip capacitor in which a conductive paste is applied to the surface of the electrode is accommodated in the through hole, and an adhesive is filled between the through hole and the chip capacitor. Next, a resin film is put on both sides of the laminated plate containing the chip capacitor, and the surface is flattened by applying pressure from both sides. Then, the core substrate which consists of the accommodation layer and the connection layer which accommodated the chip capacitor is completed by heating and hardening.

続いて、コア基板にレーザーにて非貫通孔を、ドリルにてスルーホール用の通孔をそれぞれ明け、デスミア処理後に、無電解めっきを施して公知のセミADD工法等で配線パターン、ビアホ一ル、スルーホールを形成する。更に、公知の方法でビルドアップ層を形成することによりループインダクタンスを低減したプリント配線板が提供される(例えば、特許文献2参照)。   Subsequently, a non-through hole is drilled in the core substrate with a laser and a through hole for a through hole is drilled with a drill. After the desmear treatment, electroless plating is performed and a wiring pattern and via hole are formed by a known semi-ADD method. , Through holes are formed. Furthermore, a printed wiring board in which the loop inductance is reduced by forming a buildup layer by a known method is provided (see, for example, Patent Document 2).

上記のプリント配線板の製造方法では、積層板に形成された通孔、つまり収容孔にチップコンデンサを収容するが、積層セラミックコンデンサ等の場合、自動機械による収容はコンデンサに無理な力が加わって破壊されるおそれがあるので、手作業による収容が必要となる。また、埋め込み、内蔵用に開発された薄型コンデンサの収容孔への収容は難しく、収容孔とコンデンサとの間に隙間を設ける必要がある。そして、収容孔とコンデンサ間に隙間があるために、収容孔とコンデンサの側面に接着剤を介在させる必要があるが、コンデンサの形状によっては側面の接着が困難な場合がある。
特許第2738590号明細書 特開2002−271032号公報
In the above printed wiring board manufacturing method, the chip capacitor is accommodated in the through hole formed in the laminated board, that is, the accommodation hole. However, in the case of a multilayer ceramic capacitor or the like, the automatic machine accommodates the capacitor with an excessive force. Since it may be destroyed, it must be housed manually. Further, it is difficult to accommodate the thin capacitor developed for embedding and built-in in the accommodation hole, and it is necessary to provide a gap between the accommodation hole and the capacitor. Since there is a gap between the accommodation hole and the capacitor, it is necessary to interpose an adhesive between the accommodation hole and the side surface of the capacitor. However, depending on the shape of the capacitor, it may be difficult to adhere the side surface.
Japanese Patent No. 2738590 JP 2002-271032 A

本発明の課題は、チップコンデンサ等の電子部品を内蔵するに際し、電子部品の破損防止に有効な配線板の製造方法を提供することにある。   An object of the present invention is to provide a method of manufacturing a wiring board that is effective in preventing damage to an electronic component when incorporating an electronic component such as a chip capacitor.

本発明の他の課題は、高周波回路に適用した場合におけるデカップリングに必要な大容量の静電容量を得るのに適した配線板の製造方法を提供することにある。   Another object of the present invention is to provide a method of manufacturing a wiring board suitable for obtaining a large capacitance necessary for decoupling when applied to a high frequency circuit.

本発明は、電子部品を内蔵する配線板の製造方法において、電子部品が第1、第2の電極を有するコンデンサであり、他面側に第1の金属層を有する絶縁性樹脂板に、封止後の電子部品の位置を判別するために、前記第1の金属層及び当該絶縁性樹脂板の予め定められた位置にこれらを貫通する少なくとも1つの位置決め穴を形成する工程と、前記絶縁性樹脂板の一面上に少なくとも1つの前記電子部品を載置し、その際に位置決め穴から見た電子部品の位置を撮像手段により観測し記憶する工程と、前記電子部品の実装位置に対応する箇所に該電子部品の大きさに合わせて穴あるいは切り欠きをあけた第1の絶縁性熱硬化樹脂と該第1の絶縁性熱硬化樹脂の上面側をカバーし得る上面側に第2の金属層を有する第2の絶縁性熱硬化樹脂とを、前記電子部品を載置した前記絶縁性樹脂板に組み合わせて加熱加圧成型を行う工程とを含むことにより、前記電子部品を前記絶縁性樹脂板及び前記第1、第2の絶縁性熱硬化樹脂で空隙の無い状態に封止すると共に、前記位置決め穴を前記加熱加圧成型工程において硬化した前記第1の絶縁性熱硬化樹脂により塞ぐことで封止部の表面が平滑になるようにし、更に、前記加熱加圧成型工程の後に、前記記憶する工程において記憶されたデータにより、前記位置決め穴を基準位置として前記第1の金属層及び前記絶縁性樹脂板に前記第1、第2の電極の一方に至るビアホールを形成すると共に、前記第2の金属層及び硬化した前記第2の絶縁性熱硬化樹脂に前記第1、第2の電極の他方に至るビアホールを形成する工程と、形成されたビアホールにそれぞれめっきを施して前記第1の金属層と前記第1、第2の電極の一方とを接続すると共に、前記第2の金属層と前記第1、第2の電極の他方とを接続する工程とを含むことを特徴とする。 The present invention relates to a method of manufacturing a wiring board incorporating an electronic component, wherein the electronic component is a capacitor having first and second electrodes, and is sealed on an insulating resin plate having a first metal layer on the other side. A step of forming at least one positioning hole penetrating the first metal layer and the insulating resin plate in a predetermined position in order to determine the position of the electronic component after stopping ; A step of placing at least one electronic component on one surface of the resin plate, and observing and storing the position of the electronic component viewed from the positioning hole by the imaging means at that time, and a location corresponding to the mounting position of the electronic component A first insulating thermosetting resin having holes or notches formed in accordance with the size of the electronic component and a second metal layer on the upper surface side capable of covering the upper surface side of the first insulating thermosetting resin a second insulating thermosetting resin having And a step of performing heat and pressure molding in combination with the insulating resin plate on which the electronic component is placed, thereby making the electronic component the insulating resin plate and the first and second insulating thermosetting resins. in addition to sealing the absence of voids, as the surface of the sealing portion becomes smooth by the positioning holes blocked by the first insulating thermosetting resin cured in the hot pressing mold process, further After the heat and pressure molding step, the first and second electrodes are formed on the first metal layer and the insulating resin plate with the positioning hole as a reference position based on the data stored in the storing step. Forming a via hole extending to one side and forming a via hole extending to the other of the first and second electrodes in the second metal layer and the cured second insulating thermosetting resin; Biaho The first metal layer and one of the first and second electrodes are connected to each other by plating, and the second metal layer and the other of the first and second electrodes are connected. And a step of performing .

本発明によればまた、上記のいずれかの製造方法により得られた配線板上に更にビルドアップ層を形成することによりビルドアップ配線板を得ることができる。   According to the present invention, a build-up wiring board can be obtained by further forming a build-up layer on the wiring board obtained by any one of the above-described manufacturing methods.

本発明によれば更に、上記配線板の製造方法により、コンデンサを封止した配線板を内層回路基板として複数枚用い、これら複数枚の内層回路基板を、第3の絶縁性熱硬化樹脂を組み合わせて加熱加圧成型することにより多層積層板を製造し、該多層積層板にスルーホールを形成すると共にめっきを施すことにより高周波回路のデカップリングに十分な大容量、例えば100μF〜100nF程度の静電容量を有する多層回路基板を得ることができる。   Further, according to the present invention, by the method for manufacturing a wiring board, a plurality of wiring boards sealed with capacitors are used as inner circuit boards, and the plurality of inner circuit boards are combined with a third insulating thermosetting resin. A multilayer laminate is manufactured by heat and pressure molding, and through-holes are formed in the multilayer laminate and plating is applied to provide a large capacity sufficient for decoupling of a high frequency circuit, for example, an electrostatic capacity of about 100 μF to 100 nF. A multilayer circuit board having a capacitance can be obtained.

本発明による製造方法では、チップコンデンサ等の電子部品を封止するに際し、電子部品は絶縁性樹脂基板上に載せるだけで良いので、無理な力が加わることが無く、従って電子部品の破損を確実に防止できる。   In the manufacturing method according to the present invention, when sealing an electronic component such as a chip capacitor, it is only necessary to place the electronic component on an insulating resin substrate. Can be prevented.

本発明によればまた、任意の位置に大容量のコンデンサ又は複数個のコンデンサを内蔵できることにより、大容量の静電容量を有する配線板を得ることができる。   According to the present invention, a large capacity capacitor or a plurality of capacitors can be built in an arbitrary position, whereby a wiring board having a large capacity can be obtained.

コンデンサを内蔵した配線板を用いて高周波用配線板を製造することにより、高周波用配線板に表面実装されたCPUのようなICチップと高周波用配線板内に内蔵されたコンデンサとは両面においてビアホールを介して接続されるため、最短の距離で接続できる。これにより、電源からICチップへの瞬時の電圧補完が可能となり、CPU駆動電圧を安定させることができる。   By manufacturing a high-frequency wiring board using a wiring board with a built-in capacitor, an IC chip such as a CPU mounted on the surface of the high-frequency wiring board and a capacitor built in the high-frequency wiring board have via holes on both sides. Since it is connected via, it can be connected at the shortest distance. As a result, instantaneous voltage supplement from the power source to the IC chip is possible, and the CPU drive voltage can be stabilized.

また、加熱・加圧により表面が平坦面となったコンデンサ等の電子部品内蔵基板とすることができるため、この基板上に積層を行う場合であっても凹凸に起因する配線の切断等の不良発生は生じない。   In addition, because it can be a substrate with built-in electronic parts such as capacitors whose surface is flattened by heating and pressurization, even when laminating on this substrate, defects such as wiring cuts caused by unevenness Occurrence does not occur.

コンデンサを内蔵した配線の表裏に、それぞれ電源層とグランド層を形成することにより、配線長が短くなり配線のループインダクタンスが低減する。   By forming the power supply layer and the ground layer on the front and back sides of the wiring containing the capacitor, the wiring length is shortened and the loop inductance of the wiring is reduced.

本発明によれば更に、コンデンサを封止した配線板を内層回路基板として複数枚用い、これら複数枚の内層回路基板を組み合わせて多層積層板とすることにより高周波回路のデカップリングに十分な大容量、例えば100μF〜100nF程度の静電容量を有する多層回路基板を得ることができる。   Furthermore, according to the present invention, a plurality of wiring boards encapsulating capacitors are used as inner layer circuit boards, and a plurality of inner layer circuit boards are combined to form a multilayer laminated board, so that the capacity is sufficient for high frequency circuit decoupling. For example, a multilayer circuit board having a capacitance of about 100 μF to 100 nF can be obtained.

(実施例1)
図1を参照して、本発明による配線板の製造方法の第1の実施例について説明する。図1(a)に示すように、絶縁性樹脂層11の片面に金属層(第1の金属層)12を有する絶縁性樹脂板(片面板)10を用意する。絶縁性樹脂板の材料としては、例えばエポキシ樹脂を用いた日立化成(株)製(商品名「679F材」)のものが知られているが、これに限定されるものではない。続いて、絶縁性樹脂板10に貫通穴が位置決め穴10aとして形成される(図1(b))。この位置決め穴10aは、後で説明されるように、コンデンサ内蔵後の内蔵位置を判別できるようにするために設けられる。位置決め穴10aは、マウンターを使用する場合には基板1枚につき最低2個、精度向上のためには3個以上が設けられる。
Example 1
With reference to FIG. 1, a first embodiment of a method of manufacturing a wiring board according to the present invention will be described. As shown in FIG. 1A, an insulating resin plate (single side plate) 10 having a metal layer (first metal layer) 12 on one side of the insulating resin layer 11 is prepared. As a material for the insulating resin plate, for example, a material manufactured by Hitachi Chemical Co., Ltd. (trade name “679F material”) using an epoxy resin is known, but is not limited thereto. Subsequently, a through hole is formed as a positioning hole 10a in the insulating resin plate 10 (FIG. 1B). As will be described later, the positioning hole 10a is provided so that the built-in position after the built-in capacitor can be determined. When using a mounter, at least two positioning holes 10a are provided for each substrate, and three or more positioning holes 10a are provided for improving accuracy.

次に、図1(c)に示すように、絶縁性樹脂層11の片面上の任意の位置に、コンデンサ部品20を接着性樹脂を用いて実装する。この実装は、マウンターで行うことができ、その際に位置決め穴10aから見たコンデンサ部品20の位置が撮像手段等により観測されて記憶され、後述されるビアホール等の形成に際して位置判別のために利用される。コンデンサ部品20は、上下に銅めっきを施してなる電極を有する周知のチップコンデンサ、あるいは内蔵用に開発されたコンデンサのいずれでも良い。ここでは、コンデンサ部品20として、中心に誘電体21を有し、その上下両面に電極22、23を有する大容量のチップコンデンサを用いており、以下ではチップコンデンサと呼ぶ。   Next, as illustrated in FIG. 1C, the capacitor component 20 is mounted using an adhesive resin at an arbitrary position on one side of the insulating resin layer 11. This mounting can be performed by a mounter, and at this time, the position of the capacitor component 20 viewed from the positioning hole 10a is observed and stored by an imaging means or the like, and is used for position determination when forming a via hole or the like described later. Is done. Capacitor component 20 may be either a well-known chip capacitor having electrodes formed by copper plating on the upper and lower sides, or a capacitor developed for internal use. Here, a large-capacity chip capacitor having a dielectric 21 at the center and electrodes 22 and 23 on the upper and lower surfaces is used as the capacitor component 20, and is hereinafter referred to as a chip capacitor.

次に、予め部品実装位置、つまりチップコンデンサ20の実装位置に対応する箇所にチップコンデンサ20の大きさに合わせて穴あるいは切り欠きをあけた支持体を有する未硬化状態(Bステージ)の絶縁性熱硬化樹脂(第1の絶縁性熱硬化樹脂)(以下、プリプレグと呼ぶ)30と、蓋材として穴等をあけていないBステージの絶縁性熱硬化樹脂(第2の絶縁性熱硬化樹脂)40とを、チップコンデンサ20を実装した絶縁性樹脂板10に組み合わせ(図1(d))、加熱加圧成型することにより、チップコンデンサ20を封止した銅張積層板50−1を得る(図1(e))。つまり、加熱加圧成型の結果、チップコンデンサ20の周囲及び位置決め穴10aに溶融樹脂が充填され、固化する。これにより、チップコンデンサ20は絶縁性樹脂板10及び絶縁性熱硬化樹脂30、40で空隙の無い状態に封止されると共に、銅張積層板50−1における封止部の表面が平滑になる。なお、絶縁性熱硬化樹脂40の片面、ここでは上面には金属層(第2の金属層)41が形成されている。また、絶縁性熱硬化樹脂30、40は同じ材料であることが好ましいが、異なる材料でも良い。   Next, the insulation in an uncured state (B stage) having a support body in which holes or notches are formed in advance in accordance with the size of the chip capacitor 20 at a part mounting position, that is, a position corresponding to the mounting position of the chip capacitor 20 Thermosetting resin (first insulating thermosetting resin) (hereinafter referred to as prepreg) 30 and B-stage insulating thermosetting resin (second insulating thermosetting resin) with no holes or the like as a lid material 40 is combined with the insulating resin plate 10 on which the chip capacitor 20 is mounted (FIG. 1D), and heat-press molding is performed to obtain a copper-clad laminate 50-1 in which the chip capacitor 20 is sealed ( FIG. 1 (e)). That is, as a result of heat and pressure molding, the periphery of the chip capacitor 20 and the positioning hole 10a are filled with the molten resin and solidified. Thereby, the chip capacitor 20 is sealed with the insulating resin plate 10 and the insulating thermosetting resins 30 and 40 so that there is no gap, and the surface of the sealing portion in the copper-clad laminate 50-1 becomes smooth. . A metal layer (second metal layer) 41 is formed on one surface of the insulating thermosetting resin 40, here the upper surface. The insulating thermosetting resins 30 and 40 are preferably the same material, but may be different materials.

次に、図1(f)に示すように、チップコンデンサ20を内蔵した銅張積層板50−1において、チップコンデンサ20の電極22、23に対応する位置に、それぞれレーザーにてビアホール50aを形成する。このビアホール加工に際し、位置決め穴10aの箇所が基準位置として利用される。   Next, as shown in FIG. 1 (f), via holes 50 a are formed by laser at positions corresponding to the electrodes 22 and 23 of the chip capacitor 20 in the copper clad laminate 50-1 incorporating the chip capacitor 20. To do. In this via hole processing, the location of the positioning hole 10a is used as a reference position.

続いて、図1(g)に示すように、ビアホール50a部分にそれぞれ金属めっき50bを施して、チップコンデンサ20の電極22、23と表裏の金属層12、41とをそれぞれ接続することにより大容量の静電容量を有する回路基板50を得る。   Subsequently, as shown in FIG. 1 (g), the metal plating 50b is applied to the via hole 50a, and the electrodes 22 and 23 of the chip capacitor 20 are connected to the metal layers 12 and 41 on the front and back sides, respectively. The circuit board 50 having the electrostatic capacity is obtained.

上記のようにして、大容量の静電容量を有する回路基板50を用いて、公知の工法でスルーホール形成及び回路形成を行うことにより、高周波用の回路基板として適用する場合に、デカップリングに十分な大容量の静電容量を有する回路基板を得ることができる。   As described above, when the circuit board 50 having a large capacitance is used to form a through hole and a circuit by a known method, the circuit board 50 can be used for decoupling when applied as a high frequency circuit board. A circuit board having a sufficiently large capacitance can be obtained.

更に、図1(h)に示されるように、大容量の静電容量を有する回路基板50上に公知の工法でビルドアップ層を形成することにより、高周波回路におけるデカップリングに十分な静電容量を有するビルドアップ基板60を得ることができる。   Furthermore, as shown in FIG. 1 (h), by forming a build-up layer on a circuit board 50 having a large capacitance by a known method, a capacitance sufficient for decoupling in a high-frequency circuit. Can be obtained.

図2には上記のようにして大容量のコンデンサ20を内蔵した回路基板50を用いた6層板ベースの4回ビルドアップ配線板の例を示し、図3には大容量のコンデンサ20を内蔵した回路基板50を用いた6層板の例を示す。   FIG. 2 shows an example of a six-layer board-based four-time build-up wiring board using the circuit board 50 having the large-capacitance capacitor 20 built in as described above, and FIG. An example of a six-layer board using the circuit board 50 is shown.

(実施例2)
次に、本発明の第2の実施例について説明する。この第2の実施例では、まず大容量のチップコンデンサを封止した配線板を用いて前述したように表裏両面にパターンが形成された内層回路基板を形成する。続いて、この内層回路基板を複数枚用い、これら複数枚の内層回路基板を、Bステージの絶縁性熱硬化樹脂を組み合わせて加熱加圧成型することにより大容量の静電容量を有する多層積層板を製造する。更に、この多層積層板に公知の方法でスルーホールを形成すると共にめっきを施して所望の回路を形成することにより高周波回路のデカップリングに十分な大容量、例えば100μF〜100nF程度の静電容量を有する多層回路基板を得ることができる。
(Example 2)
Next, a second embodiment of the present invention will be described. In the second embodiment, first, an inner layer circuit board having patterns formed on both front and back surfaces is formed using a wiring board encapsulating a large-capacity chip capacitor as described above. Subsequently, a multilayer laminated board having a large capacitance by using a plurality of the inner layer circuit boards, and heat-pressing the plurality of inner layer circuit boards in combination with the insulating thermosetting resin of the B stage. Manufacturing. In addition, through holes are formed in this multilayer laminate by a known method and plating is performed to form a desired circuit, thereby providing a large capacity sufficient for high frequency circuit decoupling, for example, a capacitance of about 100 μF to 100 nF. A multilayer circuit board having the same can be obtained.

以上、本発明の実施例を電子部品としてコンデンサを封止する場合について2つの例について説明したが、本発明においては封止される部品はチップコンデンサに限らず、他のコンデンサ部品、あるいはまたコンデンサ以外の部品でも良いことは言うまでも無い。また、絶縁性熱硬化樹脂としては、エポキシ樹脂、BTレジン、エポキシアクリレート樹脂、フェノール樹脂、ポリイミド樹脂、ウレタンアクリレート樹脂、ポリエステル樹脂、BCB(Benzocyclobutene)、PBO(Polybenzooxazole)等があげられ、特にエポキシ樹脂、BTレジンが好ましいと言えるが、これらに限定されるものではない。   As described above, two examples of the case of sealing a capacitor as an electronic component according to an embodiment of the present invention have been described. However, in the present invention, a component to be sealed is not limited to a chip capacitor, but other capacitor components or capacitors. Needless to say, other parts may be used. Examples of the insulating thermosetting resin include epoxy resins, BT resins, epoxy acrylate resins, phenol resins, polyimide resins, urethane acrylate resins, polyester resins, BCB (Benzocyclobutene), PBO (Polybenzoxole), and particularly epoxy resins. BT resin is preferable, but is not limited thereto.

本発明による配線板は、電子部品を封止する必要のある配線板の製造全般に適用可能であり、特に電子部品としてコンデンサを封止した場合には高周波回路への適用に優れている。   The wiring board according to the present invention can be applied to the general production of wiring boards that need to seal electronic components, and is particularly excellent in application to high-frequency circuits when a capacitor is sealed as an electronic component.

本発明による配線板の製造方法の第1の実施例を工程順に示した断面図である。It is sectional drawing which showed the 1st Example of the manufacturing method of the wiring board by this invention to process order. 図1に示された製造方法により得られた、大容量のコンデンサを内蔵した回路基板を用いた6層板ベースの4回ビルドアップ配線板の例を示す。An example of a six-layer board-based four-time build-up wiring board using a circuit board with a built-in large-capacitance capacitor obtained by the manufacturing method shown in FIG. 1 is shown. 図1に示された製造方法により得られた、大容量のコンデンサを内蔵した回路基板を用いた6層板の例を示す。An example of a 6-layer board obtained by the manufacturing method shown in FIG. 1 and using a circuit board incorporating a large-capacitance capacitor is shown.

符号の説明Explanation of symbols

10 絶縁性樹脂板
11 絶縁性樹脂層
12、41 金属層
20 チップコンデンサ(コンデンサ部品)
21 誘電体
22、23 電極
30、40 絶縁性熱硬化樹脂
50 回路基板
50−1 銅張積層板
60 ビルドアップ基板
10 Insulating resin plate 11 Insulating resin layer 12, 41 Metal layer 20 Chip capacitor (capacitor component)
21 Dielectric 22, 23 Electrode 30, 40 Insulating thermosetting resin 50 Circuit board 50-1 Copper-clad laminate 60 Build-up board

Claims (2)

電子部品を内蔵する配線板の製造方法において、
電子部品が第1、第2の電極を有するコンデンサであり、
他面側に第1の金属層を有する絶縁性樹脂板に、封止後の電子部品の位置を判別するために、前記第1の金属層及び当該絶縁性樹脂板の予め定められた位置にこれらを貫通する少なくとも1つの位置決め穴を形成する工程と、
前記絶縁性樹脂板の一面上に少なくとも1つの前記電子部品を載置し、その際に位置決め穴から見た電子部品の位置を撮像手段により観測し記憶する工程と、
前記電子部品の実装位置に対応する箇所に該電子部品の大きさに合わせて穴あるいは切り欠きをあけた第1の絶縁性熱硬化樹脂と該第1の絶縁性熱硬化樹脂の上面側をカバーし得る上面側に第2の金属層を有する第2の絶縁性熱硬化樹脂とを、前記電子部品を載置した前記絶縁性樹脂板に組み合わせて加熱加圧成型を行う工程とを含むことにより、前記電子部品を前記絶縁性樹脂板及び前記第1、第2の絶縁性熱硬化樹脂で空隙の無い状態に封止すると共に、前記位置決め穴を前記加熱加圧成型工程において硬化した前記第1の絶縁性熱硬化樹脂により塞ぐことで封止部の表面が平滑になるようにし
更に、前記加熱加圧成型工程の後に、前記記憶する工程において記憶されたデータにより、前記位置決め穴を基準位置として前記第1の金属層及び前記絶縁性樹脂板に前記第1、第2の電極の一方に至るビアホールを形成すると共に、前記第2の金属層及び硬化した前記第2の絶縁性熱硬化樹脂に前記第1、第2の電極の他方に至るビアホールを形成する工程と、
形成されたビアホールにそれぞれめっきを施して前記第1の金属層と前記第1、第2の電極の一方とを接続すると共に、前記第2の金属層と前記第1、第2の電極の他方とを接続する工程とを含むことを特徴とする電子部品を内蔵する配線板の製造方法。
In a method for manufacturing a wiring board incorporating an electronic component,
The electronic component is a capacitor having first and second electrodes;
In order to determine the position of the electronic component after sealing on the insulating resin plate having the first metal layer on the other surface side, the first metal layer and the insulating resin plate are placed at predetermined positions. Forming at least one positioning hole therethrough;
Placing at least one electronic component on one surface of the insulating resin plate, and observing and storing the position of the electronic component viewed from the positioning hole at that time by an imaging means ;
Covering a first insulating thermosetting resin having a hole or notch in accordance with the size of the electronic component at a position corresponding to the mounting position of the electronic component, and an upper surface side of the first insulating thermosetting resin A step of performing heat and pressure molding by combining a second insulating thermosetting resin having a second metal layer on the upper surface side that can be combined with the insulating resin plate on which the electronic component is placed. The electronic component is sealed with the insulating resin plate and the first and second insulating thermosetting resins so that there is no gap, and the positioning hole is cured in the heating and pressing molding process. surface of the sealing portion by closing the insulating thermosetting resin is made to be smooth,
Further, after the heating and pressing molding process, the first and second electrodes are formed on the first metal layer and the insulating resin plate with the positioning hole as a reference position based on the data stored in the storing process. Forming a via hole reaching one of the first and second electrodes, and forming a via hole reaching the other of the first and second electrodes in the second metal layer and the cured second insulating thermosetting resin;
Each of the formed via holes is plated to connect the first metal layer and one of the first and second electrodes, and the second metal layer and the other of the first and second electrodes. A method of manufacturing a wiring board containing an electronic component.
請求項1の製造方法により得られた配線板上に更にビルドアップ層を形成することによりビルドアップ配線板を得ることを特徴とする配線板の製造方法。 A method for manufacturing a wiring board, wherein a build-up wiring board is obtained by further forming a build-up layer on the wiring board obtained by the manufacturing method according to claim 1 .
JP2003329343A 2003-09-22 2003-09-22 Wiring board manufacturing method Expired - Lifetime JP4292397B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003329343A JP4292397B2 (en) 2003-09-22 2003-09-22 Wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003329343A JP4292397B2 (en) 2003-09-22 2003-09-22 Wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JP2005101021A JP2005101021A (en) 2005-04-14
JP4292397B2 true JP4292397B2 (en) 2009-07-08

Family

ID=34458603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003329343A Expired - Lifetime JP4292397B2 (en) 2003-09-22 2003-09-22 Wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JP4292397B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008251792A (en) * 2007-03-30 2008-10-16 Nec Corp Capacitor mounting method, and printed circuit board
JP5354078B2 (en) * 2012-09-18 2013-11-27 大日本印刷株式会社 Manufacturing method of component built-in wiring board, component built-in wiring board
JP6469010B2 (en) * 2014-09-01 2019-02-13 三井金属鉱業株式会社 LAMINATE FOR PRINTED WIRING BOARD MANUFACTURING, ITS MANUFACTURING METHOD, AND PRINTED WIRING BOARD MANUFACTURING METHOD

Also Published As

Publication number Publication date
JP2005101021A (en) 2005-04-14

Similar Documents

Publication Publication Date Title
KR100965339B1 (en) Printed circuit board with electronic components embedded therein and method for fabricating the same
JP4192657B2 (en) Manufacturing method of build-up multilayer wiring board with built-in chip parts
JP2009194382A (en) Production process of printed wiring board
WO2001045478A1 (en) Multilayered printed wiring board and production method therefor
JP4287733B2 (en) Multi-layer printed wiring board with built-in electronic components
JP6795137B2 (en) Manufacturing method of printed circuit board with built-in electronic elements
JP2001053447A (en) Multilayer wiring board with built-in part and manufacturing method thereof
JP2006303202A (en) Printed board with built-in component and manufacturing method thereof
KR100747022B1 (en) Imbedded circuit board and fabricating method therefore
JP3492467B2 (en) Single-sided circuit board for multilayer printed wiring board, multilayer printed wiring board and method of manufacturing the same
JP3324437B2 (en) Manufacturing method of multilayer printed wiring board
KR20160019297A (en) Printed circuit board and manufacturing method thereof
WO2014125567A1 (en) Substrate with built-in component, and manufacturing method for same
JP4717316B2 (en) Component built-in wiring board, method of manufacturing component built-in wiring board
KR100536315B1 (en) Semiconductor packaging substrate and manufacturing method thereof
JP2004349357A (en) Method for manufacturing multilayer printed wiring board
JP4292397B2 (en) Wiring board manufacturing method
JP2006165242A (en) Printed-wiring board and its manufacturing method
JP5317491B2 (en) Method for manufacturing printed wiring board
JP2005302991A (en) Manufacturing method of multi-layered wiring substrate
KR101055455B1 (en) Carrier member for substrate manufacturing and method for manufacturing substrate using same
JP3253886B2 (en) Single-sided circuit board for multilayer printed wiring board, method for manufacturing the same, and multilayer printed wiring board
JP4451238B2 (en) Manufacturing method of component-embedded substrate and component-embedded substrate
KR101436827B1 (en) Printed circuit board and manufacturing method thereof
CN111629513B (en) Multi-layer circuit board structure with through hole and blind hole and its making method

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051027

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080903

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081021

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090311

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090324

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140417

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350