JPH04215498A - Manufacture of multilayer circuit board - Google Patents
Manufacture of multilayer circuit boardInfo
- Publication number
- JPH04215498A JPH04215498A JP40211090A JP40211090A JPH04215498A JP H04215498 A JPH04215498 A JP H04215498A JP 40211090 A JP40211090 A JP 40211090A JP 40211090 A JP40211090 A JP 40211090A JP H04215498 A JPH04215498 A JP H04215498A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- resin
- multilayer
- inner layer
- layer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 29
- 239000011347 resin Substances 0.000 claims abstract description 29
- 239000011888 foil Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 238000000465 moulding Methods 0.000 claims description 12
- 239000002648 laminated material Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract description 2
- 238000005476 soldering Methods 0.000 abstract description 2
- 239000003822 epoxy resin Substances 0.000 description 8
- 229920000647 polyepoxide Polymers 0.000 description 8
- 238000007747 plating Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 208000002352 blister Diseases 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 235000013405 beer Nutrition 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、インナービアホールを
形成した多層回路板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer circuit board having inner via holes formed therein.
【０００２】0002
【従来の技術】近年、プリント回路板について配線の高
密度化、高性能化等の要求が強くなっており、回路の多
層化が進んでいる。このように回路の多層化が進むと、
各層間の回路の接続は回路板の表裏に貫通するスルーホ
ールだけでは確保することができず、インナービアホー
ルによっても接続をおこなう必要がある。2. Description of the Related Art In recent years, there has been a strong demand for higher wiring density and higher performance for printed circuit boards, and circuits are becoming more multi-layered. As circuits become more multilayered,
The circuit connection between each layer cannot be ensured only by through holes penetrating the front and back of the circuit board, but also needs to be connected by inner via holes.
【０００３】図３は多層回路板Ａの一例を示すものであ
り、多層回路板Ａの表裏に貫通するスルーホールＢを設
けると共に内層ＣにインナービアホールＤを設け、スル
ーホールＢの内周に設けたメッキ層Ｇで外層Ｅ及び一部
の内層Ｃに形成した回路Ｆを電気的に導通接続し、また
インナービアホールＤの内周のメッキ層Ｈでこのインナ
ービアホールＤを設けた内層Ｃに形成した回路Ｆ同士を
導通接続するようにしてある。FIG. 3 shows an example of a multilayer circuit board A, in which a through hole B penetrating the front and back sides of the multilayer circuit board A is provided, an inner via hole D is provided in an inner layer C, and an inner via hole D is provided on the inner periphery of the through hole B. A plating layer G formed on the outer layer E and a part of the inner layer C was electrically connected to the circuit F, and a plating layer H on the inner periphery of the inner via hole D was formed on the inner layer C in which the inner via hole D was provided. The circuits F are electrically connected to each other.
【０００４】そして上記のようなインナービアホールを
有する多層回路板の製造は、ビアホール（スルーホール
と称されることもある）を表裏に貫通させて設けた内層
回路板にプリプレグを介して他の内層回路板や外層回路
板、金属箔等の積層材を重ね、これを加熱加圧して多層
成形することによっておこなうことができる。[0004] In manufacturing a multilayer circuit board having inner via holes as described above, an inner layer circuit board having via holes (sometimes called through holes) penetrating the front and back sides is connected to other inner layers via prepreg. This can be done by stacking laminated materials such as circuit boards, outer layer circuit boards, metal foils, etc., and heating and pressurizing them to form multilayers.
【０００５】[0005]
【発明が解決しようとする課題】しかしこのようにして
多層回路板を製造するにあたって、内層回路板のビアホ
ール内には加熱加圧成形をおこなう際にプリプレグの樹
脂が溶融流動して充填されることになるが、樹脂不足で
ビアホール内に空隙が発生するおそれがある。そしてこ
のように空隙が発生すると完成された多層回路板の耐熱
性等に問題が生じるものである。すなわち、多層回路板
を製造する工程で半田付け等の際に高温（約２６０〜３
００℃）が作用することになるが、多層回路板の内部に
空隙が存在するとこの部分でフクレ等の欠陥が生じるこ
とになるのである。[Problem to be Solved by the Invention] However, when manufacturing a multilayer circuit board in this manner, prepreg resin melts and flows and fills the via holes of the inner layer circuit board during heating and pressure molding. However, there is a risk that voids may occur within the via hole due to insufficient resin. When such voids occur, problems arise in the heat resistance of the completed multilayer circuit board. In other words, during the process of manufacturing multilayer circuit boards, high temperatures (approximately 260 to 3
00°C), but if there are voids inside the multilayer circuit board, defects such as blisters will occur in these areas.
【０００６】本発明は上記の点に鑑みてなされたもので
あり、耐熱性に優れた多層回路板の製造方法を提供する
ことを目的とするものである。The present invention has been made in view of the above points, and it is an object of the present invention to provide a method for manufacturing a multilayer circuit board with excellent heat resistance.
【０００７】[0007]
【課題を解決するための手段】本発明に係る多層回路板
の製造方法は、ビアホール１を設けた内層回路板２にプ
リプレグ３を介して他の内層回路板や外層回路板、金属
箔等の積層材４を重ね、これを加熱加圧して多層成形す
ることによって多層回路板を製造するにあたって、上記
内層回路板２のビアホール１内を樹脂５で埋めた後に多
層成形をおこなうことを特徴とするものである。[Means for Solving the Problems] The method for manufacturing a multilayer circuit board according to the present invention is to attach other inner layer circuit boards, outer layer circuit boards, metal foils, etc. to an inner layer circuit board 2 provided with via holes 1 via a prepreg 3. In manufacturing a multilayer circuit board by stacking the laminated materials 4 and heating and pressurizing them to form multilayer molding, the multilayer molding is performed after filling the via holes 1 of the inner layer circuit board 2 with resin 5. It is something.
【０００８】[0008]
【作用】本発明にあっては、内層回路板２のビアホール
１内を樹脂５で埋めた後に多層成形をおこなうようにし
ているために、ビアホール１内は樹脂５で充填されてい
てプリプレグ３の樹脂不足による空隙の発生のおそれが
なくなる。[Function] In the present invention, since multilayer molding is performed after filling the via hole 1 of the inner layer circuit board 2 with the resin 5, the via hole 1 is filled with the resin 5 and the prepreg 3 is There is no possibility of voids occurring due to resin shortage.
【０００９】[0009]
【実施例】以下、本発明を実施例によって詳細に説明す
る。内層回路板２としては常法で作成されたものが用い
られる。すなわち、ガラス基材等にエポキシ樹脂等の熱
硬化性樹脂を含浸乾燥して調製したプリプレグを複数枚
重ねると共にその両側に銅箔等の金属箔を重ねて加熱加
圧成形することによって、金属箔張り積層板を作成し、
この金属箔をエッチング加工等して表裏面に回路１０の
形成をおこなうことによって内層回路板２を作成するこ
とができる。そして本発明ではビアホール１を設けた内
層回路板２を用いる。ビアホール１は内層回路板２の表
裏に貫通するように形成されているものであり、その内
周にはスルーホールメッキ処理によってメッキ層１１を
設けて表裏の回路１０を導通接続するようにしてある。EXAMPLES The present invention will now be explained in detail by way of examples. As the inner layer circuit board 2, one made by a conventional method is used. That is, by stacking multiple sheets of prepreg prepared by impregnating and drying a thermosetting resin such as an epoxy resin on a glass base material, and then layering metal foil such as copper foil on both sides and molding under heat and pressure, metal foil is formed. Create tension laminates,
The inner layer circuit board 2 can be created by etching this metal foil and forming the circuit 10 on the front and back surfaces. In the present invention, an inner layer circuit board 2 provided with via holes 1 is used. The via hole 1 is formed so as to pass through the front and back sides of the inner layer circuit board 2, and a plating layer 11 is provided on the inner periphery by through-hole plating treatment to conductively connect the circuits 10 on the front and back sides. .
【００１０】この内層回路板２を用いて多層回路板を製
造するにあたっては、まず内層回路板２のビアホール１
内を樹脂５で充填する。図１はその一例を示すものであ
り、ビアホール１内に樹脂５を詰め込んで穴埋めするよ
うにしてある。この樹脂５としては例えばＢステージ状
態のエポキシ樹脂などを用いることができる。図２はそ
の他例を示すものであり、粘度の高いエポキシ樹脂等の
樹脂５に内層回路板２をディップして加熱することによ
って、ビアホール１内に樹脂５を充填させると共に内層
回路板２の全体をＢステージ状態の樹脂５で被覆するよ
うにしたものである。これらビアホール１に充填させる
樹脂５としては、内層回路板２や後述の多層成形に用い
るプリプレグ３を構成する樹脂と同種の樹脂、例えば内
層回路板２やプリプレグ３がエポキシ系樹脂で形成され
ている場合は樹脂５もエポキシ系樹脂で形成するのが好
ましい。When manufacturing a multilayer circuit board using this inner layer circuit board 2, first the via holes 1 of the inner layer circuit board 2 are
The inside is filled with resin 5. FIG. 1 shows an example of this, in which a via hole 1 is filled with resin 5 to fill the hole. As this resin 5, for example, an epoxy resin in a B stage state can be used. FIG. 2 shows another example, in which the inner layer circuit board 2 is dipped in a resin 5 such as a highly viscous epoxy resin and heated, thereby filling the via hole 1 with the resin 5 and simultaneously forming the entire inner layer circuit board 2. is coated with resin 5 in a B-stage state. The resin 5 to be filled into these via holes 1 is the same type of resin as the resin constituting the inner layer circuit board 2 and the prepreg 3 used for multilayer molding described later, for example, the inner layer circuit board 2 and the prepreg 3 are made of epoxy resin. In this case, it is preferable that the resin 5 is also formed from an epoxy resin.
【００１１】しかして、上記のようにビアホール１を樹
脂５で充填した内層回路板２を用いて多層回路板を製造
するにあたっては、各内層回路板２の表裏両面に複数枚
のプリプレグ３を重ねると共にこのプリプレグ３を介し
て積層材４を重ねる。プリプレグ３としては、常法で作
成されたもの、例えばガラス基材にエポキシ樹脂等の熱
硬化性樹脂を含浸乾燥して作成されたものを用いること
ができる。また積層材４としては、他の内層回路板や外
層回路板、銅箔等の金属箔などを用いることができる。
そしてこれを加熱加圧して多層積層成形することによっ
て、プリプレグ３によるボンディング層で内層回路板２
に外層材４を積層して多層に回路形成をした多層回路板
を得ることができるものであり、多層回路板の層内には
内層回路板２に設けたビアホール１でインナービアホー
ルが形成されるものである。In manufacturing a multilayer circuit board using the inner layer circuit board 2 in which the via hole 1 is filled with resin 5 as described above, a plurality of sheets of prepreg 3 are stacked on both the front and back surfaces of each inner layer circuit board 2. At the same time, a laminated material 4 is stacked with this prepreg 3 interposed therebetween. As the prepreg 3, one made by a conventional method, for example, one made by impregnating a glass base material with a thermosetting resin such as an epoxy resin and drying it, can be used. Further, as the laminated material 4, other inner layer circuit boards, outer layer circuit boards, metal foils such as copper foils, etc. can be used. Then, by applying heat and pressure to form a multilayer laminate, the inner layer circuit board 2 is formed with a bonding layer made of the prepreg 3.
It is possible to obtain a multilayer circuit board in which circuits are formed in multiple layers by laminating an outer layer material 4 on the outer layer material 4, and inner via holes are formed in the layers of the multilayer circuit board using the via holes 1 provided in the inner layer circuit board 2. It is something.
【００１２】次に、本発明の効果を具体例で実証する。
具体例１ 図１のように、エポキシ樹脂系の内層回路
板２のビアホール１をＢステージ状態のエポキシ樹脂５
を充填して穴埋めし、この内層回路板２の表裏にエポキ
シ樹脂プリプレグ３を介して銅箔４を重ね、１７０℃、
３０ｋｇ／ｃｍ２、９０分の条件で多層成形した。Next, the effects of the present invention will be demonstrated with specific examples. Concrete Example 1 As shown in FIG.
Copper foil 4 was layered on the front and back of this inner layer circuit board 2 via epoxy resin prepreg 3, and heated at 170°C.
Multilayer molding was carried out under the conditions of 30 kg/cm2 and 90 minutes.
【００１３】具体例２ 図２のように、内層回路板２
をエポキシ樹脂ワニスにディップして加熱することによ
って、内層回路板２の表面をＢステージの樹脂５で被覆
すると共にビアホール１に樹脂５を充填して穴埋めをし
、あとは具体例１と同様にして多層成形した。
比較例 樹脂５によるビアホール１の穴埋めをおこな
わずに、あとは具体例１と同様にして多層成形した。Concrete Example 2 As shown in FIG.
By dipping it in epoxy resin varnish and heating it, the surface of the inner layer circuit board 2 is covered with the B-stage resin 5, and the via hole 1 is filled with the resin 5 to fill the hole, and the rest is carried out in the same manner as in Example 1. Multi-layer molding was performed. Comparative Example Multilayer molding was carried out in the same manner as in Example 1, except that the via holes 1 were not filled with resin 5.
【００１４】上記のように多層成形して得た多層回路板
について、オーブン耐熱温度を測定すると共に半田工程
でフクレ不良の発生率を調べた。結果を次表に示す。[0014] Regarding the multilayer circuit board obtained by multilayer molding as described above, the oven heat resistance temperature was measured and the incidence of blistering defects during the soldering process was investigated. The results are shown in the table below.
【００１５】[0015]
【表１】[Table 1]
【００１６】表の具体例１、２の結果にみられるように
、ビアホール１を樹脂５で穴埋めすることによって耐熱
性を高めることができると共にフクレ不良の発生を低減
できることが確認される。As seen in the results of Examples 1 and 2 in the table, it is confirmed that by filling the via hole 1 with the resin 5, heat resistance can be improved and the occurrence of blistering defects can be reduced.
【００１７】[0017]
【発明の効果】上記のように本発明は、内層回路板のビ
アホール内を樹脂で埋めた後に多層成形をおこなうよう
にしたので、ビアホール内は樹脂で充填されていて多層
回路板にプリプレグの樹脂不足による空隙が発生するお
それがないものであり、インナービアホールを有する多
層回路板の耐熱性を高めることができるものである。Effects of the Invention As described above, the present invention performs multilayer molding after filling the via holes of the inner layer circuit board with resin. There is no fear that voids will occur due to shortage, and the heat resistance of a multilayer circuit board having inner via holes can be improved.
【図１】本発明の一実施例の概略断面図である。FIG. 1 is a schematic cross-sectional view of an embodiment of the present invention.
【図２】本発明の他の実施例の概略断面図である。FIG. 2 is a schematic cross-sectional view of another embodiment of the invention.
【図３】多層回路板の断面図である。FIG. 3 is a cross-sectional view of a multilayer circuit board.
１ ビアホール ２ 内層回路板 ３ プリプレグ ４ 積層材 ５ 樹脂 1 Beer hall 2 Inner layer circuit board 3 Prepreg 4 Laminated materials 5 Resin
Claims (1)
プレグを介して他の内層回路板や外層回路板、金属箔等
の積層材を重ね、これを加熱加圧して多層成形すること
によって多層回路板を製造するにあたって、上記内層回
路板のビアホール内を樹脂で埋めた後に多層成形をおこ
なうことを特徴とする多層回路板の製造方法。Claim 1: A multilayer circuit board is produced by stacking other inner layer circuit boards, outer layer circuit boards, metal foil, and other laminated materials on an inner layer circuit board provided with via holes via prepreg, and heating and pressurizing them to form a multilayer. A method for manufacturing a multilayer circuit board, comprising filling the via holes of the inner layer circuit board with resin and then performing multilayer molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40211090A JPH04215498A (en) | 1990-12-14 | 1990-12-14 | Manufacture of multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP40211090A JPH04215498A (en) | 1990-12-14 | 1990-12-14 | Manufacture of multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04215498A true JPH04215498A (en) | 1992-08-06 |
Family
ID=18511924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP40211090A Pending JPH04215498A (en) | 1990-12-14 | 1990-12-14 | Manufacture of multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04215498A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019654A (en) * | 2004-07-05 | 2006-01-19 | Hitachi Chem Co Ltd | Multi-layer wiring board and its manufacturing method |
| JP2006303398A (en) * | 2005-04-18 | 2006-11-02 | Sanei Kagaku Kk | Hole-filled multilayered printed wiring board and manufacturing method thereof, and two-stage curing type resin composition used for manufacturing method thereof |
-
1990
- 1990-12-14 JP JP40211090A patent/JPH04215498A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006019654A (en) * | 2004-07-05 | 2006-01-19 | Hitachi Chem Co Ltd | Multi-layer wiring board and its manufacturing method |
| JP2006303398A (en) * | 2005-04-18 | 2006-11-02 | Sanei Kagaku Kk | Hole-filled multilayered printed wiring board and manufacturing method thereof, and two-stage curing type resin composition used for manufacturing method thereof |
| JP4735815B2 (en) * | 2005-04-18 | 2011-07-27 | 山栄化学株式会社 | Hole-filled multilayer printed wiring board and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990330 |