JPH03172016A - Delay time adding system - Google Patents

Abstract

PURPOSE:To exactly generate delay fluctuation in order by generating a frame leading bit string at delay time intervals calculated by a fixed interval between bits and random delay time to be set for each frame leading bit. CONSTITUTION:When there is the first input F1 bit, an arithmetic unit 1 reads out delay time x1, which random number is set, and loads the delay time as set data to a counter 2. In the counter 2, clocks are counted only for the set value x1 and afterwards, a ripple carry signal RC is outputted and defined as the first delayed F1' bit. Then, the arithmetic unit 1 is triggered and delay time x1 to the next F2 bit is calculated according to the next random set delay time x1 and x2 and fixed time x1, transferred to the counter 2 and set.

Description

[Detailed Description of the Invention] [Summary] Regarding the method of adding random delay times to the first bits of a frame at regular intervals, even if the delay fluctuation width becomes large, the set value is maintained without causing an increase in the hardware size. After adding a random delay time to the first bit of the first frame, the first bit of the next frame is added at the specified interval and the first bit of the frame based on this addition point. A delay time calculated by adding a random delay time is given, and for the first bit of the subsequent frame, a random value is set at the fixed interval and for each first bit of each frame based on the delay time for the first bit of the previous frame. horizontally so that a frame leading bit string is generated at a delay time interval calculated by the delay time.

[Industrial application field]

The present invention relates to a delay time addition method, and particularly to a method for adding random delay times to the first bits of a frame at regular intervals. As shown in Figure 4, when simulating the varying delay times (delay fluctuations) added to each packet in an actual network for packet data (cells) input at regular intervals T. , the frame start bit F. of each packet. F...
By giving a random delay time in the delay time addition processing unit 10, the first bits of frames F. It is necessary to complete ゜...F,'... as Q. [Prior Art] In order to provide such delay fluctuation, as shown in FIG. 5, for example, the delay fluctuation range from the maximum delay time to the minimum delay time is As a result, as shown in FIG. 6, the first bit of each frame F. , F. , F,,... respectively, the delay time X+ + XX + "3 +...
・is added. The structure of a conventional example of such a delay time adding method is shown in FIG.
The calculation algorithm of I is shown in FIG. 8, and the configuration of the shift register section 12 is shown in FIG. 9. In this conventional example, when the first bit of a frame (hereinafter simply referred to as the F bit) is manually input to the arithmetic unit 11, the arithmetic unit I1 stores a delay time with a distribution as shown in FIG. 5 as a random number. , each time each F bint is input manually, the delay time χl+Xf+X3+... is read out and transferred to the shift register section 12 (see FIG. 8). In the noft register section 12, as shown in FIG.
1. shift registers 221-221 by giving
is selected according to the delay time data. Therefore, the delay time according to the data set in the arithmetic unit 1l can be added to the first bit of each frame for each manually inputted F bit. [Problems to be Solved by the Invention] In the case of such a conventional example, as shown in FIG. 6, when the delay time width is larger than the interval T between the input F bits, the F Since the next F bit is input before the bit is output through each of the selected shift registers 22, -227, the number of stages of the shift register is determined by the delay setting data 30 - S. ，
Therefore, there was a problem that the a delay time as set was not added to the previously input F bit. In order to solve this problem, as shown in FIG.
．． The switching unit 31 is switched for each F bit and the switching unit 31 is applied to the variable length soft register units 32 to 327, and the variable length noft register units 32, to 32, are provided with an arithmetic unit 3.
3, the delay time setting data (1) to (nJ) are given respectively, and independent delay times are added to the multiplexer 3.
All you have to do is combine and output with 4. However, in the case of the conventional example shown in Figure 1O, as the delay fluctuation width increases, the number of variable-length shift register sections increases proportionally, resulting in an increase in hardware scale. ．． Therefore, in a method of adding random delay times to the first bits of frames at regular intervals, the present invention adds delay times according to the set value without causing an increase in hardware scale even when the delay fluctuation width becomes large. The purpose is to [Means and effects for solving the problem] In order to solve the above problem, in the delay time addition method according to the present invention, the first
As conceptually shown in the figure, the first frame leading bin l−
F. Add a random delay time XI to For the next frame first bit F, time t1 is reached after a delay time x1 has elapsed from time t6 of the frame first bit F1.
Calculate the delay time X1 based on . Then, for the next frame first bit F,
At the time when delay time x 1 has elapsed tt)j! : Calculate the delay time X2 using the reference. In this way, the delay times X and thereafter are calculated, and these delay times x1 to X,,
]<It can be seen that it is calculated by the following equation. That is, after adding the delay time x1 to the frame first bit F, the 7th frame first bit F! ~F, with a constant interval T and the first bit of each frame F. ．． ．． By generating a frame start bit string at the delay time X, -X, calculated using the random delay time X~x7.1 set for each frame, the frame start bits F1~F. , the first bit of the frame F. is given a delay fluctuation as randomly set for . '~F' can be generated sequentially at time t and ~L7. [Embodiment] FIG. 2 shows an embodiment for realizing the delay time addition method according to the present invention shown in FIG. Delay time X, ~X. randomly set for each F bit. 2 is a calculation device that stores the calculation of equation (2) and executes the calculation of equation (2) as shown in the flowchart of FIG.
This is a counter that outputs . In the operation of this embodiment, first, when there is a first input F1 bit (Fig. 3, S1), the arithmetic unit 1 reads out the delay time X1, which is set as a random number, as shown in Fig. (S2 and S3 in the same format). In counter 2, the set value
, the ripple carry signal RC is output as the first delayed F+' bit, which is generated at time t in FIG. 1 (step S4) and triggers the arithmetic unit l. Then, using the next randomly set delay times X and x8 and the constant time T, the delay time χ1 for the next F bit is calculated according to the formula, and is transferred to the counter 2 and set (same step S5, S6). In this way, calculate the delay time X, ~X7 of formula (■),
The first bit string of the frame with the delay time x1 to x7 is output. [Effects of the Invention] As explained above, according to the delay time adding method according to the present invention, the first bit of each frame is set at a fixed interval between the bits based on the delay time with respect to the first bit of the previous frame. Since the structure is designed to generate the frame start bit string of the delay time interval calculated by the random delay time set for each frame start bit, there is no need for large-scale circuit configuration. Delay fluctuations can be exploited in an orderly and accurate manner.

[Brief explanation of the drawing]

FIG. 1 is a diagram for conceptually explaining the delay time adding method according to the present invention, FIG. 2 is a block diagram showing an embodiment of the delay time adding method according to the present invention, and FIG. Flowcharts of one embodiment of the present invention, FIGS. 4 to 6, are typical of the delay time addition method. !
7 to 10 are block diagrams showing examples of the structure of a conventional delay time adding method. In the figure, F, -F, ... frame first bit, X1 to x7...
・Delay time set for the first bit of each frame, xl-×7... Interval time of the bit string after adding the delay time set for the first bit of each frame, 1... Arithmetic device, 2. ··counter.

Claims (1)

[Claims] Frame start bits (F_1 to F_
In the method of adding a random delay time to n), after adding a random delay time (x_1) by the first frame first bit (F_1), the next frame first bit (F_2) is added based on this addition point. , a delay time (X_1) calculated from the fixed interval (T) and a random delay time (x_2) added to the first bit of the frame (F_2) is given, and the subsequent first bits of the frame (F_2 to F_n ), the delay time (X
_1~X_n_-_1) as a reference, the certain interval (T)
and a random delay time (x_3 to x_n) set for each frame first bit (F_3 to F_n) and a delay time (X_2 to X_n) calculated from the delay time (X_2 to X_n). Addition method.