JPS60369A - Measuring device of pulse width - Google Patents

Abstract

PURPOSE:To measure accurately pulse width at a low frequency by gating and counting the output from a fixed oscillator and its delayed output independently by a pulse signal to be measured. CONSTITUTION:A counting signal from the fixed oscillator 11 is supplied to a gate circuit 12a and also gate circuits 12b-12d through delay circuits 13a-13c. Outputs from the respective gates are supplied to 1/2 counters 15a-16d under the positive status of pulse input signals to be measured which are inputted from an input terminal 14. Respective outputs from the 1/2 counters 15a-16d are inputted to a decision circuit 17, which outputs differences between respective counterd values and reference values successively by using the counted values of the counters 15a, 16a as the reference values. On the other hand, a multiplier 19 multiplies a counted output from a counter 18 by the number 4 of rows of the counter and an arithmetic unit 20 adds or substracts a decided output value from the decision circuit 17 to/from the multiplied output and outputs the measured value of the pulse width.

Description

[Detailed description of the invention] [Technical field of invention] The present invention is based on the improvement of a pulse width measuring device.

[Technical background of the invention and its problems]

Conventionally, a pulse width measuring device 11C configured as shown in FIG. 1 has been used in the general field of electronic equipment including audio equipment. The pulse input signal for measurement supplied from the input terminal 4 is supplied to the gate circuit 2 together with the counting signal from the fixed oscillator 1 using the crystal providence 1 terminal (X-TAL) 71il. ?The count signal is darted at either the positive or negative timing of the pulse force signal, and the second counter circuit 3 counts using the dart output.1.
It is something that

However, the pulse of one sentence like this:;・Hataketo 1
In order to accurately measure the pulse width with a measuring device, it is necessary to make the oscillation frequency of the tel 2 and fixed foot oscillator 1 as high as possible, but there is a certain limit due to the operating frequency of the counter circuit 3. There was a grudge that the resulting pulse width measurement accuracy could not be improved to that extent.

[Purpose of the invention]

So, this departure I! JJ) The present invention has been developed in view of the above points, and the object is to provide an extremely good i4 pulse width measuring device that is improved so as to be able to accurately measure pulse widths at low frequencies.

[Summary of the invention]

That is, the pulse width measuring device according to the present invention includes a fixed oscillator, an appropriate number of delay circuits that delay the output from the fixed oscillator for a predetermined period of time, and an output from the fixed oscillator and the appropriate number of slow death circuits. an appropriate number of dart circuits that individually dart each output of the output signal according to the measured Nof input signal, and an appropriate number of counters that separately count each output of the appropriate number of dart circuits. Determine whether the count output from the counter of river 4 that counts the output through the delay circuit is large or small based on the count output from the counter that counts the output from the fixed oscillator that is not passed through the delay circuit, and calculate the difference. and the number of circuits VC$5.0 for the output from the counter giving the reference count. `` Multiply the number by 11. 11-1 digit n circuit and this multiplication circuit calculates the sum or difference of the output from the 1 judgment circuit with respect to the output C from the arithmetic circuit to J. It is characterized by being prepared.

[Example of the Invention] One embodiment of the invention will be described in detail below with reference to the drawings.

That is, as shown in FIG.
The counting signal from the fixed oscillator 1 using the fixed oscillator 1 is directly supplied to one input end of the first dart circuit 12a, and the counting signal from the fixed oscillator 1 connected in cascade to the output end of the fixed oscillator 11 is 1st to 3rd delay amount 751 J a, No 3
The second to fourth dart circuits 12b serve as counting signals with a predetermined delay amount via the second to fourth dart circuits 12b and 13c, respectively.

12G and 12d are respectively supplied to the other end in a corresponding manner.

Here, the first to fourth dirt circuits 12a and 1
2b, 12c, and 12d are configured such that a pulse input signal to be measured is commonly supplied from the input terminal 9 to the other terminal of each of them, and the pulse input signal is in a positive state. The dart outputs r and FXyJl are respectively supplied to the input terminals of the fourth counters 15a, 15b, 15c, and 15d.

Moreover, each of the above-mentioned counters 15a and 15b.

Each output of 15c and 15d is sent to the fifth to eighth lid counters 16a for comparison of count values.

It is designed to be supplied to each input terminal of x6b, 1ec, and led correspondingly.

Further, each output of the first to fourth and fifth to eighth f counters 15a to 15d, 16a to 16d is 1'1j as f& for the first to eighth inputs p11 of the judgment circuit 17. It is supplied in such a way that it is possible to

That is, this 'l'lJ %z I'', 1jY3 i
y Ll: , 7 counters 15a, 16 of the first and Fi't 5 count the dart output consisting of the target and double old counting signals from the above-mentioned fixed oscillator 11.
Based on the count value by 'nK, (Oshi count 15h for each set of l11.

Each count value of 15b, 15c, 16c, 15d, and 16d is greater than or equal to 1. This is to judge whether the number is smaller than the 1'11 constant tC, and if the number is smaller than the difference between them, -o1, then il.

<'jr
, is what is being said.

Then, only the output of the fifth lid counter 16m is supplied to the counter 18, which outputs the count output sound.
It is set such that i'j-F is supplied T times 1 to 19.

Number of slips of lid counters 15R to 15d, 16s to 16d (
In this case, 4) is multiplied and the calculation power is supplied to the arithmetic circuit 20.

In addition, the above-mentioned ``Usukuchi''& 201 are ``Usukuchi'''W 1
The calculation power is multiplied by g, and the sum formula g ζ of the judgment output value from the judgment circuit 17 takes the difference.

Note that the contents of the first to eighth child counters 15a to J5d and 16a to 16d and the counter 18 are reset by a reset signal supplied via the input terminal 21 after the series of operations in each section as described above is completed. It is cleared and the counting operation is made possible again.

In this case, the counter 1ii14 operates when the pulse input signal to be measured is positive, as described above.

Next, the operation of the pulse width measuring device that is zeroed as described above will be explained based on a timing chart as shown in FIG.

That is, in FIG. 3, (,) is the pulse input signal S to be measured, and (b) 0, the conventional signal t, +, if
4 I...114 - Indicates the dart output for counting by the device, and the total count value of 1b is 10.
vI T , -Jj) Nof Rus Nakabatake 1
0T, Toshide, Rierail, 2), 1 and 883 figure (
c) ~(f) IJ: f(>; i to third; 1
γ extension circuit 13a, 13b, 13cf
3m count signal and count signal gτ passed through fb: '', % (This shows the count dart output.

Then, such a count dirt output is sent to the first to eighth counters 15n to 15d.

16a~16b Saraniu, counter 18 power! Kuntosarete, judgment circuit 11yr, and 411) ke:'F:
li'l il supplied to the arithmetic circuit 20 via FK19
, a predetermined calculation is performed.

In other words, in this case, since the count dart output of the first column shown in FIG. 3(c) is 3, = jf) x ff times it'
The 11-digit calculation output from 3 J 9 is 3X4=12.

Then, from the determination circuit 17, one number 1. The judgment output is 3-3=0 for the counting output 3 in the second column shown in FIG.
The outputs are 2-3=-1 for the counting dart outputs 2 of the third and fourth columns shown in U(eJ, (f)).

As a result, the output from the arithmetic circuit 2o is a x4+
(3-3) + (2-3) + (2-3) = 120-
1-1=10, which is the same as the conventional dart output for counting.

The pulse width that can be requested is T2=4T1 (
However, as shown in the delay time of each delay circuit '1-12'' t3=T, even though the frequency of the dart output for counting used was made sufficiently low, the result was 10T1.
The accuracy is the same as that of the conventional one (in this case, the delay amount h′6
(depending on the accuracy of the delay amount).

In other words, if the dart signal frequency used in this invention is increased to a frequency that can be operated in the past, it is possible to obtain considerably high accuracy that could not be obtained in the past. .

It should be noted that this invention is not limited to the above-mentioned and orally transmitted implementation, and is not limited to only the implementation described in 1.
There is nothing up to ↑15 that allows for various transformations and applications.

For example, as shown in FIG. 2, by increasing the number of MKs and child counters, the accuracy can be further improved.

[Effect of Departure IJ]

Therefore, as detailed above, according to the present invention, it is possible to provide a pulse width n measuring device 1j which is improved to accurately measure the pulse width at low frequencies. .

[Brief explanation of drawings]

Figure 1 shows the conventional system/system 111°4 measurement device i',...
Figure 52 is a Ct configuration explanatory diagram showing an embodiment of the arm Q'i, i t++ measuring device related to this Ell. 1 is a timing chart for explaining the operation of FIG. 2 in comparison with that of FIG. Yanobu circuit, 14.2
1... Input terminal, i5a to 15d, 16a to 16d.
... ÷ counter, 17... profit circuit, 18... counter, 19... multiplication is correction circuit, 20... correction circuit. Patent attorney representing applicant Takehiko Suzue

Claims (1)

[Claims] a fixed oscillator; an appropriate number of delay circuits that delay the output from the fixed oscillator for a predetermined time; A number of dart circuits that perform darts separately, an appropriate number of counters that separately count each output of the appropriate number of dart circuits, and a fixed number of counters that do not pass through the delay circuit among the appropriate number of counters. Determine whether the count output 'f from a counter that counts the output from the oscillator is large or small from another counter that counts the output through the delay circuit as a reference, and output according to the difference. a judgment circuit that is generated, a calculation circuit that multiplies the output from the counter that gives the reference count by a number corresponding to the number of dirt circuits, and a calculation circuit that multiplies the output from the calculation circuit from the judgment circuit. 1. A /f pulse width measuring device, comprising: an arithmetic circuit that calculates the sum or difference of υ2 of outputs.