JPH03166640A - Multi-processor system - Google Patents

Abstract

PURPOSE:To avoid the deadlock state by executing an access to a memory through a local bus on a processor board, in the case a microprocessor executes an access to an address space corresponding to a slot position in which the microprocessor itself is loaded. CONSTITUTION:When an address on an address bus 61a is not that to a device on its own board, an access is requested to the other board by using a system bus 6 as usual. However, when it is that to the device on its own board, the access to the system bus 6 is inhibited, and instead thereof, a chip select signal its outputted to the device (memory 3a) on the own board. In such a way, it is avoided to fall into a deadlock state.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a multiprocessor system that constitutes a control device such as a numerical control device, and particularly relates to a multiprocessor system that has an improved memory sharing function between the processors that make up the system. Regarding the system.

[Conventional technology]

The most common form of multiprocessor system is one in which multiple processor boards are connected together in a system hub.

FIG. 2 is a diagram showing the general structure of a multiprocessor system that constitutes a numerical control device.

The multiprocessor system includes two processor boards 1a and 1b coupled to each other via a system bus 6.
and two servo control boards lc and 1d.

The processor board 1a is equipped with a microprocessor 2as memory lJ3a, a system bus control circuit 4a, a path buffer 5a, and the like. Although various other devices are mounted on the actual board, their description will be omitted for the sake of convenience. The other boards lb, IC and 1d have the same structure as board la.

Such a multiprocessor system is provided with a shared memory for the microprocessors 2a, 2b, 2c, and 2d to exchange data with each other. The shared memory currently in practical use is one in which an independent memory board is connected to the system bus 6 and can be accessed by each microprocessor 2a, 2b, 2c, and 2d using a common address, and a processor board 1a. There is one in which the above memory lJ3a can be accessed also from other microprocessors 2b12C and 2d.

A common memory using on-board memory is advantageous in terms of cost because it eliminates the need for an independent memory board.

On the other hand, those equipped with an independent memory board as shared memory have the disadvantage of being expensive, but since any microprocessor can view the address on the shared memory as the same address, it is easy to develop software. It has the advantage of being very convenient.

That is, in a multiprocessor system, in order to process a plurality of processes simultaneously, a plurality of microprocessors are used to process the plurality of processes in a distributed manner. At this time, data communication between each microprocessor is performed via the shared memory. Therefore, when communicating a batch of data between microprocessors, by providing a shared memory board that has the same address from every microprocessor's point of view, there is no need to copy the data between microprocessors one by one. Data communication can be performed simply by communicating a pointer indicating the location (shared memory address).

[Problem to be solved by the invention]

If similar data communication is attempted in a multiprocessor system that does not have an independent shared memory board, the following problems will occur.

When a microprocessor on a multiprocessor system looks at memory on other processor boards (that is, shared memory), each board appears to be in a different address space.

For example, microprocessor 2a and microprocessor 2
Suppose that the memory 3a is shared by the memory 3a.

The microprocessor 2a can directly access this shared memory 3a as a local device on its own processor board 1a.

In other words, the shared memory 3 seen from the microprocessor 2a
a is in the local address space.

However, when the microprocessor 2b accesses the shared memory 3a, it must go through the system bus 6, so the microprocessor 2b accesses the shared memory 3a through an address space different from that of the local device. There is a need. That is, shared memory 3
The address a is recognized as a different address by the microprocessor 2a and the microprocessor 2b.

Therefore, in such a multiprocessor system, even if data is passed using a pointer as described above, the pointer cannot be used directly and the address must be converted once.

The present invention has been made in view of the above points,
To provide a multiprocessor system that can perform data communication between microprocessors simply by communicating pointers indicating data locations (shared memory addresses) without having an independent shared memory board. purpose.

[Working hard to solve the problem]

In order to solve the above problems, the present invention provides a multiprocessor system in which a plurality of processor boards each equipped with a microprocessor are connected via a system bus, in which all the microprocessors constituting the multiprocessor system are installed on any processor board. means for mapping an address space corresponding to a slot position in which the microprocessor board is held onto the memory so that the memory of the microprocessor board can be directly accessed using a common address; A multiprocessor system is provided, wherein means for accessing the memory via a local bus on the processor board when the address space is accessed is provided on each of the processor boards.

[Effect]

In order to enable all microprocessors that make up a multiprocessor system to directly access the memory on any processor board using a common address, the address space corresponding to the slot location held on the processor board is mapped to the memory. From the microprocessor's point of view, this is equivalent to having a shared memory at the same address, and there is no need to copy data between microprocessors one by one. Data communication can be performed simply by

However, when a microprocessor accesses the address space corresponding to the slot location in which it is installed, that address space is not a local address space of the board in which the microprocessor is installed, so it is accessed via the system bus. You will be requesting access for yourself. Therefore, in such cases, memory is accessed via the local bus on the processor board. This makes it possible to program the memory so that it always exists in a fixed address space, no matter which memory is viewed from which microprocessor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

The numerical control device decodes the machining program, calculates movement command data for each axis of the machine tool, and controls multiple servo motors simultaneously. When the number of servo motors, that is, the number of control axes is small, data processing and control of the servo motors can be processed by one microprocessor, so there is no need to use a multiprocessor system. However, as the number of control axes of a machine tool increases, the amount of data processed by the microprocessor also increases. Therefore, it is possible to make the numerical control device a multiprocessor system and share the processes related to servo motor control with another microprocessor. I'm dealing with it.

The numerical control device of this embodiment has two processor boards 1a and 1b and two servo control boards I as shown in FIG.
C and 1d. There is no difference in hardware between the processor boards 1a and 1b, and between the servo control boards IC and ld, and they are composed of the same board.

In the multiprocessor system that makes up this numerical control device, there is no dedicated shared memory board, so
Memories 3a, 3b, 3c and 3d on each board are used as shared memory. Therefore, the microprocessor 2a on the processor board 1a can access the memo U 3 b on the processor board 1b. Similarly, the microprocessor 2b can access the memory 3a on the processor board 1a.

Furthermore, microprocessors 2a, 2b, 2c and 2d
are their own white boards la, lb, 1c and ld
In addition to the address space for accessing the devices above, other boards la, 1b% connected to the system bus 6
Devices on lc and ld (memories 3a, 3b, 3c
and 3d, etc.).

In this example, the total address space is 16M bytes (
b y t e) and address 00 0 therein.
0 0 0 H to address 7 F F F F F
Address space up to H (hereinafter referred to as [000000
H. ．． 7FFFFFH]) is the address space for accessing devices on its own board, and the address space co o o o00H within this is
．． ．． OOFFFFH] is allocated as the memory address space.

Then, the remaining address space [8
0 0 0 0 0H. ．． FFFFFFH is allocated as an address space for accessing devices on the system bus 6.

Furthermore, this address space [800000H. ．． FFF
FFFH] on boards 1a, 1b% 1c and ld
Each board is divided into an IM byte address space and assigned to each board. Specifically, for the processor board 1a held in the first slot, the address space [800000H. ．． 8FFFFFH], and for the processor board 1b held in the second slot, the address space [90 0 0 0 0H. ．． 9FFF
FFH] is assigned. Similarly, the servo control board IC has an address space [A0 0 0 0 0H. ．． A
FFFFFH], and the servo control board 1d has an address space [B0 0 0 0 0H. ．． BFFFFFH are respectively allocated.

FIG. 1 is a diagram showing a processor board of a multiprocessor system that includes a numerical control device according to an embodiment of the present invention. This diagram shows only the details of the processor board 1a in Figure 2, but the configurations of the processor board lb, servo control boards 1c and 1d are also roughly the same as in Figure 1, so the detailed diagrams are omitted, and the reference numbers are followed by The explanation will be given with symbols bSc and d. Furthermore, in the description of this embodiment, signals marked with * indicate active low.

The microprocessor 2a has a 24-bit address (AO
O-23) and 16-bit data (D0 0-1
5), and are connected to an address bus 61a and a data bus 62a, respectively.

Furthermore, the microprocessor 2a outputs a memory read signal *RD and a write signal *WR to the control bus 63a. The microprocessor 2a receives a bus release request signal (
HOLDA), and a terminal HA that outputs an acknowledge signal (HOLDA) to the system bus arbitration control circuit 7a in response to this bus release request signal.

The memory 3a consists of 64K words, and its address address is in the address space [0000000H. ．． 00FFFF
H] range. Memory 3a address AO O-1
5 is connected to the microprocessor 2a via an address bus 61a. A data input/output terminal of the memory 3 is connected to the microprocessor 2a via a data bus 62a, and 16-bit data (DOO-15) is exchanged. Memo IJ 3a read signal terminal *OE
and write signal terminal *WE is control bus 63a
The microprocessor 2a is connected to the microprocessor 2a through the microprocessor 2a, and inputs control signals. A chip select signal is input from the OR circuit 14a to the chip select terminal *CS of the memory 3a.

The path buffer 5a connects each address bus 61a, f-
The system bus 6 is connected to the 9 bus 62a and the control bus 63a.

The decoder 9a is connected to the address bus 61a, and the address on the address bus 61a is set to the address space [0 0 0
0 0 0 0H. ．． 0 0FFFFH], the chip select signal is output to the OR circuit l4a.
and the address space [8000000I{. ,FF
FFFFH], a bus release request signal is output to AND circuits 12a and 13a.

The setting switch 10a is used to recognize the slot number in which the setting switch 10a is held, and the corresponding slot No. 8 is set in advance. Specifically, board 1a
has rl(OOIB)J on board 1b, and r2(0
1 0B) J, board 1C has r3 (0 1 1
B) J is set, and the slot number r4 (1 0 0B) J is set on board ld.

Comparator lla outputs the slot number of setting switch 10a and address A2 0-2 on address bus 62a.
2, and if both values match, a match signal is output to AND circuits 12a and 13a.

The AND circuit 12a takes the output of the comparator lla into its L active input terminal and the output of the decoder 9a into its H active input terminal, and outputs the AND signal to the system bus arbitration control circuit 7a. The AND circuit 13a receives the outputs of the comparator lla and the decoder 9a into its H active input terminals, and outputs the logical product signal to the OR circuit 14a.

Subsequently, the upper address A20-2 of the address bus 61a
2 and the slot number of the setting switch 10a, the AND circuit 12a outputs an AND signal, and if they are the same, the AND circuit 13a outputs an AND signal.

The system bus arbitration control circuit 7a handles access requests from the microprocessor 2a on board la and other boards lb,
Microprocessor 2b, 2c or 2 on lc or 1d
Arbitrate so that there is no conflict with the access request from d.

Therefore, the upper address A2 0- of the address bus 61a
2 If 2 and the slot number of the setting switch 10a do not match, use another microprocessor 2b, 2c or 2.
It is determined that there is an access request from d, and a bus release request signal is output to the microprocessor 2a.

In response, the microprocessor 2a outputs an acknowledge signal to the system bus arbitration control circuit 7a and releases the exclusive use of the bus.

The system bus timing control circuit 8a is connected to the system bus arbitration control circuit 7a, the path buffer 5a and the control bus 63a, and is connected to the system bus 6 and the local address bus 61a on the processor board 1a.
, f-tabus 62a, and control bus 63a.

Next, the operation of this embodiment will be explained.

For example, the microprocessor 2a on the processor board 1a held in the first slot is at address 90.
When 1000H is accessed, the processor board 1b held in the second slot is made aware by the system bus arbitration control circuit 7b that the access is to a device on its own board 2b.

At this time, since the microprocessor 2b is always operating on the processor board 1b, the system arbitration control circuit 7b releases the bus to the microprocessor 2b in order to arbitrate the conflict with the access request from the microprocessor 2a. Outputs a request signal. In response, the microprocessor 2b outputs an acknowledge signal to the system bus arbitration control circuit 7b to release the exclusive use of the bus.

At this point, the system bus 6 and the local bus of the processor board 1b (address bus 61b1 data bus 62b1)
control bus 63b). Then, the comparator llb receives the slot number of the setting switch 10b and the address A2 0-2 2 on the address bus 62b.
Compare the value with.

As a result, since the two values do not match, the AND circuit 13b outputs an AND signal to the OR circuit 14b. This allows the microprocessor 2a to access the device (memory 3b in this case) on the processor board 1b.

The above address 901000H is the microprocessor 2
b address space [0000000H. ．． 00FFFF
H] corresponds to address address 001000H of memory 3b.

Next, the microprocessor 2b uses this address 9010.
The case of accessing 00H will be explained. In such a case, the decoder 9b1 setting switch 10 of this embodiment
b1 comparator 11b1 AND circuit 12b and 13b
If it does not exist, the following contradiction will occur.

Address 901000H indicates the address of the device (memory 2b) on the processor board 1b on the system bus 6 according to the above definition. Therefore, when microprocessor 2b accesses address 901000H, system bus arbitration control circuit 7b outputs a bus release request signal to itself (microprocessor 2b). That is, the microprocessor 2b requests itself to release the bus. However, since the microprocessor 2b is actually in the middle of executing a bus cycle,
We can't open this up. Therefore, since the microprocessor 2b does not output an acknowledge signal, the bus cycle is never completed, resulting in a deadlock state.

However, according to the configuration of this embodiment, deadlock does not occur in such a case.

In this embodiment, the address on the address bus 62b is decoded by the decoder 9b, and it is determined whether the address is for a device on another boat on the system bus 6 or for a device on the own boat. This is because it has a function to determine whether it is present.

Therefore, when the address on address bus 62b is not for a device on its own boat, it requests access to other boards using system bus 6 as usual. However, if it is for a device on its own board, it prohibits access to system bus 6 and instead outputs a chip select signal to the device (memory 3b) on its own board. .

This avoids the deadlock situation described above.

In this embodiment, from the microprocessor ib to the memory lJ2
Looking at the address of b, it appears as if the address space [0 0
0 0 0 0 0H. ．． 0 0FFFFH]
and address space [9000000H. ．． 90FFFFH
] It will appear that both address spaces exist. However, there is only one memory space, and any address space may be used for access.

On the other hand, when looking at the address of the memory 3b from the other microprocessors 2a, 2c and 2d, the memory 3b is always in the address space [9000000f{. ．． 90FFFFH]
will exist in

Therefore, by adopting the configuration of this embodiment, the memo TJ3b can be used with any microprocessor 2a, 2b,
Even when viewed from 2c and 2d, the address space [9 0 0
0 0 0 0H. ．． 9 0FFFFI-{]
It becomes possible to program as if it exists in .

In addition, each microprocessor 2a, 2b, 2c and 2d
Even when passing data using pointers between
You can now use the pointer directly without having to convert the address one by one.

〔Effect of the invention〕

As explained above, according to the present invention, programs can be executed assuming that all microprocessors are always in the same address space with respect to the memory mounted on any processor board, even without having an independent shared memory board. It is possible to assemble.

In addition, data communication between microprocessors can be performed without converting addresses by simply communicating a pointer indicating the location of data (shared memory address) without having an independent shared memory board. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a processor board of a multiprocessor system comprising a numerical control device, which is an embodiment of the present invention, and FIG. 2 is a diagram showing a schematic structure of a multiprocessor system comprising a numerical control device. It is. la, lb-- Processor board lc, ld-
゛゜ Servo control board 2a, 2b, 2c, 2d Microprocessor 3a, 3b, 3c, 3d Memory 4a, 4b, 4c, 4d System bus control circuit 5a, 5b, 5c, 5d ・Path buffer 6 ・System bus 61a ゜Address bus 62a Data path 63a Control bus 7a ゛゜System bus arbitration control circuit 8a゜゜ System bus timing control circuit 9a Decoder 10a - Setting switch 11a' Comparator 12a, 13a -- AND circuit 1
4 a - OR circuit

Claims (1)

[Claims] (1) In a multiprocessor system in which multiple processor boards equipped with microprocessors are connected via a system bus, all microprocessors composing the multiprocessor system can directly access memory on any processor board using a common address. means for mapping in the memory an address space corresponding to a slot position held by the processor board; and when the microprocessor accesses the address space corresponding to a slot position in which the microprocessor itself is mounted; and means for accessing the memory via a local bus on the processor board, respectively provided on the processor board.