JPH03166639A - Bus control system in microprocessor - Google Patents

Abstract

PURPOSE:To eliminate the need of extending a different bus between other modules by constituting the system so that in the case a microprocessor reads out data from a memory, a bus can be allocated to other module after sending out an address to the bus. CONSTITUTION:A system bus controller 3 turns on a signal line 9 first in order to read out data from a memory 4, allows a microprocessor to receive only an address, informs a fact that desired data is transmitted after being read out, and also, turns on a signal line 6, and outputs a use request of a bus 5 to the microprocessor 2. The microprocessor 2 becomes a data reception waiting state, and also, stops sending out an address to the bus 5, turns on a signal line 7, and permits to use the bus 5 to the system bus controller. The system bus controller 3 uses the bus 5, reads out the contents of the memory 4, and sends out data to a system bus controller 3' through a system bus 100. In such a way, it becomes unnecessary to extend a different bus between other modules.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control system in a microprocessor.

[Prior art]

Conventionally, when a conventional microprocessor is equipped with a bus for reading data from or writing data to memory, when reading data from memory, it sends an address to the bus and, in response, returns the desired data. A bus control method is used in which the bus is occupied until a message is sent. An example of a system configuration using such a conventional microprocessor will be shown, and problems with the conventional microprocessor will be pointed out.

FIG. 2 is a diagram showing an example of a system configuration using a conventional microprocessor, in which 1 and 1' are processors. Processors 1 and 1' are microprocessors 2,
2', system bus controller 3, 3' and memory 4
, 4'.

5 and 5' are buses for microprocessors 2 and 2';
System bus controller 3, 3' and memory 4, 4'
is connected to. 6, 6' are buses 5, 6, 6' from system bus controllers 3, 3' to microprocessors 2, 2'
The signal line 7, 7' requires the microprocessor 2, 2' to connect the bus 5 to the system bus controller 3, 3'.
, 5'', a signal line 8, 8'' indicating that desired data is being sent to the bus 5, 5' in response to memory read access from the microprocessor 2, 2'; System buses 100 and 200 connect the processors 1 and 1'.

In FIG. 2, consider the case where the microprocessor 2 issues a read request from the memory 4' and at the same time, the microprocessor 2' issues a read request from the memory 4. The microprocessor 2 sends an address to the bus 5, the system bus controller 3 receives this address, and the memory 4
', and determines that the access is to system bus 10.
0 to the system bus controller 3'. On the other hand, the microprocessor 2' sends an address to the bus 5', and the system bus controller 3' receives this address, determines that the access is to the memory 4, and sends the address to the system bus 5' via the system bus 200. Send to controller 3.

In order to read data from the memory 4, the system bus controller 3 turns on the signal line 6 and issues a request to the microprocessor 2 to use the bus 5. However, the microprocessor 2 does not turn on the bus use permission signal line 7 to the system bus controller 3 because there is no response to the previously issued read. Therefore, the system bus controller 3 uses the bus 5 to read data from the memory 4 from the microprocessor 2'.
It is not possible to return the desired data when reading.
Similarly, since the system bus controller 3' cannot read data from the memory 4', it cannot return desired data when the microprocessor 2 reads data from the memory 4'. That is, the system configuration shown in FIG. 2 falls into a deadlock. In order to solve this problem, another dedicated bus is installed between the system bus controllers 3, 3' and the memories 4, 4', and instead of using the buses 5, 5', the system bus controllers 3, 3' It is necessary to take measures such as making the contents of 4 and 4' readable.

[Problem to be solved by the invention]

As mentioned above, when a conventional microprocessor reads data from memory, it sends an address onto the bus and
In response to this, a path control method is adopted in which the bus is occupied until the data read from the memory is transmitted, so this bus cannot be used for other purposes. Therefore, there is a problem in that an extra amount of material is required for the peripheral circuits of the microprocessor.

The present invention has been made to solve the above problems, and an object of the present invention is to enable a microprocessor to allocate the bus to another module after sending an address to the bus when reading data from the memory. Our goal is to provide technology that can.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

To achieve the above object, the present invention provides a microprocessor equipped with a bus for reading data from a memory or writing data to a memory, in response to bus use requests from other modules connected to the bus. On the other hand,
When reading data from memory, first, an address is sent to the address bus, and in response, a first transmission in which predetermined data is sent, and a first transmission in which only the address is received and a predetermined It is possible to accept two types of responses: a second transmission in which the data is read and then sent, and in the case of a response to the first transmission, the transmitted data is received, address transmission is stopped, and the It is possible to accept bus usage requests from other modules, and in the case of a second transmission response, the microphone port processor stops sending addresses to the bus, waits for data reception, and accepts bus usage requests from other modules connected to the bus. The most important feature is that it has a means for accepting requests.

[Effect]

According to the above-mentioned means, when the microprocessor reads data from the memory, it first sends an address to the address bus, and in response: a first transmission of transmitting predetermined data; and ■. It is possible to accept two types of responses: a second transmission in which only the address is received, and the predetermined data is read out and then transmitted; in the case of a response to the first transmission (■), the transmitted data is received and the address is sent. The microprocessor stops sending addresses to the bus, waits for data reception, and makes it possible to accept bus use requests from other modules connected to the bus.In the case of a response to the second transmission, the microprocessor stops sending addresses to the bus, waits for data reception, and requests to use the bus from other modules connected to the bus. Since it is possible to accept requests for use of the bus from other connected modules, when the microprocessor reads data from the memory, the bus can be allocated to other modules after sending an address to the bus.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic structure of an embodiment of a bus control method in a microprocessor of the present invention.
1-8, 1'-8' and 100, 200 are the same as in FIG. Reference numerals 9 and 9' indicate signal lines for notifying that, in response to memory read access from the microprocessors 2 and 2', only an address will be received and desired data will be transmitted after being read.

In FIG. 1, consider the case where microprocessor 2 issues a read request from memory 4' and at the same time microprocessor 2' issues a read request from memory 4. The microprocessor 2 sends an address on the bus 5, the system path controller 3 receives this address, and the memory 4'
system bus 100.
The address is sent to the system bus controller 3' via.

On the other hand, the microprocessor 2' sends an address to the path 5', and the system bus controller 3' receives this address, determines that the access is to the memory 4, and sends the address to the system bus 200 via the system bus 200. Send to controller 3. In order to read data from the memory 4, the system bus controller 3 first turns on the signal line 9, notifies the microprocessor that only the address will be received and that the desired data will be sent after reading, and further,
The signal line 6 is turned on and a request to use the bus 5 is issued to the microprocessor 2. The microprocessor 2 enters a data reception waiting state, stops sending addresses to the bus 5, turns on the signal line 7, and permits the system bus controller to use the bus 5. System bus controller 5 uses bus 5 to read the contents of memory 4 and sends the data to system bus controller 3' via system bus 100. Similarly, system bus controller 3
' also acquires the bus 5', reads the contents of the memory 4'', and sends it to the system bus controller 3 via the system bus 200.
send to System bus controller 3 sends desired data to the microprocessor via bus 5. Similarly, system bus controller 3' sends desired data to microprocessor 2' via bus 5'.

When the microprocessor 2 reads data from the memory 4, the memory 4 sends the necessary data to the bus 5 and responds to the microprocessor 2 by turning on the signal line 8. As long as the response is made via the signal line 8, there is no need to acquire the right to use the bus.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, when the microprocessor reads data from the memory, after sending the address to the bus, the bus can be allocated to other modules, and the other modules can use the bus. When constructing a processor system using a microprocessor, there is no need to establish a separate bus between other modules, making the processor system more economical.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic structure of an embodiment of a bus control method in a microprocessor of the present invention, and FIG. 2 is a schematic diagram for explaining the problems of a processor system using a conventional microprocessor. FIG. 1 is a block diagram showing one part. In the figure, 1, 1'... Processor, 2, 2'... Microprocessor, 3, 3'... System bus controller, 4, 4'... Memory, 5, 5'... Bus ,6
, 6', 7, 7'', 8, 8', 9, 9'... signal line,
100, 200... system bus.

Claims (1)

[Claims] (1) In a microprocessor equipped with a bus for reading data from or writing data to the memory, means for granting bus usage rights in response to bus usage requests from other modules connected to the bus; When reading data from memory, first, an address is sent to the address bus, and in response, a first transmission is performed in which predetermined data is sent, and only the address is received, and after reading the predetermined data, it is sent. It is possible to accept two types of responses to the second transmission, and in the case of a response to the first transmission, the transmitted data is received and address transmission is stopped,
The microprocessor is enabled to accept bus use requests from other modules connected to the bus, and in the case of a second transmission response, the microprocessor stops sending addresses to the bus, waits for data reception, and other modules connected to the bus 1. A bus control method for a microprocessor, characterized by comprising means for accepting a bus use request from a microprocessor.