JPH01108663A - Interruptive information transmission circuit - Google Patents

Abstract

PURPOSE:To shorten the transmission time of an interruptive information by designating the opponent of an interruption request by using an address line, transmitting the interruptive information directly to the opponent of interruption without bypassing and sending ID information to a system bus when the interruption request is generated. CONSTITUTION:When the interruption request is generated, a device of interrup tion request origin sends the ID information of an interruption designated destina tion to the address line 82 of the system bus 8 and its own ID information to a data line 81, respectively. And only the device having the ID information which coincides with the ID information of the interruption designated destina tion detects the coincidence of IDs, then, performs an interruption processing. In such a way, no interruption bus is required and the interruptive information can be transmitted directly to the device of the interruption designated destina tion.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt information transmission circuit between devices in a computer system in which data processing devices and intelligent devices are interconnected through a system network.

[Conventional technology]

FIG. 3 shows, for example, 1EC821BUS (IEEP1
014/Di.2) is a block diagram showing an example of a conventional computer system of this type. In the figure, A is a system control unit (system controller), B and C are data processing devices, and D is an intelligent device. 1 is the system control unit)A
bus arbiter, 2 is a bus requester that requests lotus usage rights from bus arbiter 1, 3 is an interrupt requester, 4 is an interrupt handler, 5 is a bus master,
6 is a processor (data processing processor), and that of data processing device B is CPU1;
The one is shown as CPU2. 7 is an intelligent input/output processor, and 8 is a system bus, which includes a data transfer bus (data line) 81, a data transfer bus (address line) 82, an interrupt bus 83, an arbitration bus 84, and the like.

Next, the interrupt information transmission operation of this system will be explained.

When an interrupt request signal is sent from the intelligent input/output processor 7, the interrupt request signal is sent to the bus master 5.
It is sent from the interrupt requester 3 to the interrupt bus 83 via the interrupt requester 3. The interrupt request signal sent to the interrupt bus 83 is received by the interrupt handler 4 in the data processing device B, and the bus master 5 activates the bus requester 2 to send out a request signal requesting the right to use the bus. This bus right request signal is received by the bus arbiter 1 of the system control unit A, and the bus arbiter 1 performs bus arbitration. When this arbitration is completed and data processing device B acquires the right to use the bus, the interrupt handler 4 in data processing device B requests the interrupt bus 83 to send an identification number (hereinafter referred to as ID number) indicating the interrupt source. Send a signal. This ID sending request signal is received by the interrupt requester 3 in the intelligent device, and the interrupt requester 3 sends a signal of its own ID number (ID signal) to the data line 81 of the system bus 8. This ID signal is received by the interrupt handler 4 of the data processing device B, and sent from the interrupt handler 5 to the processor (CPIJI).
The interrupt request is transmitted to 6. Thus, after the interrupt information transmission phase is completed and the processor (CPUI) 6 sends an interrupt response signal, it receives the ID information and transmits the corresponding I
Interrupt processing is started based on the D information. Processor (C
If the received ID information is determined to be an interruption to the data processing device C, the PUI) 6 transfers the IDWt information to the processor (CPU 2) 6.

[Problem that the invention seeks to solve]

In this way, conventional systems require a dedicated bus (interrupt bus 83) for transmitting interrupt requests, and 1. When interrupt requests are received simultaneously from multiple devices connected to the system bus 8, has interrupt handler 4
It is necessary to arbitrate the output order of ID signals from each device with respect to the ID sending request signal, and furthermore, the same interrupt request must be managed by one interrupt handler 4, and interrupt information to other devices must be managed by one interrupt handler 4. Communication was impossible.

This invention was made to solve the above problem.
An interrupt that eliminates the need to provide a dedicated interrupt bus, allows interrupt requests to be directly transmitted to the interrupt destination device without passing through other devices, and can shorten transmission time compared to conventional interrupts. The purpose is to provide an information transmission circuit.

[Means for solving problems]

In order to achieve the above object, the present invention includes a self-identification information storage circuit that stores in advance the self-identification information of the device to which it belongs and reads it out to the system bus; an identification information storage circuit for reading out to the bus; an identification information verification circuit for verifying the identification information in the information on the system bus with the self-identification information;
Controlling the writing/reading of the identification information storage circuit on the condition that there is a matching output from the interrupt control circuit that transmits the presence of an interrupt request to the processor in the device to which it belongs and the identification information verification circuit, and the above-mentioned The present invention has an identification information transmitting/receiving section having a control circuit for energizing an interrupt control circuit, and the identification information of the interrupt destination is given when an interrupt request is generated.

[Effect]

In this invention, the identification information transmitting/receiving section in the device in which the interrupt request has occurred directly sends the interrupt destination identification information and self-identification information to the system bus. The identification information transmitting/receiving unit in the device to which the interrupt is specified monitors the above identification information sent onto the system bus, and if it finds identification information that matches its own identification information, captures the interrupt information on the system bus. ,
The fact that an interrupt request has been made is transmitted to the processor within the device.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the interrupt requester 3 and interrupt handler 4 in the data processing devices B and C and the intelligent device in FIG. Department (hereinafter referred to as ID
This device differs from the conventional device shown in FIG. 3 in that a transmitter/receiver section 9 is provided.

As shown in FIG. 2, the ID transmitting/receiving section 9 includes a card identification information storage circuit (card ID storage circuit) 20, an identification information verification circuit (ID verification circuit) 21, a write/continuation control circuit 222, and an interrupt control circuit 23. , identification information storage circuit (TD
(D storage circuit) 24. Card ID storage circuit 20
stores identification information unique to the device to which it belongs.

The write/read control wholesale circuit 22 receives the match signal output from the ID verification circuit 21 and the write/read control signal on the system bus 8, and imports the ID information on the system bus 8 into the ID storage circuit 24 and reads the ID information on the system bus 8. It controls the writing and reading of ID information to be sent to the ID storage circuit 24 and generates an interrupt start signal. The ID storage circuit 24 is a temporary storage circuit.

Next, the interrupt information transmission operation in this system will be explained.

It is now assumed that interrupt information is transmitted between the intelligent device and the data processing device 8. The interrupt request signal from the intelligent input/output processor 7 is sent from the bus master 5 to the ID storage circuit 24 of the ID transmitter/receiver 9 (the interrupt destination ID number is stored), and at the same time, the bus master 5 sends the data transfer bus to the A right acquisition request signal is transmitted to the bus requester 2. When an intelligent device acquires the right to use the data transfer bus as a result of bus arbitration by the bus arbiter 1, it is transmitted from the arbitration bus 84 via the bus requester 2 and the bus master 5 to an interrupt in the ID sending/receiving group 9. The ID information is transmitted to the control circuit 23, and the ID transmitting/receiving section 9 sends the ID information of the own unit from the card ID storage circuit 20 to the data line 81, and at the same time transmits the interrupt destination ID information written in the ID storage circuit 24 to the address line. 82.

Data processing equipment B, C, I in intelligent equipment
The D transmitter/receiver 9 constantly monitors the ID information on the address line 82 using the ID verification circuit 2I and checks the ID information on the own card I.
The contents of the D storage circuit 20 are compared, and in this example,
ID verification circuit 2 of ID transmitter/receiver 9 in data processing device B
1 detects a match of ID information and sends a match signal to the write/read control circuit 22. The write/continue control circuit 22 uses the ID information of the interrupt source on the data line 81 as an ID.
At the same time as the data is stored in the storage circuit 24, the interrupt control circuit 23 is informed that there is an interrupt request. As a result, the interrupt control circuit 23 transmits the interrupt request to the processor (CPUI) 6 via the bus master 5, waits for an interrupt response, and upon receiving the interrupt response signal, transfers the contents of the ID storage circuit 24 to the bus master 5. Processor (C
PUI)6. From now on, the processor (CPU1)
6 executes interrupt processing based on the above received contents. On the other hand, data processing device C does not capture the ID information because the ID information on the address line 82 does not match its own ID information.

As described above, in this embodiment, when an interrupt request occurs, the interrupt requesting device waits for the right to use the lotus, and
The ID information of the interrupt destination is sent to the address line 82 of the system bus 8, and the own ID information is sent to the data line 81, and the IDI that matches the ID information of the interrupt destination is sent.
Only the device having the Iv information detects the ID match and performs the interrupt process.

Therefore, an interrupt bus is not required, and interrupt information is directly transmitted to the device to which the interrupt is specified.

In the above embodiment, the ID storage circuit 24 only sends and receives ID information, but it may be configured to send and receive other information (status information, attributes, etc.) at the same time.

Further, although the ID information to be stored in the card ID storage circuit 20 is written from the processor 6, it may be initialized manually using means such as a switch. Further, although the request to acquire the right to use the system bus 8 is transmitted to the bus requester 2 via the bus master 5, it may be directly transmitted to the ID transmission/reception unit 9. Furthermore, even if the computer system is a mixture of the conventional device without the ID transmitting/receiving unit 9 and the device of the present embodiment having the ID transmitting/receiving unit 9, the above-mentioned difference between the devices of the present embodiment having the ID transmitting/receiving unit 9 You can perform the following actions.

〔Effect of the invention〕

As explained above, this invention has the advantage that the destination of an interrupt request can be specified using the address line, so there is no need to provide a dedicated interrupt bus. Since interrupt information can be transmitted first, it is easier to transmit interrupt information between devices, and when an interrupt request occurs, the ID
Since the information is sent to the system bus, there is an advantage that the interrupt information transmission time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of an identification information transmitting/receiving section in the above embodiment, and FIG. 3 is a block diagram showing a conventional computer system. requester, 5-bus master, 6.7-processor, 8-system bus, 20-card identification information storage circuit, 21-identification information verification circuit, 22-
Write/continue control circuit, 23-interrupt control circuit, 24
- identification information storage circuit, B, C- data processing device, D- intelligent device. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] In a computer system in which multiple data processing devices, intelligent devices, and system control units are connected by a system bus, a self-identification information storage circuit that stores in advance the self-identification information of the device to which it belongs and sends it to the system bus, and an interrupt designation destination. an identification information storage circuit that stores information including identification information of the user and sends it to the system bus; an identification information verification circuit that compares the identification information in the information on the system bus with the self-identification information; control the writing/reading of the identification information storage circuit and the interrupt control circuit on the condition that there is a matching output of the interrupt control circuit that transmits the information to the processor in the device to which the device belongs and the identification information verification circuit; An interrupt information transmission circuit comprising an identification information transmitting/receiving section having an energizing control circuit, wherein the identification information of the interrupt destination is given when an interrupt request is generated.