JP2001306486A - Shared memory access system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means that can directly and effectively access a fast memory which is connected one to one to an exclusive I/F from an external bus master. SOLUTION: When an external bus master 212 accesses an RDRAM 210, a DMA is set and requested to an internal DMA control part 204 by means of protocol control signals such as HLDRQ (213), HLDAK (214), MRQ (215) and MREADY (216). Meanwhile, the bus master 212 outputs the same command of protocol as that of protocol to be given when a CPU 201 gains access to the RDRAM 210 to an external system bus 211. The bus master 212 performs the DMA data transfer to the RDRAM 210 via a direct path set between a slow bus control part 206 and a fast bus control part 205.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory access system, and more particularly to an RDRAM (Rambus DRAM) and an SDRAM connected one-to-one to a bus master such as a CPU.
The present invention relates to a shared memory access system suitable for accessing a general-purpose high-speed memory such as a RAM (Synchronous DRAM) from an external bus master.

[0002]

2. Description of the Related Art Since a system resource called a memory is expensive, there are many systems in which a plurality of processing devices, for example, a CPU and an input / output device are connected by a bus to share a memory. In such a system, a device that can request the right to use the bus, such as a CPU or an input / output device, is called a bus master. Here, a bus master other than the CPU is referred to as an external bus master.

Conventionally, when an external bus master accesses a memory, there is known a method of exchanging data by indirect means such as communication between CPUs. This method
If an external master tries to access the memory,
First, the external bus master establishes communication with the CPU,
Thereafter, the external bus master accesses the memory via the CPU.

In a "data transfer device" described in Japanese Patent Application Laid-Open No. 1-185557, a bypass is provided in a system bus connecting a processor, a memory, an input / output device, and a bus master. Even during data transfer, the bus master can transfer data to and from the memory via another system bus, thereby improving system efficiency.

Further, in the "identification number assigning method" described in Japanese Patent Application Laid-Open No. 3-257655, a memory and a plurality of bus masters are connected to one system bus, and an identification number registration area is provided in a memory area. By registering the identification number in this area by program control, errors such as double registration can be eliminated and the system can be flexibly responded to system changes.

Further, in the "system bus control system of an information processing apparatus" described in Japanese Patent Application Laid-Open No. Hei 3-19752, a memory is accessed by address information stored in information holding means such as a FIFO. A control circuit or the like is provided so that the system bus is used by another bus master even when the memory is being accessed by a certain bus master and when data transfer is not actually performed.

[0007]

However, each of the above-mentioned conventional techniques has the following problems.

[0008] In the first technique utilizing communication between CPUs,
Since the CPU that manages the memory accesses the memory and indirectly exchanges data with the external bus master, the CPU process is inserted between the memory for access and the external bus master process. Decrease.

In the technique described in the second Japanese Patent Application Laid-Open No. 1-185557, the RDR is stored in the memory because the bus has a dual configuration.
When a recent general-purpose high-speed memory such as an AM or an SDRAM is used, a dedicated interface (I / F) of a specification required on the memory side is branched into one-to-two, so that electrical characteristics and signal timing conditions are required. There is a problem that it is quite difficult to actually design a base so as to satisfy the above. Further, since the bus is duplicated, the area of the signal line is also increased, and it is very difficult to design the device compactly.

In the technique disclosed in Japanese Patent Laid-Open No. Hei 3-257655, the memory is connected to one bus in a one-to-many connection since a memory and a plurality of bus masters are connected to one system bus. For the same reason as in the prior art, there is a drawback that it is difficult to satisfy the specifications of the dedicated I / F of the general-purpose high-speed memory. Further, a bus exclusive control unit for arbitrating a plurality of equivalent bus masters must be installed separately from the bus master, and furthermore, a part of the memory area is divided and an identification number registration area for bus master identification is allocated in the memory area. There is also the disadvantage of having to create

In the technique described in Japanese Patent Application Laid-Open No. 4-319,752, a bus arbitration function (a bus control circuit, a FIFO control circuit, etc.) is provided in a main storage device including a memory.
Must be provided. Therefore, as in the case of the third prior art, the general-purpose memory cannot be used as it is, and an area for arbitration information is reserved in the memory area in advance, and a plurality of main memories including the memory are provided. If a bus control unit for arbitrating the bus master must be incorporated, the configuration of the memory unit becomes complicated.

The bus to which the memory is connected is a system bus, not a bus dedicated to the memory. However, recent general-purpose high-speed memories (RDRAMs and the like) require dedicated I / Fs specific to their memory types, but it is difficult for the third and fourth prior arts to meet such demands. Even if a general-purpose high-speed memory is fetched into the main storage device as in the fourth conventional technique, access from all bus masters is indirect in any case, and the recent high-speed memory which is an advantage of the general-purpose high-speed memory is obtained. There is also a problem that it cannot be used for high-speed access from a CPU.

An object of the present invention is to provide an I / O dedicated to a general-purpose high-speed memory.
An object of the present invention is to provide a shared memory access system that can access a general-purpose high-speed memory connected one-to-one to a main bus master such as a CPU with a / F at a high speed from an external bus master.

Another object of the present invention is to provide a shared memory access system capable of suppressing an increase in signal lines and enabling a compact design.

[0015]

According to a first aspect of the present invention, there is provided a shared memory access system which is shared by a CPU in a CPU chip and an external bus master connected to the CPU chip by an external system bus. A memory which is connected to the F in a one-to-one bus connection is accessed from the external bus master using the same protocol as the protocol by which the CPU accesses the external system bus.

A shared memory access system according to a second aspect of the present invention includes a high-speed memory interface connected to a high-speed memory on a one-to-one basis; a high-speed system bus connected to the high-speed memory interface; A high-speed bus control unit that controls the high-speed system bus; an external system bus connected to the external bus master; a low-speed system bus connected to the external system bus and the low-speed memory; A low-speed bus control unit for controlling a system bus; a DMA control unit for controlling the low-speed bus control unit and the high-speed bus control unit and issuing a DMA transfer instruction to each of them; A bus buffer used for DMA data transfer in the same CPU chip;
When the external bus master outside the chip performs data transfer with the high-speed memory, the CPU temporarily relinquishes the bus master right in response to a request from the external bus master, and the DMA control unit operates similarly to the normal DMA transfer. Data is bridged between the high-speed memory and an external bus master.

High-speed memories include, for example, RDRAM and SD
It may be a RAM.

The operation will be described with reference to a specific example of the present invention. In FIG. 2, an RDRAM 210 is a dedicated RSRAM I / F2
03 is connected in a one-to-one manner, and the CPU 201 normally serves as a bus master to manage the CPU chip 209 with a built-in peripheral circuit. When the external bus master 212 wants to access the RDRAM 210, the external bus master 212
It issues a bus hold request protocol control signal HLDRQ (213) to the PU chip 209. On the other hand, if the CPU 101 allows the bus control to be released,
The bus hold is permitted, and the hold acknowledge protocol control signal HLDAK (214) is sent to the external bus master 2
Return to 12.

The external bus master 212 receives HLDAK (21
4), upon receiving the bus mastership of the CPU chip 209, MRQ (215) and MREADY (21)
A memory access is issued to the external system bus (211) together with the two protocol control signals of 6). On this occasion,
Inside the CPU chip 209, control similar to that of DMA is performed, and the RDRAM 210 and the external bus master 212
The data is transferred while being handled as an MA transfer target. That is, a DMA transfer setting and a DMA request are performed from the external bus master 212.

With this configuration and control, the dedicated I / F
The advantage is that the high-speed memory connected one-to-one can be directly accessed without using indirect means such as communication between CPUs.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the above and other objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 shows the concept of the present invention. In FIG. 1, when the external bus master 102 intends to use a memory (not shown) shared with the CPU 101 via a bus (not shown), it outputs a protocol control signal HLDRQ for a bus hold request to the CPU 101. When the CPU 101 may permit use of the bus, the protocol control signal HL for permitting hold is used.
DAK is transferred to the external bus master 102 and the DMA controller 10.
Output to 3.

External bus master 10 receiving HLDAK
2 is a protocol control signal MRQ for memory request
Then, an address and a read / write command are issued to the DMA control unit 103. The read / write command is issued by the CPU 101 to the external system bus 21 shown in FIG.
1 is the same as the protocol for accessing.
On the other hand, when the preparation for the DMA transfer is completed, the DMA control unit 103 sets the protocol control signal MREAD.
Y is output to the external bus master 102. Then, once the CPU 10 is connected between the external bus master 102 and the memory.
1 controls data transfer without performing an indirect process such as processing data.

Referring to FIG. 2, there is shown a block diagram of a system configuration according to an embodiment of the present invention. In this embodiment, an RDRAM 210 and an external bus master 212 are connected to a CPU chip 209. CPU
The chip 209 includes an RDRAM I / F 203 for the CPU 201 and the RDRAM 210, and the CPU 201 and the RDRA
A high-speed system bus 202 to which the MI / F 203 is connected,
High-speed side bus control unit 2 for controlling high-speed system bus 202
05, an external system bus 211 for the external bus master 212, a low-speed system bus 208 to which the external system bus 211 and a low-speed memory (not shown) are connected, a low-speed bus control unit 206 for controlling the low-speed system bus 208,
DMA controller 204 that controls high-speed bus controller 205 and low-speed bus controller 206, and bus buffer 20
7 inclusive.

The CPU 201 is the core CPU of the present system. RDRAM 210 is used as a general-purpose high-speed memory, and an RDRAM I / F 20 which is an I / F unit dedicated to the memory is used.
3 and the high-speed system bus 20 together with the CPU 201.
2 are connected. The high-speed system bus 202 is controlled by a high-speed bus control unit 205. The low-speed system bus 208 is connected to a low-speed memory or the like, which is a memory whose speed cannot be as high as that of the RDRAM 210. The low-speed system bus 208 is controlled by the low-speed bus control unit 206. Then, the high-speed system bus 202 side,
Normal data exchange with the low-speed system bus 208 is directly performed between the high-speed bus control unit 205 and the low-speed bus control unit 206 without passing through the bus buffer 207.

RDRAM 210 as a main storage memory;
When performing DMA transfer with the low-speed memory, the DMA control unit 204 issues a DMA transfer instruction to the high-speed bus control unit 205 and the low-speed bus control unit 206, respectively. D at this time
The MA transfer data is temporarily stored in a bus buffer 207 provided exclusively for DMA from a transfer source bus (high-speed system bus 202 or low-speed system bus 208). When the accumulation of data in the bus buffer 207 is completed, the bus on the transfer source side is released, and the data is sent out to the bus on the transfer destination side (low-speed system bus 208 or high-speed system bus 202).

The external bus master 212 is a CPU chip 2
09 is connected via an external system bus 211 to the outside. The HLDRQ 213 transmits a bus hold request from the external bus master 212, and the HLDAK 214 transmits a bus hold permission from the CPU chip 209. MRQ 215 and MREADY 216 are protocol control signals in a state where the bus hold request of the external bus master 212 is permitted. BCLKOUT 217 is a system clock for an external system bus.

Since the RDRAM 209 is well known to those skilled in the art, and is not directly related to the present invention, the detailed description thereof will be omitted.

Hereinafter, the operation of the present embodiment will be described. First, a read operation from the RDRAM 210 will be described with reference to the block diagram of FIG. 2 and the timing diagram of FIG.

From the external bus master 212 to the RDRAM 21
0, the external bus master 21
2 first issues HLDRQ 213 of active L,
It requests a bus hold from the CPU 209. In the timing chart of FIG. 3, a bus hold request has already been issued from the beginning. This bus hold request is transmitted to the CPU 201 without passing through the DMA control unit 204. When the CPU 201 permits the bus hold of the CPU chip 209, the active low HLDAK 214 is returned to the external bus master 212 without passing through the DMA control unit 204. I do. FIG.
In the timing chart of FIG. HLD
The AK 214 is also transmitted from the CPU 201 to the DMA control unit 204.

When the bus hold is established, the external bus master 212 accesses the RDRAM 210 by using the active high MRQ, which is a protocol control signal for access.
Along with 215, a memory read protocol command including an access target address and data size is output to the external system bus 211. This corresponds to the phase shown in FIG. At this time, the protocol command output from the external bus master 212 to the external system bus 211 is the same as the protocol of the CPU chip 209 for accessing the external system bus 211. MRQ2 in the phase of FIG.
15 together with the address information and the memory read protocol command received from the external system bus 211.
A is transmitted to the A control unit 204, and as the DMA transfer setting, D
The setting is made such that the MA transfer source is the RDRAM 210 and the DMA transfer destination is the external bus master 212.

When the preparation for the DMA transfer is completed, the MREADY 216 of the active L is set in the phase of FIG.
Is issued to the external bus master 212, and one clock later, in the phase of FIG.
The data DMA-transferred into the PU chip 209 is output to the external system bus 211. Output of data requested to be read by the external bus master 212 (see FIG.
When the external bus master 212 completes the HL
The DRQ 213 is returned to inactive (H) (phase in FIG. 3), and the bus hold request is cancelled. HLD
When the RQ 213 returns to inactive (H), the CPU 2
01 returns the HLDAK 214 to inactive (H) and returns from the bus hold state (phase 11 in FIG. 3).

Next, the write operation to RDRAM 210 will be described with reference to both the block diagram of FIG. 2 and the timing diagram of FIG.

From the external bus master 212 to the RDRAM 21
0, the external bus master 21
2 first issues HLDRQ 213 of active L,
It requests a bus hold from the CPU 209. In the timing chart of FIG. 4, a bus hold request has already been issued from the beginning. This bus hold request is transmitted to the CPU 201 without passing through the DMA control unit 204. When the CPU 201 permits the bus hold of the CPU chip 209, the active low HLDAK 214 is returned to the external bus master 212 without passing through the DMA control unit 204. I do. FIG.
In the timing chart of FIG. HLD
The AK 214 is also transmitted from the CPU 201 to the DMA control unit 204.

When the bus hold is established, the external bus master 212 performs an access to the RDRAM 210 by using an active high MRQ, which is a protocol control signal for the access.
Along with 215, a memory write protocol command including an access target address and a data size is output to the external system bus 211. This corresponds to the phase of FIG. At this time, the protocol command output from the external bus master 212 to the external system bus 211 is the same as the protocol of the CPU chip 209 for accessing the external system bus. The address information and the memory read protocol command received from the external system bus 211 together with the MRQ 215 in the phase of FIG. 4 are transmitted to the DMA control unit 204, and are set as DMA transfer settings.
External bus master 212 for transfer source, RDR for DMA transfer destination
The setting is made with the AM 210.

When the preparation for the DMA transfer is completed, the MREADY 216 of the active L is set in the phase of FIG.
Is issued to the external bus master 212. At the rise of BCLKOUT at the beginning of the phase in FIG.
The external bus master 212 recognizes that the preparation for the DMA transfer is OK, outputs the transfer data to the external system bus 212 from the fall of BCLKOUT in the phase of FIG.

When the data transfer is completed, the external bus master 212 returns the HLDRQ 213 to inactive (H) (the phase in FIG. 4) and cancels the bus hold request. When the HLDRQ 213 returns to inactive (H), the CPU 201 returns the HLDAK 214 to inactive (H) to return from the bus hold state (phase 11 in FIG. 3).

According to another embodiment of the present invention, the basic configuration is as described above.
An SDRAM may be adopted instead of the RDRAM 210. Since the SDRAM is well known to those skilled in the art, and is not directly related to the present invention, detailed description thereof will be omitted.

[0039]

As described above, according to the present invention, the general-purpose high-speed memories RDARM and SDRAM which are connected to a bus master such as a CPU one-to-one by a dedicated I / F of the SDRAM are used. On the other hand, it is possible to directly access from the external bus master by efficient means instead of inefficient and indirect means such as communication between CPUs.

Further, since the means such as the bus duplication as in the prior art is not employed, there is an effect that the increase in the number of signal lines can be suppressed and the high-speed IC specification can be prevented from being damaged.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the concept of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart for a memory read operation of the embodiment shown in FIG. 1;

FIG. 4 is a timing chart for a memory write operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

 101 CPU 102 External bus master 103 DMA control unit 201 CPU 202 High-speed system bus 203 RDRAM I / F 204 DMA control unit 205 High-speed side bus control unit 206 Low-speed side bus control unit 207 Bus buffer 208 Low-speed system bus 209 OPU chip 210 RDRAM 211 External System bus 212 External bus master 213 HLDRQ 214 HLDAK 215 MRQ 216 MREADY 217 BCLKOUT

Claims (4)

[Claims] A memory shared by a CPU in a CPU chip and an external bus master connected to the CPU chip by an external system bus, and connected to a dedicated I / F in a one-to-one correspondence with the memory, A shared memory access system wherein the external bus master accesses the external system bus using the same protocol as a protocol by which a CPU accesses the external system bus. 2. A high-speed memory interface connected to the high-speed memory on a one-to-one basis, a high-speed system bus connected to the high-speed memory interface, and a CPU which is usually a bus master of the high-speed system bus
A high-speed bus control unit for controlling the high-speed system bus; an external system bus connected to an external bus master; a low-speed system bus connected to the external system bus and the low-speed memory; and controlling the low-speed system bus A low-speed bus control unit, a DMA control unit that controls the low-speed bus control unit and the high-speed bus control unit and issues a DMA transfer instruction to each of the low-speed bus control unit, and a DMA control unit that is used when DMA data is transferred between the high-speed memory and the low-speed memory When the external bus master outside the CPU chip performs data transfer with the high-speed memory, the CPU temporarily grants the bus master right in response to a request from the external bus master. The DMA controller transfers data between the high-speed memory and the external bus master in the same manner as in a normal DMA transfer. Shared memory access system and performs a bridge data. 3. The shared memory access system according to claim 1, wherein an RDRAM is employed as said high-speed memory. 4. The shared memory access system according to claim 1, wherein an SDRAM is adopted as said high-speed memory.