JPH03152944A - 電界効果型トランジスタのワイヤボンディング方法 - Google Patents
電界効果型トランジスタのワイヤボンディング方法Info
- Publication number
- JPH03152944A JPH03152944A JP1291003A JP29100389A JPH03152944A JP H03152944 A JPH03152944 A JP H03152944A JP 1291003 A JP1291003 A JP 1291003A JP 29100389 A JP29100389 A JP 29100389A JP H03152944 A JPH03152944 A JP H03152944A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- effect transistor
- wire bonding
- field effect
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 12
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000005611 electricity Effects 0.000 description 12
- 230000003068 static effect Effects 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 10
- 230000006378 damage Effects 0.000 description 6
- 230000035939 shock Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
め要約のデータは記録されません。
Description
タのワイヤボンディング方法に関するものである。
グにおいては、第3図に示すように、第1番目のボンデ
ィング4を半導体素子のボンディングパッド3側に、第
2番目のボンディング5をパッケージ(又はリードフレ
ーム)2例の端子に行うことにより、結線するようにし
ていた。
ディング方法においては、これを静電耐圧が極めて低い
半導体素子に対して行うと、ワイヤボンディング時に発
生する静電気は、第1番目のボンドが半導体素子のボン
ディングバントに接触した瞬間、ボンディングバンドか
ら半導体素子の動作層に流れ込み、半導体素子の静電破
壊を誘起したり、或いは、破壊にまで及ばないとしても
半導体素子に静電衝撃を加えることにより、半導体素子
の品質が損なわれるという欠点があった。
のワイヤボンディング時に発生ずる静電破壊を防止し、
信頼性の高い電界効果型トランジスタのワイヤボンディ
ング方法を提供することを目的とする。
ンジスタのワイヤボンディングにおいて、ソースのボン
ディングパッド(11)にワイヤボンディングを行う工
程と、ドレインのボンディングバンド(12)にワイヤ
ボンディングを行う工程と、ゲートのボンディングバン
ド(13)にワイヤボンディングを行う工程とを施すよ
うにしたものである。
ンディングをパッケージ(又はリードフレーム)側とな
し、第2番目のボンディングを電界効果型トランジスタ
のボンディングパッド側とするようにしたものである。
ボンディングパノ)”(11)にワイヤボンディングを
行い、その後、ドレインのボンディングパッド(12)
にワイヤボンディングを行い、最後に静電耐圧力月番低
いゲートのボンディングパッド(13)にワイヤボンデ
ィングを行うようにしたので、一部の静電気が電界効果
型トランジスタに印加されたとしても、ゲートの静電破
壊を防止することができる。
も、第1番目のボンディングはパッケージ(又はリード
フレーム)側であるため、発生した静電気をパッケージ
(又はリードフレーム)を通して逃がすことができ、電
界効果型トランジスタに静電衝撃を与えることはない。
ボンディングをするワイヤは既に第1番目のボンドでパ
ッケージ(又はリードフレーム)に接続されているため
に、その静電気はボンディングワイヤを通してパッケー
ジ(又はリードフレーム)側に逃げてしまい、電界効果
型トランジスタに静電衝撃を与えることはない。
に説明する。
のワイヤボンディング工程の説明図である。
ードフレーム)20側に第1番目のボンディング21a
を行い、次いで、電界効果型トランジスタ10のソース
のボンディングパッド11へのボンディング22aを行
う。
ードフレーム)20側に第1番目のボンディング21b
を行い、次いで、電界効果型トランジスタ10のドレイ
ンのボンディングパッド12へのボンディング22bを
行う。
リードフレーム)20側に第1番目のボンディング21
cを行い、次いで、静電耐圧が1番低いゲートのボンデ
ィングパッド13へのボンディング22cを行う。
ッケージ(又はリードフレーム)20側のボンディング
を先行させ、その後に電界効果型トランジスタ10側の
ボンディングパッドへのボンディングを行う。例えば、
ゲートのボンディングパッド13の場合は、第2図に示
すように、まず、パンケージ(又はリードフレーム)2
0側へのボンディング21cを行った後に電界効果型ト
ランジスタ10側にあるゲートのボンディングパッド1
3へのボンディング22cを行う。
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。
果型トランジスタのソース、トレインの順序で先にワイ
ヤボンディングを行い、最後にゲートのワイヤボンディ
ングを行うようにしたので、一部の静電気が電界効果型
トランジスタに印加されたとしても、ゲートの静電破壊
の確率は非常に低く押さえることができる。
も、第1番目のボンドはパッケージ(又はリードフレー
ム)側であるため、発生した静電気をパッケージ(又は
リードフレーム)を通して逃がすことができ、電界効果
型トランジスタに静電衝撃を与えることはない。
はリードフレーム)に接続されているため、いかなる場
合でも、電界効果型トランジスタよりもボンディングワ
イヤの方が電気抵抗が低くなる。そのため、第2番目の
ボンド時に静電気が発生したとしても、その静電気は、
ボンディングワイヤを通してパッケージ(又はリードフ
レーム)側に逃げてしまい、電界効果型トランジスタに
静電衝撃を与えることはない。
M T (High Electron Mobil
ity Transistor)を、30.000個製
造した結果、静電破壊による不良は発生していない。ま
た、1000時間にわたる高温通電試験バイアス印加に
よる加速耐湿試験等も実施しているが、そのような信輔
性試験でも不良も皆無である。
のワイヤボンディング工程の説明図、第2図はその電界
効果型トランジスタのワイヤボンディング状態を示す部
分側面図、第3図は従来の半導体素子のワイヤボンディ
ング状態を示す部分側面図である。 10・・・電界効果型トランジスタ、II・・・ソース
のポンディングバンド、12・・・ドレインのボンディ
ングバンド、13・・・ゲートのポンディングパラ「、
20・・・パッケージ(又はリードフレーム) 、21
a、21b。 21c、22a、22b、22c・・・ボンディング。
Claims (2)
- (1)電界効果型トランジスタのワイヤボンディング方
法において、 (a)ソースのボンディングパッドにワイヤボンディン
グを行う工程と、 (b)ドレインのボンディングパッドにワイヤボンディ
ングを行う工程と、 (c)ゲートのボンディングパッドにワイヤボンディン
グを行う工程とを有することを特徴とする電界効果型ト
ランジスタのワイヤボンディング方法。 - (2)請求項1記載の電界効果型トランジスタのワイヤ
ボンディング方法において、第1番目のボンディングを
パッケージ又はリードフレーム側となし、第2番目のボ
ンディングを電界効果型トランジスタのボンディングパ
ッド側とすることを特徴とする電界効果型トランジスタ
のワイヤボンディング方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1291003A JP2726124B2 (ja) | 1989-11-10 | 1989-11-10 | 電界効果型トランジスタのワイヤボンディング方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1291003A JP2726124B2 (ja) | 1989-11-10 | 1989-11-10 | 電界効果型トランジスタのワイヤボンディング方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03152944A true JPH03152944A (ja) | 1991-06-28 |
JP2726124B2 JP2726124B2 (ja) | 1998-03-11 |
Family
ID=17763202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1291003A Expired - Lifetime JP2726124B2 (ja) | 1989-11-10 | 1989-11-10 | 電界効果型トランジスタのワイヤボンディング方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2726124B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005340677A (ja) * | 2004-05-31 | 2005-12-08 | Matsushita Electric Ind Co Ltd | ワイヤボンダの押さえパーツおよび支持パーツ |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62192641U (ja) * | 1986-05-29 | 1987-12-08 |
-
1989
- 1989-11-10 JP JP1291003A patent/JP2726124B2/ja not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62192641U (ja) * | 1986-05-29 | 1987-12-08 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005340677A (ja) * | 2004-05-31 | 2005-12-08 | Matsushita Electric Ind Co Ltd | ワイヤボンダの押さえパーツおよび支持パーツ |
Also Published As
Publication number | Publication date |
---|---|
JP2726124B2 (ja) | 1998-03-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5288661A (en) | Semiconductor device having bonding pad comprising buffer layer | |
JPH09321220A (ja) | 薄膜型の静電放電保護構造を有するマイクロエレクトロニクス・デバイス | |
JPWO2011087119A1 (ja) | 半導体装置およびその製造方法 | |
US20190237458A1 (en) | Semiconductor device having multiple gate pads | |
JPH03152944A (ja) | 電界効果型トランジスタのワイヤボンディング方法 | |
JP4179491B2 (ja) | 半導体装置及びその製造方法、ならびにその特性評価方法 | |
CN101582421A (zh) | 可测试静电放电保护电路 | |
JPH0511660B2 (ja) | ||
JPS60235455A (ja) | ダイナミツクメモリ− | |
JP2757702B2 (ja) | 樹脂封止型半導体装置 | |
JPH11345847A (ja) | 半導体ウエハ及び半導体装置の製造方法 | |
JPH07106386A (ja) | 半導体装置のスクリーニング方法 | |
JPH04139848A (ja) | 半導体装置 | |
JP2641998B2 (ja) | 半導体装置 | |
JPH09283572A (ja) | フィルム・キャリア半導体装置 | |
JPH0567708A (ja) | 半導体集積回路のパツケージ方法 | |
JPH02271547A (ja) | フィルムキャリヤ型半導体装置 | |
JPH07202183A (ja) | 半導体集積回路装置 | |
JPS6159657B2 (ja) | ||
JPS6188539A (ja) | Mos電界効果トランジスタ | |
JP2000164611A (ja) | 半導体集積回路及び半導体集積回路の製造方法 | |
JPS61274279A (ja) | 半導体装置のスクリ−ニング方法 | |
JPS62163371A (ja) | ゲ−トタ−ンオフサイリスタ | |
JPS63283138A (ja) | 半導体装置 | |
JPH118351A (ja) | 半導体装置及びその実装方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081205 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081205 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091205 Year of fee payment: 12 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091205 Year of fee payment: 12 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
EXPY | Cancellation because of completion of term |