JPH03145162A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a semiconductor device low in resistance and to enable it to be easily manufactured by a method wherein the surfaces of a polysilicon gate electrode and a source and a drain diffusion layer formed on a silicon substrate are exposed, and a high melting metal layer grown through a selective CVD method is formed in contact with the exposed surfaces concerned. CONSTITUTION:A polysilicon gate oxide film 3 is formed on a region demarcated by a LOCOS oxide film 2 on a P-type semiconductor substrate 1, and a gate electrode 4 is formed thereon. A low concentration N-type diffusion layer 5 is formed taking advantage of the gate electrode 4. Thereafter, a side wall 6 is formed on both the sides of the gate electrode 4 respectively, impurity is implanted taking advantage of the side walls 6 to form an N-type high concentration diffusion layer 7. Then, the surface of the polysilicon gate electrode 4 and a source and a drain diffusion layer, 7 and 7, of silicon are exposed, and tungsten is selectively grown on the exposed surface concerned through a CVD method to form a high melting metal layer 8. By this setup, the gate electrode 4, the source diffusion layer 7, and the drain diffusion layer 7 are made low in resistance by the high melting metal layer 8 to enable an element to operate at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOS (MOS) transistor whose wiring resistance is lowered to improve its operating speed.

[Conventional technology]

Conventionally, in this type of semiconductor device, in order to reduce the resistance of the source, drain, and gate electrodes of a MOS transistor, a high-melting point metal silicide compound is formed in contact with the source, drain, and gate electrodes by a self-alignment method.

FIG. 2 shows an example thereof, which will be explained together with its manufacturing method. First, an LO of about 1 μm is formed on the P-type semiconductor substrate 11.
After forming the GO3 (selective oxidation method) oxide film 12, the gate oxide film 13. A gate electrode 14 is formed. Then, a low concentration N type expansion layer 15 is formed by implanting N type impurities at a low concentration.

Furthermore, after sidewalls 16 are formed on both sides of the gate electrode 14, a high melting point metal (for example, titanium) is sputtered and heat-treated on the entire surface to convert the high melting point metals on the source, drain, and gate electrodes into silicide compounds. . Then, by selectively etching and removing only the high melting point metal that has not been silicided, the high melting point metal silicide layer 18 is formed in a self-aligned manner. Furthermore, after that, high concentration N
A type diffusion N17 is formed.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, in order to form the high melting point metal silicide layer 18 by a self-alignment method, a whole surface sputtering process of the high melting point metal, a heat treatment (silicidation) process 2 and a selective etching removal process are required. becomes long and complicated. Also, since it turns high melting point metal into silicide,
There is a problem in that the resistance becomes relatively large when used as wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has low resistance and can be easily manufactured.

[Means to solve the problem]

In the semiconductor device of the present invention, the surfaces of the gate electrode made of polysilicon and the source and drain diffusion layers formed in the silicon substrate are exposed, and the semiconductor device is processed by selective CVD in contact with these exposed surfaces. A grown high melting point metal layer is formed.

[Effect]

In this configuration, the high melting point metal layer is grown only on the exposed surface of the silicon material by selective CVD, so it is possible to manufacture a semiconductor device with low resistance using only this growth step.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.

This configuration will be explained according to the manufacturing process.

First, a LOCO8 oxide film 2 of about 1 .mu.m is formed on a P-type semiconductor substrate 1, and a gate oxide film 3 made of polysilicon is formed in the region bottomed by the LOCO3 oxide film 2. Then, a gate electrode 4 is formed on the gate oxide film 3. Then, an N-type impurity is implanted by a self-alignment method using the GaI electrode 4 to form a low concentration N-type diffusion layer 5.

Thereafter, sidewalls 6 are formed on both sides of the gate electrode 4. This sidewall 6 can be easily formed by depositing sidewall material on the entire surface and then etching back this sidewall material using an anisotropic etching method.
can. Then, using this sidewall 6, impurities are implanted to form a heavily doped N-type diffusion layer 7 as a source and a drain.

Next, the diffusion layer 7 on the gate electrode 4 and on the source and drain
After exposing the polysilicon and silicon surfaces, tungsten is selectively grown on the silicon surfaces by CVD to grow a high melting point metal layer 8. In this selective CVD method, tungsten is grown only on the exposed surface of silicon, and tungsten is not grown on other parts.

As a result, the high melting point metal layer 8 is formed only on and in contact with the gate electrode 4 and the source and drain diffusion layers 7. Therefore, the gate electrode 4 and the source and drain diffusion layers 7 are made to have low resistance by the high melting point metal layer 8, thereby achieving higher speed of the device. In addition, during this manufacturing, full surface sputtering of high melting point metal, silicide ratio treatment of 9
Processes such as selective etching are not necessary, and the high melting point metal layer 8 can be easily manufactured.

Note that other high melting point metals that can be selectively grown by CVD may be used instead of tungsten.

〔Effect of the invention〕

As explained above, the present invention simplifies the manufacturing process of the high melting point metal layer because the high melting point metal layer is grown by selective CVD only on the exposed surfaces of the gate electrode, source, and drain diffusion layers. There is an effect that can be done. In addition, high melting point metals have lower layer resistance than silicide compounds, so they are suitable for gate electrodes and sources.

This also has the effect of reducing the resistance of the drain diffusion layer and improving the operating speed.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view of an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of a conventional semiconductor device. l, 11... P-type semiconductor substrate, 2, 12... LOC
○S oxide film, 3.13... Gate oxide film, 4.14.
...Gate electrode, 5.15...Low concentration N-type diffusion layer, 6
．． 16...Side wall, 7.17...High concentration N
Type diffusion layer, 8... High melting point metal layer, 18... High melting point metal silicide layer.

Claims (1)

[Claims] 1. In a semiconductor device in which a gate electrode is formed of polysilicon on a gate oxide film formed on a silicon substrate, and source and drain diffusion layers are formed on the silicon substrate, the gate electrode and source and drain diffusion layers are formed on the silicon substrate. 1. A semiconductor device characterized in that the surface of the layer is exposed and a high melting point metal layer is formed in contact with the exposed surface by selective CVD.