JPH03145160A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a semiconductor device from fluctuating in threshold voltage and to protect it against gate breakdown strength failure and instability by a method wherein contaminated resist on a gate insulating film left on a logic region is separated off after an impurity level is formed in the gate insulating film through the implantation of threshold controlling ions, and a new gate insulating film is formed. CONSTITUTION:A tunnel window is made in a gate insulating film 4 of a memory region so as to reach to an N-type diffusion region 3, and an ultra-thin insulating film 5 is grown on the exposed N-type diffusion region 3. Moreover, a polysilicon film 6 is deposited thereon. Then, a slit is made in the polysilicon film 6 in a memory region, and the polysilicon film 6 is removed from a logic region. Furthermore, when a resist pattern is formed for the implantation of ions, the gate insulating film 4 is contaminated by the attachment of resist. Then, ions are implanted so as to control a logic transistor in threshold value. At this point, an impurity level is formed in the gate insulating film 4 on the logic region through the passage of ions. Then, the contaminated gate insulating film 4 on the logic gate is separated off. Thereafter, a new gate insulating film 7b of a logic transistor is formed at the same time together with the insulating film 7a.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor device in which a nonvolatile memory device with a two-layer polysilicon structure and a logic transistor are mounted together. It is used for equipment.

(Conventional technology) Conventionally, E2PROM is formed in a memory area.

When forming a two-layer conductivity type nonvolatile memory device such as an EPROM and a single-layer conductivity type semiconductor device (hereinafter referred to as a "logic transistor") formed in a logic area on the same semiconductor substrate, the following steps are required. The manufacturing method shown below is used.

First, a laminated film of a first insulating film and a first conductive film is formed on a semiconductor substrate, and then the first conductive film and the first insulating film in the logic area are separated using normal photolithography technology. Remove. Further, a second insulating film (gate insulating film of the logic transistor) is formed on the semiconductor substrate in the logic region. Thereafter, ion implantation for controlling the threshold value of the logic transistor is performed using a normal photolithography technique. Furthermore, a second conductive film is deposited on the entire surface to form a gate electrode of a logic transistor.

However, this manufacturing method has the following drawbacks.

First, in order to implant ions for threshold control in the logic system, it is necessary to perform photolithography immediately after forming the gate insulating film for the logic transistor. For this reason, resist, which is generally known as a source of contamination, adheres to the gate insulating film, which is most important for the operation and reliability of the logic transistor. Therefore, this gate insulating film is contaminated, causing fluctuations in the threshold voltage (VTll) of the transistor and poor gate breakdown voltage.

Second, since the process is such that ion species for threshold control are implanted through the gate insulating film of the logic transistor, impurity levels are formed in this insulating film. Therefore, this impurity level eliminates the instability of the device.

(Problems to be Solved by the Invention) As described above, conventional logic transistors have had drawbacks such as fluctuations in the threshold voltage (VTH), poor gate breakdown voltage, and instability.

Therefore, an object of the present invention is an E2PROM.

An object of the present invention is to provide a highly reliable semiconductor device in which a non-volatile memory device such as an EPROM and a logic transistor are mounted together, which is free from fluctuations in the threshold voltage of the logic transistor, poor gate breakdown voltage, and instability.

[Structure of the Invention] (Means for Solving the Three Problems) In order to achieve the above object, the manufacturing method of the present invention first forms at least a first insulating film over the entire surface of a semiconductor substrate, and A first conductive film is formed on the first insulating film. Next, after removing a portion of the first conductive film, ions are selectively implanted into the portion for controlling the threshold of the logic transistor. Next, after removing the first insulating film remaining in the partial head region, a second insulating film (gate insulating film of the logic transistor) is formed on the entire surface. Next, a second conductive film is formed on this second insulating film.

(Function) In the above manufacturing method, in order to prevent the insulating film of the gate of the logic transistor from being contaminated by the resist used in photolithography during ion implantation for controlling the threshold value, the sulfur remaining in the logic region is removed. The first insulating film is peeled off. In addition, a second insulating film is formed in its place. That is, the second insulating film is not exposed to the resist afterwards, and is free from ion species. will not pass.

Therefore, since the second insulating film is a film with less contamination, a highly reliable semiconductor device can be provided.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In this description, common parts will be denoted by common reference numerals throughout the drawings to avoid redundant explanation.

Figures 1(a) to (f) show a two-layer polysilicon structure (FL
1 shows a first embodiment in which the present invention is applied to a semiconductor device in which an OTOX type) E2FROM and a logic transistor having a -layer polysilicon structure are mounted together.

First, as shown in FIG. 2A, the surface of a p-type silicon substrate 1 is separated into an element active region and a field region 2 by a normal element isolation method. Next, as shown in the same figure (b),
Ion implantation is performed in the memory area to form an n-type diffusion region 3 for threshold control and under a tunnel film in the E"FROM cell portion, which will be described later. After this, a gate insulating film (first insulating film) is formed on the entire surface. Further, a tunnel window reaching the gate insulating film 41 in the memory region; n-type diffusion region V43 is opened using photolithographic technology.

An extremely thin insulating film 5 as a tunnel film is grown on the n-type diffusion region 3 exposed by the tunnel window. moreover,
A first polysilicon MO is deposited on the gate insulating film 4 and the ultra-thin insulating film 5. Next, as shown in FIG. 2C, a slit (not shown) is opened in the polysilicon film 6 in the memory area using photolithography. Furthermore, the polysilicon film 6 is peeled off in the logic region. Furthermore, a resist pattern (not shown) for ion implantation is formed using photolithography.

The +15 gate insulating film 4 in the logic region is contaminated by the adhesion of resist. Further, ion implantation for controlling the threshold value of the logic transistor is performed using ion implantation technology. At this time, an impurity level is formed in the gate insulation l\I4 of the logic region by the passage of ion species. Therefore,
As shown in FIG. 4(d), the gate insulating film 4 in the thus contaminated logic region is removed by etching. After this, Po1y-Po of E2FROM cell
ly insulating film (second insulating film) At the same time as 7a, a new gate insulating film (second insulating film 1t! I
) form 7b. Further, a second polysilicon film 8 is deposited on these insulating films 7a and 7b. Next, as shown in the same figure (e), E
Perform patterning of 2FROM cells and logic transistors. After this, E2FRO was created using ion implantation technology.
The source and drain regions 9 of the M cell and logic transistor are respectively formed to complete the transistor structure.

Next, as shown in FIG. 2F, after a protective film 10 is deposited, this protective film 10 is planarized by heat treatment. Furthermore, after contact holes are formed using photolithography, metal wiring 11 is formed.

By the way, in the first embodiment, the polysilicon 1l
Ie and 8 may be silicide-based materials such as tungsten silicide and molybdenum silicide. The present invention also provides a polysilicon film in which the memory area has two or more layers;
The present invention can be applied as long as the logic region is composed of one or more layers of polysilicon film, and can also be applied to, for example, a semiconductor device in which an EFROM and a logic transistor are mounted together. Furthermore, the present invention can also be applied to semiconductor devices having a CMOS structure.

In addition, the gate insulating film 4, the ultra-thin insulating film 5, and the Po1y-POI formed at the same time! /The insulation M7a and the new gate insulation film 7b are of course a single layer oxide film,
It may also be a nitride film, a nitride oxide film, etc. of the vehicle layer. Further, a composite film of an oxide film and a nitride film, a composite film of an oxide film and a nitrided oxide film, or an insulating film other than those described above may be used.

Figures 2(a) to (f) show a two-layer polysilicon structure (FL
The present invention is applied to a semiconductor device in which an OTOX type) E"FROM and a logic transistor of a -layer polysilicon structure are mounted together, and the mIt& of the insulating films 7a and 7b shown in the above first embodiment is This shows a second embodiment that is different.

First, as shown in FIG. 2A, the surface of a p-type silicon substrate 1 is separated into an element active region and a field region 2 by a normal element isolation method. Next, as shown in the same figure (b),
Ion implantation is performed in the memory region to form an n-type diffusion region 3 for threshold value control and under a tunnel film of an E' FROM cell portion to be described later. Thereafter, a gate insulating film (first insulating film) 4 is formed on the entire surface. Furthermore, a tunnel window reaching the n-type diffusion region 3 is opened in the gate insulating film 4 in the memory region using photolithography.

An extremely thin insulating film 5 as a tunnel film is grown on the n-type diffusion region 3 exposed by the tunnel window. moreover,
A first polysilicon film 8 is deposited on the gate insulating film 4 and the ultra-thin insulating film M5. Next, as shown in FIG. 2C, a slit (not shown) is opened in the polysilicon film 0 in the memory area using photolithography. Further, after forming the Po1y-Poly insulating film 7c of the E2FROM cell, the Po1y-Poly insulating film 7C and the first polysilicon film 6 existing in the logic region are removed using photolithography. Furthermore, a resist pattern (not shown) for ion implantation is formed using photolithography. The gate insulating film 4 remaining in the logic region is contaminated by the adhesion of resist. Further, ion implantation for controlling the threshold value of the logic transistor is performed using ion implantation technology. At this time, an impurity level is formed in the gate insulating film 4 in the logic region due to the passage of ion species. Therefore, as shown in FIG.
Etch this to remove it. After this, E2
A new gate insulating film 7b of the logic transistor is formed at the same time as the Po1y-Poly insulating film 7a which is additionally formed on the Po1y-Poly insulating film 7c of the FROM cell.

Further, a second polysilicon film 8 is deposited on these insulating films 7a and 7b. Next, as shown in FIG. 4(e), patterning of the E2FROM cell and the logic transistor is performed using photolithography technology. Thereafter, the source and drain regions 9 of the E2 FROM cell and the logic transistor are respectively formed by ion implantation technology to complete the transistor structure. Next, the same figure (f)
As shown in the figure, after the protective film 10 is deposited, this protective film! 0 is flattened by heat treatment. Furthermore, after contact holes are formed using photolithography, metal wiring 11 is formed.

By the way, in the second embodiment, the polysilicon film 6
and 8 may be a silicide-based material such as tungsten silicide or molybdenum silicide. Also,
The present invention is applicable as long as the memory area is made up of two or more layers of polysilicon film and the logic area is made up of more than one layer of polysilicon film, and is also applicable to, for example, a semiconductor device in which an EPROM and a logic transistor are mounted together. be able to. Furthermore, the present invention can also be applied to semiconductor devices having a CMOS structure.

In addition, a gate insulating film 4, an extremely thin insulating film 5, a Po1y-Po
The ly insulating films 7a, 7c and the new gate insulating film 7b are not only oxide films of the rat layer, but also may be nitride films, nitrided oxide films, etc. of the t11 layer. Further, a composite film of an oxide film and a nitride film, a composite film of an oxide film and a nitrided oxide film, or an insulating film other than those described above may be used.

Figures 3(a) and (b) show a two-layer polysilicon structure (F
The present invention is applied to a semiconductor device in which a LOTOX type) E2 FROM and a logic transistor with a -layer polysilicon structure are mounted together, and the structure of the insulating film 7c shown in the second embodiment is oxidized@/ This figure shows an example of a gauze 3 made of a nitride film/oxide film.

First, in the same manner as in the second embodiment, a field region 2, an n-type diffusion region t*3, and a gate insulating film 4 are formed on the surface of a p-type silicon substrate 1, respectively.

Further, after opening a tunnel window in the gate insulating film 4 in the memory area, the n-type diffusion region 3 exposed by the tunnel window is
An extremely thin insulating film 5 is grown on top.

Furthermore, a first polysilicon film 6 is deposited on the gate insulating film 4 and the extremely thin insulating film 5 (see FIG. 2(b)). Next, as shown in FIG. 3(a), a slit (not shown) in the polysilicon film 6 is opened in the memory area using photolithography. In addition, an oxide film 7C is used as the Po1y-Poly insulating film 7c of the E2PROM cell.
-1, a laminated film of 7 cm2 of nitride film and 70-9 oxide film is formed. Thereafter, using a photolithography technique, a laminated film of the oxide film 7C-1, nitride film 7C-2, and oxide film 7C-1 existing in the logic area and the first polysilicon M6 are removed.
Perform peeling. Furthermore, a resist pattern (not shown) for ion implantation is formed using photolithography. At this time, the gate insulating film 4 remaining in the logic region is contaminated by the adhesion of resist. Further, ion implantation for controlling the threshold value of the logic transistor is performed using ion implantation technology. At this time, an impurity level is formed in the gate insulating film 4 in the logic region due to the passage of ion species. Therefore, in order to remove the contaminated gate insulating film 4, the memory area is covered with a resist using photolithography technology, as shown in FIG. Peel off only. After this, the E2FROM cell's Po1y-Poly excellent film 7C
Same as the Poly-Poly insulating film 7a to be additionally formed in 14
7, a new gate insulating film 7b of the logic transistor
form. After this, although not shown, the insulating films 7a and 7
A second polysilicon film is deposited on h. Furthermore, patterning of the E2 FROM cell and logic transistor is performed using photolithography technology. moreover,
The transistor structure is completed by forming the source and drain regions of the E2 FROM cell and the logic transistor using ion implantation technology, respectively. Next, after depositing a J-holding film, this protective film is planarized by heat treatment. Further, after forming a contact hole using photolithography technology, a metal wiring is formed into a single shape.

FIGS. 4(a) to (C) show that in the third embodiment,
This shows a fourth embodiment in which the gate insulating film 4 existing in the logic region is removed without adding a photolithographic process.

First, as shown in FIG. 2A, a field region 2, an n-type diffusion region 3, and a gate insulating film 4 are formed on the surface of a p-type silicon substrate 1, respectively. Further, an extremely thin insulating film 5 is formed in the tunnel window of the memory area, and a first polysilicon film 6 is deposited on the gate insulating film 4 and the extremely thin insulating film 5. Furthermore, after opening a slit (not shown) in the polysilicon film 0 in the memory area using photolithography technology, the E2FROM cell's Po1y-Poly insulation [7c
As, oxide film 7cm+s nitride film 7C-2 and oxide film 7
A laminated film of cm is formed. After this, a 7 cm + layer of oxide film existing in the logic area was removed using photolithography technology.
, the laminated film of the nitride film 7C-2 and the oxide film 7C-1 and the first polysilicon film 6 are removed. Furthermore, a resist pattern (not shown) for ion implantation is formed using photolithography. At this time, the gate insulating film 4 remaining in the logic region is contaminated by the adhesion of resist. Further, ion implantation for controlling the threshold value of the logic transistor is performed using ion implantation technology. At this time,
Impurity intermediates are formed in the gate insulating film 4 in the logic region by the passage of ion species. Next, as shown in FIG. 3B, the gate insulating film 4 in the logic region thus contaminated is removed without adding a photolithography process. At this time, 7 cm3 of the uppermost oxide film of the Poly-Poly insulating film 7c is also removed at the same time. Next, the same figure (C
), the E2 FROM cell Po1y-Po
At the same time as the Poly-Poly insulation film 7a which is additionally formed on the Ly insulation film 7c, a new gate insulation film 7b of the logic transistor is formed. After this, although not shown, the insulation M
A second polysilicon film is deposited on 7a and 7b. Furthermore, patterning of the E2FROM cell and logic transistor is performed using photolithography technology.

Further, the source and drain regions of the E2FROM cell and the logic transistor are respectively formed by ion implantation technology to complete the transistor structure. Next, after depositing a protective film, this protective film is planarized by heat treatment.

Further, after contact holes are formed using photolithography technology, metal wiring is formed.

In the third embodiment, a photolithography process is added to the peeling off of the gate insulating film 4 after the ion implantation for threshold control of the logic transistor, and the 7 cm 3 of oxide film is covered with a resist. Therefore, Po1y- of E2FROM cell
The uppermost layer of the poly insulating film 7C is not etched.

Further, in the fourth embodiment, the gate insulating film 4 is peeled off without adding a photolithography process after the ion implantation for threshold control of the logic transistor. For this reason, the Po1y-Poly insulating film 7C of the E2FROM cell
7 cm of the top oxide film is also removed at the same time. However, since the Poly-Poly insulating film 7a is formed before the new gate insulating film 7b of the logic transistor is formed, in terms of reliability, it is possible to improve the reliability by adding one photolithography process as in the third embodiment. There is no inferiority when compared with.

[Effects of the Invention] As described above, the method for manufacturing a semiconductor device of the present invention provides the following effects.

In a semiconductor device in which a non-volatile memory device such as an E2PROM or an EPROM is mixed with a logic transistor, the gate insulating film remaining in the logic region is contaminated with resist due to photolithography, and impurities are added due to subsequent ion implantation for threshold control. It is peeled off because a level is formed. In its place, a new gate insulating film is formed. Therefore, the new gate insulating film is not subsequently exposed to resist, and no ionic species can pass through it. That is, it is possible to eliminate fluctuations in threshold voltage, poor gate breakdown voltage, and instability of the logic transistor.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention, gj44
The figure is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention. l...p-type silicon substrate, 2... field region,
3... N-type diffusion region, 4... Gate insulating film, 5...
・Ultra-thin insulating film, 6.8...polysilicon film, ? a,
7c...Poly-PolyW! , lamina, 7
Q-, m oxide film, 7cm2... nitride film, 70-3...
- Oxide film, 7b... Gate insulating film, 9... Source,
drain area.

Claims (1)

[Claims] A step of forming at least a first insulating film on the entire surface of the semiconductor substrate, a step of forming a first conductive film on the first insulating film, and a step of removing a partial region of the first conductive film. a step of selectively implanting ions into the partial region; a step of removing the first insulating film remaining in the partial region; and a step of forming a second insulating film over the entire surface. , forming a second conductive film on the second insulating film.