JPH03142857A - Wiring method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To restrict the detour of wiring between blocks to the minimum degree and to reduce the interconnecting area by using the different wiring layers for the wiring in a circuit cell or in a circuit block and between the circuit cells or between the circuit blocks. CONSTITUTION:For example, in a semiconductor integrated circuit constituted of three block levels, a plurality of circuit cells 1 are assembled, and a circuit block 2 at the first block level is formed. Then, a plurality of the circuit blocks 2 at the first block level are assembled, and a circuit block 3 at the second block level which is the upper level is formed. Then, a plurality of the circuit blocks 3 at the second block level are assembled, and a circuit block 4 at the third level which is the upper level is further formed. Thus, the intended integrated circuit can be obtained. That is, the wirings in the circuit cell or in the circuit block are performed by using the two layers, and the interconnections between the circuit cells or between the circuit blocks are performed by using the two layers thereon.

Description

[Detailed description of the invention]

[Object of the Invention] (Industrial Application Field) The present invention relates to a wiring method for a building block standard cell type or gate array type semiconductor integrated circuit using multilayer wiring. (Prior Art) A building block method has been proposed as a wiring design method for a standard cell type or gate array type semiconductor integrated circuit. This is achieved by configuring circuits for logic functions and memory functions in generally rectangular areas called circuit blocks, arranging multiple circuit blocks within a chip, and wiring each block. The circuit operation obtained is as follows. As a circuit block, RAM/R
It is possible to freely handle anything composed of OM, PLA, ALU, CPU, or polycell. FIG. 4 shows a schematic diagram when this building block method is applied to two-layer wiring. The chip is divided into a plurality of circuit blocks 5, which are element regions, and a wiring region 6 between each circuit block 5. The wiring area 6 is an area where wiring for connecting input and output terminals of each circuit block 5 is provided. The wiring within each circuit block 5 and between the circuit blocks 5 uses first layer wiring and second layer wiring. For example, the first layer wiring uses the horizontal direction (horizontal direction), and the second layer wiring uses the vertical direction (horizontal direction). vertical) wiring is assigned. In such a semiconductor integrated circuit, wiring routes are determined by the following procedure. That is, (1) Arrangement and wiring within each block are performed. ■Connect the first contact 7 to the circuit block 5 for wiring between blocks.
Determine on the boundary of . ■Connection area 6 to multiple channels 8
A second contact 9 is determined on the boundary of the channel 8 based on the positional relationship of the contacts 7 of the two circuit blocks 5 to be connected. (2) Wiring is performed from the first contact 7 of one circuit block 5 through the second contact 9 to the other first contact 7 to be connected. ■Repeat the same procedure for other wiring routes. In the wiring method for a two-layer semiconductor integrated circuit as described above, when providing the first contact 7, wiring is required from a predetermined position inside the circuit block 5 to the boundary of the circuit block 5, and in this case, the wiring has already been completed. The wiring route was bypassed, which caused an increase in the wiring area. Furthermore, when wiring between each circuit block 5, the upper part of the circuit block 5 cannot be used and only the wiring area 6 can be used, which similarly increases the wiring area and makes the wiring between the circuit blocks 5 complicated. It had become. This increase in wiring area leads to an increase in chip area, making it impossible to realize fine semiconductor integrated circuits, and the increased complexity of wiring requires time to design wiring, and it is difficult to realize reliable semiconductor integrated circuits. There was a problem that I couldn't get it. (Problems to be Solved by the Invention) As described above, in the conventional building block type semiconductor integrated circuit wiring design method, connection terminals are provided at the boundaries of each circuit block. In this case, the wiring must be routed by detouring the route that has already been routed, resulting in an increase in the wiring area and complication of the wiring. In addition, when wiring between each circuit block, only the wiring area is used and the area above the circuit block is not used, so the increase in the wiring area and the complexity of the wiring also lead to an increase in the chip area and the need for fine semiconductor integration. The circuit cannot be realized. It also makes the wiring more complicated. This increase in wiring area and complication of the wiring requires time to design the wiring, making it impossible to obtain a reliable semiconductor integrated circuit. There was a problem. It is an object of the present invention to provide a method for designing wiring for a semiconductor integrated circuit that solves these problems.

[Structure of the invention]

(Means for Solving the Problems) The present invention has been made in view of the above circumstances. The present invention provides a wiring method for a semiconductor integrated circuit, characterized in that wiring within a circuit cell or circuit block and wiring between circuit cells or circuit blocks are realized using different wiring layers. Further, the second invention provides a method for determining a wiring connection terminal within a circuit cell or a circuit block and performing wiring between the circuit cells or between the circuit blocks. Select the block and
Extract multiple wiring connectable terminals within this selected circuit cell or circuit block, and extract wiring board connection terminals within a circuit cell or circuit block other than this selected circuit cell or circuit block. , the wiring connection terminal is determined from among the plurality of wiring connectable terminals based on the positional relationship between the plurality of wiring connectable terminals and the wiring board connection terminal or the already determined wiring connection terminal and the congestion level of the wiring. The present invention provides a wiring method for semiconductor integrated circuits. (Function) As described above, according to the first invention, wiring within a circuit cell or circuit block is performed using two layers, and furthermore, two layers above the wiring are used to conduct wiring between circuit cells or between circuit blocks. By repeating this method, it is possible to perform multilayer wiring by expanding the two-layer wiring concept.
Since wiring design is simplified and facilitated, unwired circuits can be prevented and a reliable semiconductor integrated circuit can be obtained. Furthermore, since the wiring layers within a block and between blocks are different, the tops of the blocks can also be used for inter-block wiring, reducing the wiring area and miniaturizing the semiconductor integrated circuit. Further, by making the wiring distribution uniform in each two-layer wiring, it is possible to alleviate the problem of the step difference that occurs in multilayer wiring. Also, 1st. According to the second invention, there is no need to provide a connection position from within a block to an inter-block wiring on a block boundary, and the optimum connection position can be selected, so detours can be minimized and the wiring area can be reduced. As a result, fine semiconductor integrated circuits can be obtained. (Example) Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a semiconductor integrated circuit to which the wiring method of the present invention is applied. Here, a semiconductor integrated circuit composed of three block levels will be considered. A plurality of circuit cells 1 (hereinafter abbreviated as cells) are assembled to form a circuit block 2 at a first block level. Further, a plurality of circuit blocks 2 at the first block level are assembled to form a circuit block 3 at the second block level at the upper level. Further, a plurality of circuit blocks 3 at the second block level are assembled to form a circuit block 4 at a third block level at a higher level, thereby making it possible to obtain a desired semiconductor integrated circuit. For example, when considering a 16-bit multiplier, cell 1 is NAND. A NOR circuit is considered, and as the circuit block 2 at the first block level, an ADDER circuit formed using the cell 1 is considered.
, LATCH circuit, etc. can be considered. Furthermore, as the circuit block 3 at the second block level,
A shift register formed using the circuit block 2 of the first block level, a 4-bit multiplier circuit, etc. can be considered. Furthermore, a 16-bit multiplier circuit formed using the circuit block 3 of the second block level is obtained as the circuit block 4 of the third block level. The case where the wiring method of the present invention is applied to a semiconductor integrated circuit having the above structure will be described below. First, the interior of the cell 1 is wired using the first and second wiring layers. Here, for example, the first layer is allocated to horizontal wiring, and the second layer is allocated to vertical wiring. At this time, regarding the wiring of the net connecting to other cells 1, it is not necessary to extend the wiring to the boundary of the cell 1 as in the conventional case. Further, a plurality of cells 1 are collected and arranged at predetermined positions to form a circuit block 2 at a first block level. Here, wiring between cells 1 within circuit block 2 at the first block level is performed using the third and fourth wiring layers. The wiring within each cell 1 and the wiring between a plurality of cells 1 in the circuit block 2 at the first block level consisting of cells 1 are in different wiring layers, so the wiring between cells 1 cannot pass over the cell 1. can. Further, since the terminal position for connecting a plurality of cells 1 does not need to be provided at the boundary of the cells 1, the optimum position can be selected, and a detour of the wiring of the net spanning between the cells 1 can be avoided. Furthermore, when wiring uses two sets of wiring layers: the first layer, the second layer, and the third layer and the fourth layer, by avoiding local concentration of wiring, it is possible to avoid steps that occur in multilayer wiring. . Further, a plurality of circuit blocks 2 at the first block level are assembled and arranged at a predetermined position to form a circuit block 3 at the second block level. here. Wiring between a plurality of circuit blocks 2 at the first block level within a circuit block at the second block level is performed using the fifth and sixth wiring layers. Here, similarly to the above, the wiring within each first block level circuit block 2 and the second line consisting of the first block level circuit block 2 are connected.
The wiring between the plurality of circuit blocks 2 at the first block level within the circuit block 3 at the block level is on different wiring layers, so the wiring between the circuit blocks 2 at the first block level is on the circuit block 2 at the first block level. can pass through. Also, the circuit block 2 at the first block level
Since it is not necessary to provide the terminal position at the boundary of the circuit block 2 of the first block level when connecting between the terminals, the optimal position can be selected, and the position of the terminal can be selected between the circuit blocks 2 and
You can avoid detours for net wiring that straddles the network. Similarly, a plurality of circuit blocks 3 at the second block level are assembled and arranged at predetermined positions to form a circuit block 4 at the third block level. Here, using the wiring layers of the 7th and 8th layers, the circuit block 4 of the 3rd block level is constructed.
Wiring is performed between a plurality of circuit blocks 3 at the second block level within the circuit. Through the above steps, a desired semiconductor integrated circuit can be obtained. According to the wiring method for semiconductor integrated circuits as described above, the wiring within a cell or circuit block and the wiring between cells or circuit blocks use different wiring layers, so the connection terminal position of the wiring between blocks is In addition to being provided above or on blocks, the area above cells or blocks can also be used for wiring between cells or blocks, so detours of wiring between cells or blocks can be minimized. Further, by making the wiring uniform in each of the intra-block wiring and the inter-block wiring, it is possible to reduce the level difference in the wiring layer. Note that the number of block levels does not necessarily have to be three, and may be two or four or more depending on the circuit configuration. Figure 2 is a schematic configuration diagram illustrating a method for determining terminals when wiring between cells or blocks of a semiconductor integrated circuit to which the wiring method of the present invention is applied, and Figure 3 is a diagram for determining terminal positions. 2 is a flowchart showing a processing procedure. Based on FIG. 2, a case will be described in which wiring is performed between a plurality of circuit blocks 2 at the first block level within the circuit block 3 at the second block level. A plurality of first block level circuit blocks 21.2.
2. 2. 2. 2. 2. 2 Nona 28458
7g Circuit block 2. 2. 2. The arrangement between 2
Suppose you want to do 4 5 8 lines. First, first, connect multiple first
Block level circuit block 21°2, -2.2.2
．． 2.2.2, perform the 2345678 arrangement. (Step 301) Next, each circuit block 2. 2. 2. 2845, wiring board connection terminals (hereinafter abbreviated as temporary connection terminals) 100,
Determine 400,500.800. (Step 302) Next, in order to determine wiring connection terminals (hereinafter abbreviated as connection terminals) of circuit block 2, other circuit blocks 2, 2. −2 and placement
4 5 8 wire connectable terminal (hereinafter abbreviated as connectable terminal) 101,
102. 103. 104. 105°106.10
Set 7. Next, for circuit blocks for which connection terminals have already been determined among other circuit blocks 2, 25, and 28, this connection terminal is extracted, and for circuit blocks that have not been determined, temporary connection terminals are extracted. Set. In this case, circuit block 2. 2. 2 is 4
5 8 Since the connection terminal has not yet been determined, the temporary connection terminal 40
Set 0,500.800. Next, circuit block 2
Connectable terminals 101, 102° 103, 104, 1
05, 106.107 and circuit blocks 2, 2.28 as connection terminals in circuit block 2, based on the positional relationship of 400°5 500.800 and the degree of congestion in the 5th and 6th layers for wiring. 107 is determined. (Step 303) Next, in order to determine the connection terminals of the circuit block 24, connectable terminals 4o1゜402, 403, 404, . Set. Next, among the other circuit blocks, the connection terminal 107 is set for the circuit block 21 whose connection terminal has already been determined, and the temporary connection terminal 500, 800 is set for the circuit block 2.2B whose connection terminal has not yet been determined. circuit block 2
4 connectable terminals 401, 402, 403, 404 and circuit block 2, connection terminal 107 of circuit block 2.
The connection terminal 401 is determined as the connection terminal in the circuit block 24 based on the positional relationship of the temporary connection terminals 500.8 and 800 and the degree of congestion in the fifth and sixth layers where wiring is performed. The same procedure is repeated for circuit block 2.
2 connection terminal 501°8801 is determined. (Step 304> The above is a description of one wiring net, but the connection terminals are determined using the same procedure for other wiring nets. (Snap 305)
) Next, by wiring between these connection terminals, a plurality of first
Wiring between circuit blocks 2 at block level can be realized. (Step 306) According to the connection terminal determination method and wiring method for wiring between blocks of a semiconductor integrated circuit as described above, the wiring in the circuit block 2 at the first block level and the plurality of circuits at the first block level Since the wiring between the blocks 2 is in different wiring layers, there is no need to provide connection terminals for inter-block wiring on the boundaries of the circuit blocks 2 at the first block level, and an optimal connection position can be selected. Also, wiring can "pass" over the circuit block at the first block level. Therefore, detours of the wiring can be minimized, so the wiring area can be reduced, and a fine semiconductor integrated circuit can be obtained. Although the wiring method between a plurality of circuit blocks 2 at the first level within the circuit block 3 at the second block level has been described here, it is not limited to this, and the wiring method within the circuit block 2 at the first block level is explained. Wiring between multiple cells 1,
A plurality of second circuits within the circuit block 4 at the third block level.
Needless to say, the present invention can also be applied to wiring between circuit blocks 3 at a block level or wiring between circuit blocks at a higher level. [Effects of the Invention] As described above, according to the present invention, since the wiring layer within a block and the wiring layer between blocks are different, the plotted area can also be used for wiring between blocks, and the contact position of block wiring can be By considering the relationship with the connection position of other blocks when selecting the contact position of the inter-block wiring, it is possible to minimize the detour of the inter-block wiring and reduce the wiring area. As a result, fine semiconductor integrated circuits can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a wiring method for a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a wiring method for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 3 is a flowchart showing a processing flow of a wiring method according to an embodiment of the present invention, and FIG. 4 is a diagram showing a conventional wiring method for a semiconductor integrated circuit. In the figure, 1...Cell, 2...Circuit block at first block level, 3...Circuit block at second block level, 4
... Third block level circuit block, 5... Circuit block, 6... Wiring area, 7... First contact, 8... Channel, 9... Second contact, 10
,40゜50.80...Block connected to net n, 100.400,500,800...Temporary connection terminal,
101.102,103,104,106,107...
- Terminals that can connect net n of block 10 with other blocks, 401, 501, 801... Connection terminals of blocks 40, 50, and 80 that connect to net n.

Claims (2)

[Claims] (1) When wiring multiple circuit cells or circuit blocks to form an upper level circuit block, the wiring within the circuit cell or circuit block and the wiring between the circuit cells or between the circuit blocks is A wiring method for a semiconductor integrated circuit, which is realized using different wiring layers. (2) When determining a wiring connection terminal within the circuit cell or the circuit block and wiring between the circuit cells or between the circuit blocks, the circuit cell or the circuit block for which the wiring connection terminal is scheduled to be determined. , extract a plurality of wiring connectable terminals within the selected circuit cell or circuit block, and extract a plurality of terminals that can be connected to wiring within the selected circuit cell or circuit block, and The wiring board connection terminals are extracted in the plurality of wiring connectable terminals based on the positional relationship between the plurality of wiring connectable terminals and the wiring board connecting terminal or the already determined wiring connection terminal and the degree of wiring congestion. 2. The wiring method for a semiconductor integrated circuit according to claim 1, wherein the wiring connection terminal is determined from the following.