JP2851079B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing an integrated circuit based on a desired logic. A plurality of identical functions provided in a cell and having no difference in operation are provided. When trying to obtain the desired logic by connecting a plurality of cells using terminals, the overall connection efficiency can be improved without intersecting the individual connection relationships of each functional terminal in the placement and wiring process. The purpose of the present invention is to provide a method of manufacturing a semiconductor integrated circuit, which can reduce the number of repair steps after the placement and wiring processing and can carry out LSI development in a short period of time. A semiconductor integrated circuit comprising a first cell having a plurality of the same function terminals and a plurality of second cells connected to any of the function terminals of the cell; All the second The first cell and each second cell as a net connected to only one of the functional terminals of the first cell.
After arranging the cells, among the arranged second cells, those adjacent to the functional terminals to be used are grouped together, and a wiring path connecting each functional terminal to each group is determined. Configured.

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an integrated circuit based on desired logic.

In recent years, with the increase in the degree of integration of LSIs, it is required to build more logic circuits in a limited area on a substrate.

For this reason, it is necessary to be able to simply define the unique logic desired by the user who is increasing, and to realize efficient wiring in the wiring processing.

2. Description of the Related Art Conventionally, when arranging cells constituting a semiconductor integrated circuit based on logical connection information designated by a user, the arrangement processing of cells constituting the logic is faithfully performed in accordance with the logical connection information. I have done it. At this time, when a plurality of cells are connected to a cell having the same function terminal which has no difference in operation, due to restrictions caused by physical conditions (in the case of an output terminal, the upper limit of the output drive capability), If a plurality of terminals must be used in the same cell, the user must define different connection relationships (hereinafter, referred to as nets) for these terminals.

That is, as shown in FIG. 6, when a plurality of driven cells C1 to C12 are connected to a driving cell C0 having two output terminals # 1 and # 2 that output the same signal, the physical condition (output driving capability Due to the restrictions imposed by the upper limit), these output terminals # 1 and # 2 must be used, and the user must use separate nets for these output terminals # 1 and # 2.
N1 and N2 will be defined.

Then, when performing the arrangement processing of the driving cell C0 and the driven cells C to C12 based on the logical connection information specified by the user, the driven cells C1 to C12 are arranged in an intersecting positional relationship as shown in FIG. After this arrangement processing, a wiring path is determined in the wiring processing.

[Problems to be Solved by the Invention] However, in the wiring process, both nets N1 and N2 are treated as separate logics, and the output terminals # 2 are connected to the output terminals # 1 so that the driven cells C1 to C6 are connected to the output terminals # 1. Driven cell C7 ~
The wiring route is determined so that C12 is connected. As a result, as shown in FIG. 7, the wiring of both nets N1 and N2 becomes a wiring pattern crossing each other as shown by a broken line frame in each wiring region LT, and the wiring density due to these wirings increases in the same wiring region LT. I do. The more complicated the intersection of the wirings of the two nets N1 and N2, the greater the degree of congestion of the wiring at the intersection of the two nets N1 and N2, resulting in a problem of lowering the wiring efficiency of the entire circuit.

The present invention has been made to solve the above problems, and an object of the present invention is to connect a plurality of cells by using a plurality of identical function terminals provided in the cells and having no difference in operation. When trying to obtain the desired logic, it is possible to improve the overall wiring efficiency without intersecting the individual connection relationship of each functional terminal in the placement and wiring processing, and to greatly reduce the number of repair steps after the placement and wiring processing. It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit, which can reduce LSI development in a short period of time.

[Means for Solving the Problems] First, among a large number of cells formed on a substrate, all the second cells connected to the first cell are replaced by only one of the functional terminals of the first cell. 1st cell and 2nd cell are arranged as a net connected to. After that, among the arranged second cells, those adjacent to the functional terminals to be used are grouped. Then, a wiring path connecting each functional terminal and each group is determined.

[Operation] Since the determination of the wiring route performed after the cell arrangement processing is performed in a group formed by adjacent second cells,
Wiring paths of different groups do not cross each other, and wiring efficiency is improved.

Further, since each group constituted by adjacent second cells is connected to the function terminal of the first cell closest to the group, unnecessary sneaking of wiring from the function terminal can be avoided.

[Examples] Hereinafter, an example that embodies the present invention will be described.

FIG. 1 is a process diagram showing a cell placement process in one embodiment of the present invention, FIG. 2 is a process diagram showing a wiring process in one embodiment, FIG. 3 is a logic diagram created by a user in one embodiment, FIG. 4 is a logic diagram after the placement / wiring processing, and FIG. 5 is a flowchart for explaining the placement / wiring processing in the present invention. The same components as those in FIGS. explain.

This embodiment describes the avoidance of a drive cell C0 having two output terminals Χ1 and Χ2 for outputting the same signal as a first cell and a plurality of driven cells C1 to C12 as a second cell. I do.

Now, before performing the placement / wiring processing,
As shown in the figure, it is assumed that there is a logic diagram in which all the driven cells C1 to C12 are defined as one net N0 connected to only the output terminal Χ.

Based on this logic diagram, as shown in FIG. 1, the automatic placement processing of the driving cell C0 and the driven cells C1 to C12 is performed on a substrate (not shown). In this arrangement process, the driven cell C1
To C12 as one net N0, the degree of freedom in the arrangement of the driven cells C1 to C12 is increased, and the arrangement is well-balanced.

After the placement processing, among the placed driven cells C1 to C12,
Connect the terminals that are close to the output terminals # 1 and # 2 to the terminals # 1 and # 2.
Grouping within the number of cells connectable to 2. In this embodiment, the driven cells C1, C2, C10, C11, and C12 are group G1, and the driven cells C4, C5, C6, C7, C8, and C9 are group G2. Next, output terminals # 1 and # 2 close to the groups G1 and G2 are allocated, and a new net N1 is formed by the output terminal # 1 and the group G1 as shown in FIG. Configures the net N2.

Then, by performing automatic wiring processing in each of the newly configured nets N1 and N2, a wiring route in each of the nets N1 and N2 is determined as shown in FIG.

As described above, in the present embodiment, after performing the process of arranging the driven cells C1 to C12, the driven cells adjacent to the output terminals # 1 and # 2 form groups G1 and G2, and the groups G1 and G2 The output terminals # 1 and # 2 are assigned to form nets N1 and N2. Since the wiring processing is performed in each of the nets N1 and N2, the wiring paths of the nets N1 and N2 do not intersect, and the wiring efficiency can be improved. As a result, it is possible to significantly reduce the number of repair steps after the placement / wiring processing and to perform LSI development in a short time.

Further, in this embodiment, the nets N1 and N2 are configured by allocating the nearest output terminals # 1 and # 2 to the groups G1 and G2, so that wiring from the output terminals # 1 and # 2 to each group G1 and G2 is unnecessary. Can be avoided.

[Effects of the Invention] As described above in detail, according to the present invention, a plurality of cells are connected to each other by using a plurality of identical function terminals having no difference in operation provided in the cells. When trying to obtain logic, the overall connection efficiency can be improved without intersecting the individual connection relationship of each functional terminal in the placement and wiring processing, and the number of repair steps after the placement and wiring processing is greatly reduced. There is an excellent effect that LSI development can be performed in a short period of time by reducing the amount.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a cell placement process in one embodiment of the present invention, FIG. 2 is a process diagram showing a wiring process in one embodiment, FIG. 3 is a logic diagram created by a user in one embodiment, FIG. 4 is a logic diagram after the placement and wiring processing, FIG. 5 is a flowchart for explaining the placement and wiring processing in the present invention, FIG. 6 is a logic diagram created by a user in the past, and FIG. FIG. 9 is a diagram illustrating a placement / wiring result. In the figure, C0 is a driving cell as a first cell, C1 to C12 are driven cells as a second cell, N1 and N2 are nets, and # 1 and # 2 are output terminals as terminals having the same function.

Claims (1)

(57) [Claims] 1. A first cell having a plurality of identical functional terminals among a plurality of cells formed on a substrate, and a plurality of second cells connected to any of the functional terminals of the cells. Wherein all second cells connected to the first cell are connected to only one of the functional terminals of the first cell as a net, and the first cell and each After arranging the second cells, among the arranged second cells, those adjacent to the functional terminals to be used are grouped together, and a wiring route connecting each functional terminal to each group is determined. A method for manufacturing a semiconductor integrated circuit.