JPH03139865A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH03139865A JPH03139865A JP27761089A JP27761089A JPH03139865A JP H03139865 A JPH03139865 A JP H03139865A JP 27761089 A JP27761089 A JP 27761089A JP 27761089 A JP27761089 A JP 27761089A JP H03139865 A JPH03139865 A JP H03139865A
- Authority
- JP
- Japan
- Prior art keywords
- cells
- cell
- wiring
- terminals
- functional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 13
- 238000012937 correction Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 241001453327 Xanthomonadaceae Species 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
[概要]
半導体集積回路の製造方法に係り、詳しくは所望の論理
に基づく集積回路の製造方法に関し、セルに設けられた
動作上は何ら違いのない複数個の同一機能端子を使用し
て複数個のセルを接続して所望する論理を得ようとする
際、配置・配線処理において各機能端子の個別な接続関
係に交差を生じさせず、全体の配線効率を向上でき、配
置・配線処理後における修正工数を大幅に削減してLS
I開発を短期間で行なうことができる半導体集積回路の
製造方法を提供することを目的とし、基板上に形成され
た多数のセルのうち、同一機能端子を複数個有する第1
のセルと、このセルの機能端子のいずれかに接続される
複数個の第2のセルとで構成される半導体集積回路にお
いて、前記第1のセルに接続される全第2のセルを第1
のセルの機能端子のいずれか1つのみに接続されるネッ
トとして前記第1のセル及び各第2のセルの配置を行な
った後、配置された各第2のセルのうち、使用される各
機能端子に近接したもの同士をグループ化し、各機能端
子と各グループとを結ぶ配線経路を決定するように構成
した。[Detailed Description of the Invention] [Summary] This invention relates to a method for manufacturing a semiconductor integrated circuit, more specifically, a method for manufacturing an integrated circuit based on a desired logic, in which a plurality of identical functions provided in a cell with no operational differences are provided. When trying to obtain the desired logic by connecting multiple cells using terminals, it is possible to improve the overall wiring efficiency by eliminating intersections between the individual connection relationships of each functional terminal during placement and wiring processing. , LS with a significant reduction in the number of corrections after placement and wiring processing.
The purpose of the present invention is to provide a method for manufacturing semiconductor integrated circuits that enables I development in a short period of time.
In a semiconductor integrated circuit comprising a cell and a plurality of second cells connected to any of the functional terminals of this cell, all the second cells connected to the first cell are connected to the first cell.
After arranging the first cell and each second cell as a net connected to only one of the functional terminals of the cells, each of the second cells to be used is Components that are close to a functional terminal are grouped together, and a wiring route connecting each functional terminal and each group is determined.
[産業上の利用分野]
本発明は、半導体集積回路の製造方法に係り、詳しくは
所望の論理に基づく集積回路の製造方法に関するもので
ある。[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing an integrated circuit based on desired logic.
近年、LSIの高集積化に伴って、基板上の限られた領
域内により多くの論理回路を作り込むことが要求されて
いる。In recent years, as LSIs have become more highly integrated, there has been a demand for more logic circuits to be built into a limited area on a substrate.
このため、増加傾向にあるユーザーが所望する独自の論
理を簡潔に定義できるとともに、配線処理において効率
的な配線を実現することが必要となっている。For this reason, there is a need for an increasing number of users to be able to easily define their own desired logic and to achieve efficient wiring in wiring processing.
[従来の技術]
従来、ユーザが指定した論理接続情報に基づいて半導体
集積回路を構成する各セルの配置処理を行なう際、この
論理接続情報に対し、その論理を構成するセルの配置処
理を忠実に行なっている。[Prior Art] Conventionally, when placing each cell constituting a semiconductor integrated circuit based on logical connection information specified by a user, the placement process of the cells constituting the logic has been faithfully performed based on the logical connection information. I am doing it.
この時、動作上は何ら違いのない同一機能端子を有する
セルに対して複数のセルを接続する場合、その物理的条
件により生じる制約(出力端子の場合、出力ドライブ能
力の上限)のため、これらの端子を同一セルの中で複数
個使用しなければならない場合には、ユーザはこれらの
端子に対してそれぞれ別々の接続関係(以下、ネットと
いう)を定義しなければならない。At this time, when connecting multiple cells to cells that have terminals with the same function that have no operational differences, there are constraints caused by the physical conditions (in the case of output terminals, the upper limit of output drive capability). If a plurality of terminals must be used in the same cell, the user must define separate connection relationships (hereinafter referred to as nets) for each of these terminals.
即ち、第6図に示すように同一信号を出力する2つの出
力端子XI、X2を有する駆動セルCOに対して複数の
従動セル01〜CI2を接続する場合、その物理的条件
(出力ドライブ能力の上限)により生じる制約のため、
これらの出力端子XI。That is, when a plurality of driven cells 01 to CI2 are connected to a driving cell CO having two output terminals XI and X2 that output the same signal as shown in FIG. Due to the constraints imposed by
These output terminals XI.
X2を使用しなければならず、ユーザはこれらの出力端
子XI、X2に対してそれぞれ別々のネットNl、N2
を定義することとなる。X2 must be used, and the user has to create separate nets Nl, N2 for these output terminals XI, X2, respectively.
will be defined.
そして、ユーザの指定した論理接続情報に基づいて駆動
セルCO及び従動セルC1〜C12の配置処理を行なう
場合、第7図に示すように各従動セル01〜CI2は交
差した位置関係に配置され、この配置処理後に配線処理
にて配線経路が決定される。When the drive cell CO and the driven cells C1 to C12 are arranged based on the logical connection information specified by the user, the driven cells 01 to CI2 are arranged in an intersecting positional relationship as shown in FIG. After this placement process, a wiring route is determined in a wiring process.
[発明が解決しようとする課題]
ところが、配線処理では両ネットNl、N2が別々の論
理として扱われ、出力端子XIに対して従動セルCl−
C6が接続されるように、出力端子X2に対して従動セ
ルC7〜C12が接続されるように配線経路が決定され
る。その結果、第7図に示すように両ネットNl、N2
の配線は各配線領域LTにおいて破線枠で示すように互
いに交差した配線パターンとなり、同一配線領域LT内
でこれらの配線による配線密度が増加する。そして、両
ネットNl、N2の配線の交差状態が複雑になればなる
ほど、両ネットN1.N2の交差部における配線の混雑
度が大きくなり、回路全体の配線効率が低下するという
問題点がある。[Problems to be Solved by the Invention] However, in wiring processing, both nets Nl and N2 are treated as separate logics, and the driven cell Cl- is connected to the output terminal XI.
The wiring route is determined so that the driven cells C7 to C12 are connected to the output terminal X2 such that C6 is connected to the output terminal X2. As a result, as shown in Fig. 7, both nets Nl and N2
In each wiring region LT, the wirings form a wiring pattern that intersects with each other as shown by the broken line frame, and the wiring density due to these wirings increases within the same wiring region LT. The more complicated the crossing state of the wirings of both nets Nl and N2, the more complicated the crossing state of the wirings of both nets N1 and N2. There is a problem in that the degree of wiring congestion at the intersection of N2 increases and the wiring efficiency of the entire circuit decreases.
本発明は上記問題点を解決するためになされたものであ
って、その目的はセルに設けられた動作上は何ら違いの
ない複数個の同一機能端子を使用して複数個のセルを接
続して所望する論理を得ようとする際、配置・配線処理
において各機能端子の個別な接続関係に交差を生じさせ
ず、全体の配線効率を向上でき、配置・配線処理後にお
ける修正工数を大幅に削減してLSI開発を短期間で行
なうことができる半導体集積回路の製造方法を提供する
ことにある。The present invention was made to solve the above problems, and its purpose is to connect a plurality of cells using a plurality of terminals with the same function provided in the cells and having no operational differences. When trying to obtain the desired logic using a layout/wiring process, the overall wiring efficiency can be improved by eliminating the possibility of crossing over the individual connection relationships of each functional terminal during the placement/wiring process, and greatly reducing the number of corrections required after the placement/wiring process. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can reduce the number of LSIs and develop LSIs in a short period of time.
[課題を解決するための手段]
まず、基板上に形成された多数のセルのうち、第1のセ
ルに接続される金弟2のセルを第1のセルの機能端子の
いずれか1つのみに接続されるネットとして第1のセル
及び各第2のセルの配置を行なう。この後、配置された
各第2のセルのうち、使用される各機能端子に近接した
もの同士をグループ化する。そして、各機能端子と各グ
ループとを結ぶ配線経路を決定する。[Means for solving the problem] First, among a large number of cells formed on a substrate, the cell of Kintetsu 2 connected to the first cell is connected to only one of the functional terminals of the first cell. The first cell and each second cell are arranged as a net connected to the first cell and each second cell. Thereafter, among the second cells arranged, those close to each functional terminal to be used are grouped. Then, a wiring route connecting each functional terminal and each group is determined.
[作用]
セル配置処理後に行なう配線経路の決定は、近接する第
2のセル同士で構成したグループ内で行なわれるため、
異なるグループの配線経路が互いに交差することはなく
、配線効率が向上される。[Operation] Since the wiring route is determined after the cell placement process is performed within the group made up of adjacent second cells,
The wiring paths of different groups do not cross each other, and wiring efficiency is improved.
又、近接する第2のセル同士で構成された各グループは
、そのグループに最寄りの第1のセルの機能端子に接続
されるので、その機能端子からの配線の不要な廻り込み
を回避できる。Further, each group composed of adjacent second cells is connected to the functional terminal of the first cell closest to the group, so that unnecessary wiring from the functional terminal can be avoided.
[実施例] 以下、本発明を具体化した一実施例について説明する。[Example] An embodiment embodying the present invention will be described below.
第1図は本発明の一実施例におけるセル配置処理を示す
工程図、第2図は一実施例における配線処理を示す工程
図、第3図は一実施例においてユーザが作成する論理図
、第4図は配置・配線処理後における論理図、第5図は
本発明における配置・配線処理を説明するためのフロー
チャートであり、第6,7図と同様の構成については同
一の符号を付して説明する。FIG. 1 is a process diagram showing cell placement processing in one embodiment of the present invention, FIG. 2 is a process diagram showing wiring processing in one embodiment, and FIG. 3 is a logic diagram created by the user in one embodiment. FIG. 4 is a logic diagram after placement and wiring processing, and FIG. 5 is a flowchart for explaining placement and wiring processing in the present invention. Components similar to those in FIGS. 6 and 7 are given the same reference numerals. explain.
本実施例は第1のセルとして同一信号を出力する2つの
出力端子XI、X2を有する駆動セルCOと、第2のセ
ルとしての複数個の従動セルC1−CI2とで構成され
る回路について説明する。This embodiment describes a circuit that is composed of a driving cell CO having two output terminals XI and X2 that outputs the same signal as a first cell, and a plurality of driven cells C1 to CI2 as second cells. do.
今、配置・配線処理を行なう前に、ユーザにより第3図
に示すように、全従動セルCl−C12が出力端子XI
のみに接続される1つのネットNOとして定義した論理
図があるとする。Now, before performing the placement and wiring processing, the user has set all the driven cells Cl-C12 to the output terminals XI as shown in FIG.
Suppose we have a logic diagram defined as one net NO connected only to
この論理図に基づき、第1図に示すように基板(図示路
)上において駆動セルCO及び従動セルCl−CI2の
自動配置処理を行なう。この配置処理において従動セル
C1−C12を1つのネットNOとして取り扱うため、
各従動セルC1〜C12の配置の自由度が高くなり、バ
ランスのよい配置となる。Based on this logic diagram, the driving cells CO and driven cells Cl-CI2 are automatically placed on the substrate (the path shown in the figure) as shown in FIG. In this placement process, the driven cells C1-C12 are treated as one net NO.
The degree of freedom in arranging each of the driven cells C1 to C12 is increased, resulting in a well-balanced arrangement.
配置処理後、配置された各従動セルC1−CI2のうち
、各出力端子XI、X2に近接したもの同士を各端子X
I、X2に接続可能なセル数以内でグループ化する。本
実施例では従動セルC1゜C2,C3,CIO,C11
,C12をグループGlとし、従動セルC4,C5,C
6,C7゜C8,C9をグループG2とする。次にグル
ープGl、G2に対して近接した出力端子Xi、 N2
を割り振り、第4図に示すように出力端子XIとグルー
プG1とで新たにネットN1を構成するとともに、出力
端子X2とグループG2とでネットN2を構成する。After the placement process, among the placed driven cells C1-CI2, those close to each output terminal XI, X2 are connected to each terminal X.
Group cells within the number of cells that can be connected to I and X2. In this embodiment, the driven cells C1゜C2, C3, CIO, C11
, C12 as group Gl, and driven cells C4, C5, C
6, C7° C8, C9 are group G2. Next, output terminals Xi and N2 close to groups Gl and G2
As shown in FIG. 4, output terminal XI and group G1 constitute a new net N1, and output terminal X2 and group G2 constitute net N2.
そして、新たに構成された各ネットNl、 N2内にお
いて自動配線処理を行なうことによって、第2図に示す
ように各ネットNl、N2における配線経路が決定され
る。Then, by performing automatic wiring processing within each of the newly constructed nets Nl and N2, the wiring routes in each of the nets Nl and N2 are determined as shown in FIG.
このように、本実施例では各従動セルC1〜C12の配
置処理を行なった後、各出力端子XI。In this manner, in this embodiment, after the arrangement processing of each of the driven cells C1 to C12 is performed, each output terminal XI.
N2に近接する従動セル同士でグループGl。Driven cells close to N2 form a group Gl.
G2を形成し、両グループGl、G2に近接する出力端
子XI、X2を割り振ってネットN1゜N2を構成した
。そして、各ネットNl、N2内において配線処理を行
なうようにしたので、各ネットNl、N2の配線経路が
交差せず、配線効率を向上することができる。これによ
り、配置・配線処理後における修正工数を大幅に削減し
てLSI開発を短期間で行なうことができる。G2 was formed, and output terminals XI and X2 close to both groups Gl and G2 were allocated to form nets N1°N2. Since the wiring process is performed within each net Nl, N2, the wiring routes of each net Nl, N2 do not intersect, and wiring efficiency can be improved. As a result, the number of correction steps after placement and wiring processing can be significantly reduced, and LSI development can be carried out in a short period of time.
又、本実施例においては、グループGl、 G2に対し
て最寄りの出力端子Xi、X2を割り振ってネットNl
、N2を構成したので、出力端子XI、X2から各グル
ープGl、G2への配線の不要な廻り込みを回避できる
。In addition, in this embodiment, the nearest output terminals Xi and X2 are allocated to the groups Gl and G2, and the net Nl is
, N2, it is possible to avoid unnecessary wiring from the output terminals XI, X2 to the respective groups G1, G2.
[発明の効果]
以上詳述したように、本発明によればセルに設けられた
動作上は何ら違いのない複数個の同一機能端子を使用し
て複数個のセルを接続して所望する論理を得ようとする
際、配置・配線処理において各機能端子の個別な接続関
係に交差を生じさせず、全体の配線効率を向上すること
ができ、配置・配線処理後における修正工数を大幅に削
減してLSI開発を短期間で行なうことができる優れた
効果がある。[Effects of the Invention] As detailed above, according to the present invention, a desired logic can be realized by connecting a plurality of cells using a plurality of terminals with the same function provided in the cells and having no operational differences. When trying to achieve this, it is possible to improve the overall wiring efficiency by eliminating intersections between the individual connection relationships of each functional terminal during the placement and wiring process, and significantly reducing the number of correction steps after the placement and wiring process. This has the excellent effect of allowing LSI development to be carried out in a short period of time.
第1図は本発明の一実施例におけるセル配置処理を示す
工程図、
第2図は一実施例における配線処理を示す工程図、
第3図は一実施例においてユーザが作成する論理図、
第4図は配置・配線処理後における論理図、第5図は本
発明における配置・配線処理を説明するためのフローチ
ャート、
第6図は従来においてユーザが作成した論理図、第7図
は従来方法における配置・配線結果を示す図である。
第2図
一実施例zF3ける配m処理を示す工裡回目において、
COは第1のセルとしての駆動セル、
Cl−CI2は第2のセルとしての従動セル、Nl、N
2はネット、
XI、X2は同一機能端子としての出力端子である。1 is a process diagram showing cell placement processing in one embodiment of the present invention; FIG. 2 is a process diagram showing wiring processing in one embodiment; FIG. 3 is a logic diagram created by the user in one embodiment; Figure 4 is a logic diagram after placement and wiring processing, Figure 5 is a flowchart for explaining the placement and wiring processing in the present invention, Figure 6 is a logic diagram created by a user in the conventional method, and Figure 7 is a logic diagram in the conventional method. FIG. 3 is a diagram showing placement/wiring results. In the first part of FIG. 2 showing the m arrangement process in Example zF3, CO is the driving cell as the first cell, Cl-CI2 is the driven cell as the second cell, Nl, N
2 is a net, and XI and X2 are output terminals with the same function.
Claims (1)
子を複数個有する第1のセルと、このセルの機能端子の
いずれかに接続される複数個の第2のセルとで構成され
る半導体集積回路において、前記第1のセルに接続され
る全第2のセルを第1のセルの機能端子のいずれか1つ
のみに接続されるネットとして前記第1のセル及び各第
2のセルの配置を行なった後、配置された各第2のセル
のうち、使用される各機能端子に近接したもの同士をグ
ループ化し、各機能端子と各グループとを結ぶ配線経路
を決定するようにしたことを特徴とする半導体集積回路
の製造方法。1 Among the many cells formed on the substrate, it is composed of a first cell having a plurality of identical functional terminals and a plurality of second cells connected to any of the functional terminals of this cell. In the semiconductor integrated circuit, all the second cells connected to the first cell are connected to the first cell and each second cell as a net connected to only one of the functional terminals of the first cell. After performing the placement, among the placed second cells, those close to each functional terminal to be used are grouped together, and the wiring route connecting each functional terminal to each group is determined. A method for manufacturing a semiconductor integrated circuit, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27761089A JP2851079B2 (en) | 1989-10-25 | 1989-10-25 | Manufacturing method of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27761089A JP2851079B2 (en) | 1989-10-25 | 1989-10-25 | Manufacturing method of semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH03139865A true JPH03139865A (en) | 1991-06-14 |
JP2851079B2 JP2851079B2 (en) | 1999-01-27 |
Family
ID=17585823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27761089A Expired - Fee Related JP2851079B2 (en) | 1989-10-25 | 1989-10-25 | Manufacturing method of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2851079B2 (en) |
-
1989
- 1989-10-25 JP JP27761089A patent/JP2851079B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2851079B2 (en) | 1999-01-27 |
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