JPH03139865A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the formation of intersections in individual connecting relations of functional terminals in use and to improve total wiring efficiency by arranging first and second cells as nets which are connected to only either one of the functional terminals of the first cell, and forming a group of the cells which are in the close proximity of each functional terminal used among the second cells. CONSTITUTION:A driving cell CO and driven cells C1-C12 are automatically arranged. Of the arranged driven cells C1-C12, the cells which are in close proximity to output terminals X1 and X2 are grouped within the number the cells which can be connected to the terminals X1 and X2. The output terminals X1 and X2 which are close to the groups G1 and G2 are assigned. A net N1 is newly formed of the output terminal X1 and the group G1. A net N2 is formed of the output terminal X2 and the group G2. Automatic wiring is performed in the newly formed nets N1 and N2. Thus, the wiring paths in the nets N1 and N2 are determined.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for manufacturing a semiconductor integrated circuit, more specifically, a method for manufacturing an integrated circuit based on a desired logic, in which a plurality of identical functions provided in a cell with no operational differences are provided. When trying to obtain the desired logic by connecting multiple cells using terminals, it is possible to improve the overall wiring efficiency by eliminating intersections between the individual connection relationships of each functional terminal during placement and wiring processing. , LS with a significant reduction in the number of corrections after placement and wiring processing.
The purpose of the present invention is to provide a method for manufacturing semiconductor integrated circuits that enables I development in a short period of time.
In a semiconductor integrated circuit comprising a cell and a plurality of second cells connected to any of the functional terminals of this cell, all the second cells connected to the first cell are connected to the first cell.
After arranging the first cell and each second cell as a net connected to only one of the functional terminals of the cells, each of the second cells to be used is Components that are close to a functional terminal are grouped together, and a wiring route connecting each functional terminal and each group is determined.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and more particularly to a method of manufacturing an integrated circuit based on desired logic.

In recent years, as LSIs have become more highly integrated, there has been a demand for more logic circuits to be built into a limited area on a substrate.

For this reason, there is a need for an increasing number of users to be able to easily define their own desired logic and to achieve efficient wiring in wiring processing.

[Prior Art] Conventionally, when placing each cell constituting a semiconductor integrated circuit based on logical connection information specified by a user, the placement process of the cells constituting the logic has been faithfully performed based on the logical connection information. I am doing it.

At this time, when connecting multiple cells to cells that have terminals with the same function that have no operational differences, there are constraints caused by the physical conditions (in the case of output terminals, the upper limit of output drive capability). If a plurality of terminals must be used in the same cell, the user must define separate connection relationships (hereinafter referred to as nets) for each of these terminals.

That is, when a plurality of driven cells 01 to CI2 are connected to a driving cell CO having two output terminals XI and X2 that output the same signal as shown in FIG. Due to the constraints imposed by
These output terminals XI.

X2 must be used, and the user has to create separate nets Nl, N2 for these output terminals XI, X2, respectively.
will be defined.

When the drive cell CO and the driven cells C1 to C12 are arranged based on the logical connection information specified by the user, the driven cells 01 to CI2 are arranged in an intersecting positional relationship as shown in FIG. After this placement process, a wiring route is determined in a wiring process.

[Problems to be Solved by the Invention] However, in wiring processing, both nets Nl and N2 are treated as separate logics, and the driven cell Cl- is connected to the output terminal XI.
The wiring route is determined so that the driven cells C7 to C12 are connected to the output terminal X2 such that C6 is connected to the output terminal X2. As a result, as shown in Fig. 7, both nets Nl and N2
In each wiring region LT, the wirings form a wiring pattern that intersects with each other as shown by the broken line frame, and the wiring density due to these wirings increases within the same wiring region LT. The more complicated the crossing state of the wirings of both nets Nl and N2, the more complicated the crossing state of the wirings of both nets N1 and N2. There is a problem in that the degree of wiring congestion at the intersection of N2 increases and the wiring efficiency of the entire circuit decreases.

The present invention was made to solve the above problems, and its purpose is to connect a plurality of cells using a plurality of terminals with the same function provided in the cells and having no operational differences. When trying to obtain the desired logic using a layout/wiring process, the overall wiring efficiency can be improved by eliminating the possibility of crossing over the individual connection relationships of each functional terminal during the placement/wiring process, and greatly reducing the number of corrections required after the placement/wiring process. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit that can reduce the number of LSIs and develop LSIs in a short period of time.

[Means for solving the problem] First, among a large number of cells formed on a substrate, the cell of Kintetsu 2 connected to the first cell is connected to only one of the functional terminals of the first cell. The first cell and each second cell are arranged as a net connected to the first cell and each second cell. Thereafter, among the second cells arranged, those close to each functional terminal to be used are grouped. Then, a wiring route connecting each functional terminal and each group is determined.

[Operation] Since the wiring route is determined after the cell placement process is performed within the group made up of adjacent second cells,
The wiring paths of different groups do not cross each other, and wiring efficiency is improved.

Further, each group composed of adjacent second cells is connected to the functional terminal of the first cell closest to the group, so that unnecessary wiring from the functional terminal can be avoided.

[Example] An embodiment embodying the present invention will be described below.

FIG. 1 is a process diagram showing cell placement processing in one embodiment of the present invention, FIG. 2 is a process diagram showing wiring processing in one embodiment, and FIG. 3 is a logic diagram created by the user in one embodiment. FIG. 4 is a logic diagram after placement and wiring processing, and FIG. 5 is a flowchart for explaining placement and wiring processing in the present invention. Components similar to those in FIGS. 6 and 7 are given the same reference numerals. explain.

This embodiment describes a circuit that is composed of a driving cell CO having two output terminals XI and X2 that outputs the same signal as a first cell, and a plurality of driven cells C1 to CI2 as second cells. do.

Now, before performing the placement and wiring processing, the user has set all the driven cells Cl-C12 to the output terminals XI as shown in FIG.
Suppose we have a logic diagram defined as one net NO connected only to

Based on this logic diagram, the driving cells CO and driven cells Cl-CI2 are automatically placed on the substrate (the path shown in the figure) as shown in FIG. In this placement process, the driven cells C1-C12 are treated as one net NO.
The degree of freedom in arranging each of the driven cells C1 to C12 is increased, resulting in a well-balanced arrangement.

After the placement process, among the placed driven cells C1-CI2, those close to each output terminal XI, X2 are connected to each terminal X.
Group cells within the number of cells that can be connected to I and X2. In this embodiment, the driven cells C1゜C2, C3, CIO, C11
, C12 as group Gl, and driven cells C4, C5, C
6, C7° C8, C9 are group G2. Next, output terminals Xi and N2 close to groups Gl and G2
As shown in FIG. 4, output terminal XI and group G1 constitute a new net N1, and output terminal X2 and group G2 constitute net N2.

Then, by performing automatic wiring processing within each of the newly constructed nets Nl and N2, the wiring routes in each of the nets Nl and N2 are determined as shown in FIG.

In this manner, in this embodiment, after the arrangement processing of each of the driven cells C1 to C12 is performed, each output terminal XI.

Driven cells close to N2 form a group Gl.

G2 was formed, and output terminals XI and X2 close to both groups Gl and G2 were allocated to form nets N1°N2. Since the wiring process is performed within each net Nl, N2, the wiring routes of each net Nl, N2 do not intersect, and wiring efficiency can be improved. As a result, the number of correction steps after placement and wiring processing can be significantly reduced, and LSI development can be carried out in a short period of time.

In addition, in this embodiment, the nearest output terminals Xi and X2 are allocated to the groups Gl and G2, and the net Nl is
, N2, it is possible to avoid unnecessary wiring from the output terminals XI, X2 to the respective groups G1, G2.

[Effects of the Invention] As detailed above, according to the present invention, a desired logic can be realized by connecting a plurality of cells using a plurality of terminals with the same function provided in the cells and having no operational differences. When trying to achieve this, it is possible to improve the overall wiring efficiency by eliminating intersections between the individual connection relationships of each functional terminal during the placement and wiring process, and significantly reducing the number of correction steps after the placement and wiring process. This has the excellent effect of allowing LSI development to be carried out in a short period of time.

[Brief explanation of the drawing]

1 is a process diagram showing cell placement processing in one embodiment of the present invention; FIG. 2 is a process diagram showing wiring processing in one embodiment; FIG. 3 is a logic diagram created by the user in one embodiment; Figure 4 is a logic diagram after placement and wiring processing, Figure 5 is a flowchart for explaining the placement and wiring processing in the present invention, Figure 6 is a logic diagram created by a user in the conventional method, and Figure 7 is a logic diagram in the conventional method. FIG. 3 is a diagram showing placement/wiring results. In the first part of FIG. 2 showing the m arrangement process in Example zF3, CO is the driving cell as the first cell, Cl-CI2 is the driven cell as the second cell, Nl, N
2 is a net, and XI and X2 are output terminals with the same function.

Claims (1)

[Claims] 1 Among the many cells formed on the substrate, it is composed of a first cell having a plurality of identical functional terminals and a plurality of second cells connected to any of the functional terminals of this cell. In the semiconductor integrated circuit, all the second cells connected to the first cell are connected to the first cell and each second cell as a net connected to only one of the functional terminals of the first cell. After performing the placement, among the placed second cells, those close to each functional terminal to be used are grouped together, and the wiring route connecting each functional terminal to each group is determined. A method for manufacturing a semiconductor integrated circuit, characterized by: