JPS62115740A - Integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent confusion on a design by a change into multilayers, and to conduct a hierarchization design using multilayer interconnections easily by each making specific wiring layers correspond to a plurality of design hierarchies in an integrated circuit having multilayer interconnection structure. CONSTITUTION:A large scale integrated circuit has wiring layers consisting of N layers, and the wiring layers are used as a first layer, a second layer ... an N-th layer toward an upper layer from a lower layer. On the other hand, a circuit in a chip is constituted of M-th order hierarchies composed of a chip level LSI circuit, etc. consisting of the interconnections of (1) fixed-shape connections among a small number of elements or in elements, (2) a simple circuit employing said (1) as a unit, (3) a circuit using said (2) as a unit and having a scale larger than 2, ... M a large scale circuit block employing said M-1 as a unit. In such a case, wiring layers for the whole layers or one part of a first layer - an n1-th layer are made to correspond to a first-order hierarchy, wiring layers for the whole layers or one part of an n1'-th layer - an n2-th layer are made to correspond to a second-order hierarchy, and wiring layers for the whole layers or one part of an nm-1'-th layer - an nm-th layer are made similarly to correspond to the connections of a chip level in an M-th order hierarchy, an uppermost layer, and circuits are connected at each hierarchy level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and particularly to an integrated circuit device having a multilayer wiring structure.

[Conventional technology]

In order to achieve large scale and high integration of integrated circuits, it is necessary to miniaturize the patterns of circuits and elements and to construct wiring layers into a multilayer structure. As the scale of integrated circuits increases, it is necessary to impose certain rules on the method of laying each wiring layer.

In other words, in the early days when two-layer wiring was adopted as multilayer wiring, second-layer wiring was used as an auxiliary tool to solve wiring intersections in first-layer wiring, but recently, second-layer wiring The wiring is also used with the same tackiness as the first layer wiring, which also produces the effect of reducing the wiring area. For this reason, in the second layer wiring, similar to the first layer wiring, predetermined rules are followed, for example, the first layer wiring is extended in the X direction and the second layer wiring is extended in the Y direction.
It becomes necessary to provide rules such as extending the wires in the directions to facilitate the design of each wire.

However, in recent years, integrated circuits have become larger in scale that cannot be followed by a two-layer wiring structure, and therefore a multilayer wiring structure of three or four layers or more is required.

[Problem that the invention seeks to solve]

In the conventional integrated circuit device described above, when configuring a multilayer wiring structure with three or four layers or more, the wiring rules given to each wiring layer are applied as they are in the past. In this case, wiring in different layers extends in the same direction and overlaps in the plane position, which tends to cause mutual interference between multiple wiring layers, such as interference at the connection points between multilayer wiring. . For this reason, especially in a multilayer wiring structure having four or more layers, it becomes extremely difficult to design each wiring layer, resulting in a problem that design efficiency is significantly reduced.

Means for Solving Problem C] The integrated circuit device of the present invention aims to facilitate the design of each wiring layer in a multilayer wiring structure and to improve the design efficiency of the entire multilayer wiring structure.

The integrated circuit device of the present invention is an integrated circuit in which a plurality of design layers are stacked to form a multilayer wiring structure, and the circuit design of each layer is configured by associating one or more specific wiring layers with each layer. ing.

In this case, the specific wiring layer is a wiring layer including one wiring layer and lower wiring layers.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a diagram explaining the basic concept of the present invention.

Nowadays, large-scale integrated circuits have N wiring layers, which are divided into the first layer and the second layer from the bottom layer to the top layer.

. . . is the Nth layer. On the other hand, the circuit configuration in a chip is, for example, (1): fixed connection between a small number of elements or within an element, (2): an hour wheel-like circuit using (1) as a unit, (3)
= A circuit larger in scale than (2) using (2) as a unit,
. . . M: It is assumed that the circuit is constituted by an M-th hierarchy composed of chimp level L31 circuits consisting of interconnected large-scale circuit blocks in units of (M-1).

In such a case, the first layer corresponds to all or part of the wiring layers from the 1st layer to the n1th layer, and the second layer corresponds to all the wiring layers from the 1st layer to the n2th layer. The wiring layers of the layer or a part thereof are made to correspond to each other, and the third layer is made to correspond to all or a part of the wiring layers from the n2'th layer to the n1th layer, and in this way, the wiring layer of the Mth layer is In other words, the circuit connection at each layer level is performed by making all or a part of the layers from the nff1-l''th layer to the n0th layer correspond to the chip level connection at the top layer.However, as mentioned above, n,, n2.-+ , n,, nl'+
nZZ −', n, and 11-1' do not necessarily define a mutual magnitude relationship.

Also, each of these numbers is equal to or greater than 1, or equal to or less than N. In particular, there may be one or more equal to N, or conversely there may be none. Wiring layers that do not correspond to any level in the design hierarchy, for example wiring layers such as capacitors and inductors formed using power supply wiring main lines and wiring, do not necessarily need to be made to correspond to circuit hierarchies. Of course, such a wiring layer that does not correspond to any hierarchy is not necessary for any integrated circuit.

FIG. 2 shows an embodiment in which the present invention is actually applied to a semiconductor integrated circuit device. In the figures, (A) and (B).

(C) shows the design hierarchy, (A) shows the connection hierarchy at the element level, and (B) shows the connection structure at the element level composed of (A>) as one unit, and consists of various aggregates of these. Circuit Bronf-level connection hierarchy (C) shows a chip-level connection hierarchy consisting of various aggregates of circuit blocks constructed by (B). In this example, the number of hierarchies M is three.

Here, in FIG. 2A, ▪ indicates the first layer wiring, 5 indicates a bipolar transistor, and b, e, and c indicate the base, emitter, and collector of the bipolar transistor, respectively. Further, 6 indicates the position of the connection terminal used in the layer CB) in the same figure. In addition, in this embodiment, the first layer wiring l is a wiring mainly made of tungsten in order to prevent alloy spikes (reaction between the wiring metal and silicon at the semiconductor substrate contact portion) that are likely to occur in shallow bonds formed on the semiconductor substrate. Because of the material used, the wiring resistance is an order of magnitude higher than that of aluminum.

For this reason, the potential shift is large in DC terms due to circuit operation.
With alternating current, the time constant is large, so it is not possible to extend the wiring for a long time. However, as shown in the same figure (A), the double base is made into one terminal by the first layer wiring 1, and it also contributes to making the collector C and emitter e of the two transistors common. A total of eight transistor electrodes, including the emitter and collector, are reduced to four at the connection point to the second layer wiring, as shown by reference numeral 6, producing the effect of one wiring layer.

Further, although not shown, it is also possible to reduce the load capacitance by providing a "tunnel wiring" made of a diffusion layer in the first layer wiring, which is used to avoid wiring intersections. In this way, it can be seen that in this embodiment, the correspondence between the first layer and the first layer wiring is based on consideration of manufacturing stability and circuit operation stability. That is, in this example, one of the wiring layers corresponding to the first layer always includes the first layer wiring, and therefore it is possible to hierarchize without going against the characteristics specific to the 1M wiring.

On the other hand, in the same figure (B), 2 is the second layer wiring, and 3 is the third N layer wiring.
Each wiring is shown. Further, 6 indicates the terminal point position of the first layer as described above, 7 indicates the terminal point position of the second 111 layer used at the third layer level, and 8 indicates the terminal point position of the second layer 111 used at the third layer level.
The position of the opening for connection between the layer wiring 2 and the third layer wiring 3 is shown. The wiring layers used in this second layer are the second layer wiring 2 and the third layer wiring 3. In particular, the third layer wiring 3 is designed to reduce the number of layers used in consideration of the usage in the upper layer. (Three in this example), and furthermore, they are laid only in the vertical direction in the figure.

In addition, in the same figure (C), 9 indicates the position of the opening for connection between the third layer wiring 3 and the fourth layer wiring 4, and 10 to 1
Reference numeral 2 indicates various circuit blocks having the same structure as that shown in FIG. 3(B), and in particular, 10 is the same block as shown in FIG. 3(B). 13 indicates a chip.

Note that most of the circuit blocks, chip pads, etc. are not shown in this figure.

In this third layer, the wiring directions are distinguished so that the main wiring directions are perpendicular to each other, such that the third layer wiring 3 is in the vertical axis direction in the figure, and the fourth layer wiring 4 is in the horizontal axis direction. There is. The third N wiring 3, which includes the circuit blocks 10 to 12 and other circuit blocks not shown, is all laid in accordance with this rule.

Therefore, in this embodiment configured in this way, the first layer wiring 1 is placed in the first layer, the second layer wiring 2 and third layer wiring 3 are placed in the second layer, and the third layer wiring is placed in the third layer. Layer wiring 3 and 4
Since N wirings 4 are used and each layer has only two layers of wiring, even though a multilayer structure is designed, the design is almost the same as a conventional two-layer wiring structure. In particular, the third layer wiring is used for two layers, the second and third layers, and in this case, the wiring installation direction is defined to prevent confusion between the layers.

Therefore, the design efficiency of each block is maintained at the same level as that of the conventional two-layer structure, and in particular, the design efficiency per the same scale at the chip level is 2.
This can be improved over chips with a layered structure.

Here, the present invention is not limited to the embodiments described above, and various modifications can be made. For example, when the layer resistance of the first layer wiring is low, the first layer corresponds to the first and second layer wiring to form a small circuit block, and the second layer corresponds to the second and third layer wiring. It is also possible to construct a chip-level LSI logic by associating the wiring to form a macro circuit block consisting of a collection of small blocks, and by associating the third and fourth layer wiring to the third layer. In addition, if the current flowing through the main line of the power supply wiring is very large, such as in a large-scale bipolar circuit, the top layer wiring, where it is easy to thicken the wiring metal, should be placed in a layer corresponding to the circuit configuration described above. It is also possible to separate it from the main power supply line and make it a layer dedicated to the power supply main line.

〔Effect of the invention〕

As explained above, in an integrated circuit having a multilayer wiring structure, the present invention associates a specific wiring layer with each of a plurality of design hierarchies, thereby preventing design confusion caused by multilayering and eliminating the need for conventional two-layer wiring. It is possible to maintain almost the same design efficiency at the block design level as that of an integrated circuit having several wiring layers, and it becomes possible to smoothly perform hierarchical design using multilayer wiring. As a result, the design efficiency of integrated circuits can be improved as the degree of integration increases.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of the present invention, showing the relationship between the design hierarchy and the wiring layer, and Fig. 2 shows an example of application of the present invention.
(B) and (C) are plan views of wiring layers corresponding to the first to third hierarchies. l...First layer wiring, 2...Second layer wiring, 3...Third layer wiring, 4...Fourth layer wiring, 5...Transistor, 6...First place and 2nd connection point, 7... 2nd and 3rd connection point, 8... Connection point between 2nd layer and 3rd layer wiring, 9... 3rd layer and 4th layer wiring connection point, 10-12・
...Various circuit blocks, 13...chips.

Claims (1)

[Claims] 1. In an integrated circuit in which a plurality of design layers are stacked to form a multilayer wiring structure, each layer is associated with one or more specific wiring layers to form a circuit design for each layer. An integrated circuit device characterized by: 2. The integrated circuit device according to claim 1, wherein the specific wiring layer includes one wiring layer and lower wiring layers. 3. The integrated circuit device according to claim 2, wherein the wiring layers used over a plurality of levels have a main wiring laying direction defined in one direction. 4. The integrated circuit device according to claim 3, wherein the main wiring directions between the wirings in adjacent wiring layers are orthogonal to each other.