JPH03136117A - Microcomputer - Google Patents

Abstract

PURPOSE:To constitute the microcomputer so that its internal circuit can be started stably and in a short time by providing a timing signal generating part, and a reset signal control part for outputting an internal reset signal. CONSTITUTION:A timing signal generating part 2 inputs an internal clock pulse ICK, and outputs a timing signal TM for controlling an operation timing of an internal circuit and a reset release signal RSU. When an inputted reset signal RS is in an active level and when the reset release signal RSU is in an inactive level, a reset signal control part 3 sets an internal reset signal IRS to an active level and holds the internal circuit in a reset state. Subsequently, when the reset signal RS becomes an inactive level, and also, the reset release signal RSU becomes an active level, the internal reset signal IRS is set to an inactive level, and the reset state of the internal circuit is released. In such a way, the internal circuit is started stably and in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer, and more particularly to a microcomputer that has a reset function and operates using clock pulses.

[Conventional technology]

Conventionally, when releasing a reset state, this type of microcomputer is not limited by the pulse width of the clock pulse. When the input reset signal is set to an inactive level, the internal circuit is released from the reset state by this reset signal.

[Problem to be solved by the invention]

The conventional microcomputer described above is configured to release the reset state of the internal circuit when the input reset signal reaches an inactive level, so the reset signal reaches an inactive level before the clock pulse oscillation stabilizes. In this case, the internal circuit cannot necessarily operate normally due to the instability or lock pulse at that time, which causes the problem of program runaway.

This is because the oscillation amplitude is small and susceptible to noise until the clock pulse oscillation using mechanical vibration of a crystal oscillator or ceramic oscillator becomes stable, and the pulse width of the clock pulse captured inside the microcomputer is This is because the pulse width is not constant at all and includes many pulses with narrow pulse widths.

In order to solve this problem, it was necessary to maintain the reset signal at an active level until the oscillation stabilized, which required an external reset input circuit and a modification to the reset input circuit.

Alternatively, in order to maintain the reset state until the oscillation stabilizes, some microcomputers have a timer installed inside the microcomputer and use this timer to maintain the reset state for a predetermined period of time.
When the amplitude of the output is small immediately after the start of oscillation, the timer itself may malfunction, and the reset state may be released before the oscillation stabilizes.

Therefore, with these methods, it is necessary to estimate the oscillation stabilization time sufficiently long and maintain the reset state for a long time.
Another drawback is that it takes a long time after the power is turned on until the reset state is released and the program starts operating.

An object of the present invention is to provide a microcomputer that can stably and quickly start its internal circuits without providing an external reset input circuit or an internal timer.

[Means to solve the problem]

The microcomputer of the present invention includes a clock pulse input section that validates the clock pulse and outputs it as an internal clock pulse when the pulse width of the input clock pulse is wider than a preset pulse width; a timing signal generating section that generates a reset release signal using an internal clock pulse and also generates a timing signal that controls the operation timing of the internal circuit; and a reset signal control section that outputs an internal reset signal that becomes an active level when the input reset signal is an inactive level and when the reset release signal is an active level, the internal reset signal becomes an inactive level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The clock pulse input section 1 inputs a clock pulse CK, and outputs this clock pulse CK as an internal clock pulse ICK only when the pulse width of this clock pulse CK is wider than a preset pulse width. This preset pulse width is a pulse width that allows all internal circuits of the microcomputer to which the internal clock pulse ICK is input to operate normally.

The timing signal generator 2 generates an internal clock pulse ICK.
is input, and this internal clock pulse ICK is used to generate a timing signal TM that controls the operation timing of the internal circuit.
and outputs a reset release signal R3U.

The reset signal control unit 3 receives the input reset signal R8.
is at active level, and reset release signal R8
When U is inactive level, internal reset signal IR
8 is set as the active level to hold the internal circuit in a reset state. Then, when the reset signal R8 becomes inactive level and the reset release signal R8U becomes active level, the internal reset signal IR8 becomes inactive level, and the reset state of the internal circuit is released.

In this way, even if the reset signal R8 is set to an inactive level, the internal clock ICK is not generated, that is, until a clock pulse with a pulse width that allows all internal circuits of the microcomputer to operate normally is input. , the reset state will not be released.

Further, since the internal reset signal IR8 becomes inactive level by the reset release signal R8U, there is no need to provide a sufficiently long waiting time for oscillation stabilization, and the time until the internal circuit starts operating can be shortened.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which only the clock pulse with a pulse width that allows all the internal circuits of the microcomputer to operate normally is enabled, and the reset state can be released by the valid or lock pulse. Since there is no need to provide a sufficiently long wait time for the clock pulse oscillation to stabilize, the internal circuit can be started stably and quickly without providing an external reset input circuit or an internal timer. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1... Clock pulse input section, 2... Timing signal generation section, 3... Reset signal control section.

Claims (1)

[Claims] A clock pulse input section that validates the clock pulse and outputs it as an internal clock pulse when the pulse width of the input clock pulse is wider than a preset pulse width, and a reset release signal generated by the internal clock pulse from this clock pulse input section. and a timing signal generating section that generates a timing signal that controls the operation timing of the internal circuit; a reset signal control section that outputs an internal reset signal that becomes inactive level when the reset signal that is input is at inactive level and the reset release signal is at active level.