JP2007279933A - Clock signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal generation circuit which does not unnecessarily delay the supply of clock signals in simplified circuit configuration. <P>SOLUTION: When the oscillating operation of an oscillator 5 is started, pulse signals OC whose pulse is narrow immediately after the operation is started and gets close to a prescribed width as being stabilized are outputted. The pulse signals OC are delayed for prescribed time in a delay element 6 and supplied to FFs 7 and 8 as delayed pulse signals DL. In the FF 7, since the pulse signals OC are held at the rise of the delayed pulse signals DL, signals S7 become "L" while the width of the pulse signals OC is shorter than the prescribed time and become "H" when the pulse width exceeds the prescribed time. In the meantime, in the FF 8, since the pulse signals OC are held at the timing of the fall of the delayed pulse signals DL and outputted from an inverted output terminal /Q, signals S8 become "H" at all times. Thus, the clock signals CK of a prescribed pulse width are outputted from an AND gate 9. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a clock signal generation circuit.

  In an integrated circuit that supplies a clock signal using an internal oscillation circuit such as a crystal oscillator, a CR oscillator, or a ring oscillator, it takes some time for the clock signal to stabilize after oscillation starts. Until the clock signal is stabilized, the integrated circuit may operate in an unstable manner. Therefore, it is necessary to stop supplying the clock for a time sufficiently longer than the time during which the clock signal is stabilized. In particular, in an integrated circuit having a function of stopping a clock signal in a standby state, supply of an unstable clock signal at the start of operation of the oscillation circuit is controlled when shifting from the standby state to a normal operation.

FIG. 2 is a configuration diagram of a conventional clock signal generation circuit.
This clock signal generation circuit counts an oscillator (OSC) 11 whose oscillation operation is controlled by an enable signal EN, an oscillation signal OC output from the oscillator 11, and the count value is a predetermined value cn1, cn2, cn3. ..., the counter (CNT) 12 that outputs signals CN1, CN2, CN3, ... when these are exceeded, and these signals CN1, CN2, CN3, ... are selected according to the selection signal set in the register (REG) 13 And an AND gate 15 that gates the oscillation signal OC output from the oscillator 11 with the signal CN output from the selector 14 and outputs it as a clock signal CLK.

JP 2000-172737 A

  Patent Document 1 discloses a circuit that cascades two flip-flops (hereinafter referred to as “FF”) having a clock terminal and a signal input terminal, and detects a change in an asynchronous input signal to form a one-shot pulse. And a clock prohibition circuit comprising a transmission gate that controls the supply to the first stage FF using the one-shot pulse as a prohibition signal, thereby enabling unstable output of the FF in a synchronization circuit including a plurality of FFs. It is said that asynchronous signals can be synchronized in a short time while avoiding the state.

  However, since the clock signal generation circuit sets the stable period of the clock signal based on the count value of the counter, the clock signal is not supplied until the specified count value is reached even if the clock signal is stable. I was n’t. Therefore, not only the supply of the clock signal is delayed more than necessary, but also a relatively large circuit such as a counter for counting the clock signal is required.

  An object of the present invention is to provide a clock signal generation circuit that has a simplified circuit configuration and does not unnecessarily delay the supply of a clock signal.

  The clock signal generation circuit of the present invention starts output of an enable signal by a start signal, and when power down is designated, a control unit that stops output of the enable signal, and when the enable signal is given An oscillation unit that performs an oscillation operation and outputs a pulse signal, a delay unit that delays and outputs the pulse signal by a preset delay time, and compares the pulse signal with an output signal of the delay unit A first detection unit that outputs a first permission signal when a high-level time of the signal is longer than the delay time; and a low-level time of the pulse signal by comparing the pulse signal with the output signal of the delay unit A second detection unit that outputs a second permission signal when is longer than the delay time, and an output signal of the delay unit when the first and second permission signals are output. It is characterized by comprising an output section for outputting a clock signal.

  In the present invention, the delay unit that outputs the pulse signal output from the oscillation unit by delaying by a preset delay time, and the pulse signal is compared with the output signal of the delay unit. The first and second detection units that output the first and second permission signals, respectively, and the output signal of the delay unit when the first and second permission signals are output when the time is long. An output unit for outputting as a clock signal is provided. Thus, there is an effect that a clock signal can be output with a simplified circuit configuration without unnecessarily delaying supply.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

FIG. 1 is a block diagram of a clock signal generation circuit showing an embodiment of the present invention.
This clock signal generation circuit has a 2-input AND gate 1 to which a reset signal / RS and an interrupt signal / IN are applied. The reset signal / RS is given from the reset circuit at the time of the initial reset, and is manually given by an operator or the like at an arbitrary timing. By giving the level “L”, the state of each part in the integrated circuit is initialized. It is a signal for returning. In the normal operation state, the reset signal / RS is at level “H”. On the other hand, the interrupt signal / IN is a signal for starting this clock signal generation circuit from an external device or circuit, and is set to “L” to display an interrupt. In a normal operation state, the interrupt signal / IN is “H”. The signal S1 output from the AND gate 1 is supplied to the set terminal S of FF2.

  The FF 2 holds the signal applied to the input terminal D at the rising timing of the clock signal CK applied to the clock terminal C, outputs it to the inverted output terminal / Q, and applies the “L” signal to the set terminal S. When it is set, it is forcibly set to output "L" from the inverted output terminal / Q. An input terminal D of FF2 is supplied with a power-down signal / PD that becomes “L” in order to stop the operation of the oscillation circuit during standby. In the normal operation mode, the power down signal / PD is “H”.

  The signal S2 output from the inverting output terminal / Q of FF2 is applied to one input side of the 2-input AND gate 3, and the reset signal / RS is applied to the other input side of the AND gate 3. Yes. The signal S3 output from the AND gate 3 is supplied to the set terminal S of the FF4 similar to the FF2.

  The input terminal D of the FF 4 is connected to “L”, and the clock signal CK is supplied to the clock terminal CK. An enable signal EN is output from the output terminal Q of the FF 4 and is provided as a control signal for the oscillator 5 and FFs 7 and 8 described later.

  The oscillator 5 is composed of, for example, a crystal oscillator, a CR oscillator, or a ring oscillator, and performs an oscillation operation when the enable signal EN is “H”, and stops the oscillation operation when the enable signal EN is “L”. The pulse signal OC output from the oscillator 5 is supplied to the delay element 6 and the input terminals D of the FFs 7 and 8. The delay element 6 includes a plurality of cascaded gates, integration circuits, and the like, and delays the input pulse signal OC by a preset delay time and outputs it as a delay pulse signal DL. The delayed pulse signal DL is connected to the clock terminal C of the FFs 7 and 8 and the first input side of the 3-input AND 9.

  The FF 7 holds the pulse signal OC given to the input terminal D at the rising timing of the delayed pulse signal DL given to the clock terminal C, and outputs it from the output terminal Q as the signal S 7, and “L” to the reset terminal R. When the enable signal EN is given, the stored content is forcibly reset.

  The FF 8 holds the pulse signal OC applied to the input terminal D at the falling timing of the delayed pulse signal DL applied to the clock terminal C, and outputs the inverted signal as the signal S8 from the inverted output terminal / Q. At the same time, when the “L” enable signal EN is given to the reset terminal R, the stored contents are forcibly reset.

  The signals S7 and S8 respectively output from these FFs 7 and 8 are given to the second and third input sides of the AND gate 9, and the clock signal CK is outputted from the output side of the AND gate 9. ing.

  FIG. 3 is a truth table showing the relationship between the reset signal / RS, the interrupt signal / IN and the power down signal / PD, which are the input signals of FIG. 1, and the enable signal EN. FIG. FIG. 2 is a signal waveform diagram showing the oscillation operation of FIG. 1 when given. Hereinafter, the operation of FIG. 1 will be described with reference to FIGS. 3 and 4.

First, the operation of the control unit that controls the start and stop of the oscillator 5 will be described with reference to FIG.
As shown in FIG. 3, when the reset signal / RS becomes “L” at the time of startup, the signal S3 output from the AND gate 3 becomes “L” regardless of the interrupt signal / IN and the power down signal / PD. , FF4 is reset, and the enable signal EN becomes “H”. When the external interrupt signal / IN becomes “L” in the standby state, the signal S1 of the AND gate 1 becomes “L”, the FF2 is set and the signal S2 becomes “L”, and the AND gate 3 The signal S3 becomes “L”. As a result, the enable signal EN becomes “H”. Therefore, when a start signal such as a reset signal / RS or an interrupt signal / IN is given, the enable signal EN is output and the oscillation operation of the oscillator 5 is started. The reset signal / RS and the interrupt signal / IN then become “H” and shift to the normal operation state.

  In the normal operation state, the reset signal / RS, the interrupt signal / IN, and the power down signal / PD are all “H”. As a result, the signal S1 becomes “H”, the FF2 is released from the set state, the power-down signal / PD of the input terminal D is held at the timing of the clock signal CK, and is output from the inverted output terminal / Q. Therefore, the signal S2 becomes “L”. For this reason, the signal S3 output from the AND gate 3 is held in the “L” state, the set state of the FF 4 is continued, and the enable signal EN is held in “H”.

  At the time of transition to the power down state, the power down signal / PD is set to “L”. As a result, the signal S2 of the FF2 becomes “H” at the rising timing of the clock signal CK. Accordingly, the signal S3 of the AND gate 3 becomes “H”, and the set state of the FF4 is released. Then, the signal “L” of the input terminal D of the FF 4 is held at the rising timing of the next clock signal CK, and the enable signal EN becomes “L”. Thereby, the oscillation operation of the oscillator 5 is stopped.

  Next, the operation from the start of the oscillator 5 to the output of the clock signal CK will be described with reference to FIG.

  When the enable signal EN is “L”, the oscillation operation of the oscillator 5 is stopped, but the output signal OC of the oscillator 5 at this time is fixed to “L” or “H” depending on the circuit configuration. . 4A and 4B show cases where the output signal OC when the oscillator 5 is stopped is “L” and “H”, respectively. Since both operations are the same, here, description will be given based on FIG.

  When the enable signal EN changes to “H”, the oscillation operation of the oscillator 5 is started, and the FFs 7 and 8 are released from the reset state and can perform normal operation. In the oscillator 5, the output of the pulse signal OC is started. At this time, the pulse width at which the pulse signal OC becomes “H” is narrow immediately after the operation is started, and is widened to have a predetermined pulse width as the operation is stabilized. The pulse signal OC is given to the delay element 6 and delayed by a preset delay time, and is given to the clock terminals C of the FFs 7 and 8 as the delayed pulse signal DL.

  In the FF7, the pulse signal OC is held at the rising timing of the delay pulse signal DL, and is output as the signal S7 from the output terminal Q. While the pulse width of the pulse signal OC is shorter than the delay time of the delay element 6, This signal S7 is "L". Then, when the pulse width of the pulse signal OC exceeds the delay time of the delay element 6, the signal S7 becomes "H". That is, it is determined by the FF7 whether or not the “H” time of the pulse signal OC is longer than the delay time, and when it is long, the “S” signal S7 is output.

  On the other hand, in the FF8, the pulse signal OC is held at the falling timing of the delayed pulse signal DL, inverted, and output from the inverted output terminal / Q as the signal S8. Therefore, the signal S8 has a pulse width of the pulse signal OC. Regardless of whether it is always “H”. That is, it is determined by the FF8 whether or not the “L” time of the pulse signal OC is longer than the delay time, and when it is long, the “S” signal S8 is output.

  The signals S7 and S8 and the delayed pulse signal DL are ANDed by the AND gate 9 and output as the clock signal CK. As a result, the output of the delayed pulse signal DL having a narrow pulse width immediately after the start of the operation is stopped, and the clock signal CK having a pulse width equal to or larger than the pulse width corresponding to the predetermined delay time is output.

  As described above, the clock signal generation circuit of this embodiment delays the pulse signal OC output from the oscillator 5 by delaying the pulse signal OC by delaying the pulse signal OC by a predetermined time and the pulse signal OC. FFs 7 and 8 held at the timing of the pulse signal DL, and an AND gate 9 that outputs the logical product of the output signals S7 and S8 of these FFs 7 and 8 and the delayed pulse signal DL as a clock signal CK. This eliminates the output of an abnormal clock signal CK having a narrow pulse width immediately after the start of operation with a simple circuit configuration, and unnecessarily delays the supply of the clock signal when the pulse width reaches a predetermined value. There is an advantage that the clock signal CK can be output immediately without any problem.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) The input signal and circuit for controlling the output of the enable signal EN are not limited to those illustrated.
(B) Instead of the delay element 6, a delay circuit capable of switching the delay time may be provided. Thereby, it is possible to correspond to various oscillation frequencies.

It is a block diagram of a clock signal generation circuit showing an embodiment of the present invention. It is a block diagram of the conventional clock signal generation circuit. 2 is a truth table showing a relationship between an input signal and an enable signal in FIG. 1. FIG. 2 is a signal waveform diagram illustrating the oscillation operation of FIG. 1.

Explanation of symbols

1,3,9 AND gate 2,4,7,8 FF
5 Oscillator 6 Delay element

Claims (1)

A control unit that starts output of the enable signal by a start signal and stops output of the enable signal when power down is designated;
An oscillating unit that oscillates and outputs a pulse signal when the enable signal is given;
A delay unit that delays and outputs the pulse signal by a preset delay time;
A first detection unit that compares the pulse signal with an output signal of the delay unit and outputs a first permission signal when a high level time of the pulse signal is longer than the delay time;
A second detection unit that compares the pulse signal with the output signal of the delay unit and outputs a second permission signal when the low level time of the pulse signal is longer than the delay time;
An output unit that outputs the output signal of the delay unit as a clock signal when the first and second permission signals are output;
A clock signal generation circuit comprising:

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