TWI420484B - Thereof frequency divider and method and gate driver of the same - Google Patents

Description

Frequency divider circuit, method and application thereof

The present invention relates to a frequency divider circuit (Frequency Divider) device, and more particularly to a frequency divider circuit for a gate driver of a liquid crystal display (LCD).

In the current era of rapid technological development, liquid crystal display (LCD) related industries are booming. In general, the Gate Driver of the LCD is provided with a Shift Register, and the Shift Register responds to the scanning of the clock signal to generate a sequentially enabled gate signal. In the existing gate driver technology, a technique for reducing the circuit area of the shift register by frequency division of the scan clock signal has existed.

However, in many cases, the shift register will not operate properly because the scan clock signal is de-clocked. For example, please refer to FIG. 1 , which illustrates a related signal timing diagram of a conventional shift register. The shift register is used, for example, to generate a gate signal in response to the Rising Edge EDG_ri of the scan clock signal CLK when the start signal IPEN is at a high level. However, since the phase may change after the signal is removed, the rising edge of the pulse signal CLKD during the frequency sweep scanning triggers the time when the start signal IPEN is at the low level. As such, the shift register will not be able to generate a gate signal. In this way, how to ensure that the shift register can respond to the normal operation of the scan clock signal after the frequency division operation is the direction that the industry is constantly striving for. one.

The invention relates to a frequency divider circuit (Frequency Divider) and a gate driver (Gate Driver) applied thereto. The frequency divider circuit can control the frequency-divided scan signal to trigger a specific driving edge during a specific period of time ( Driving Edge). Thus, compared to the conventional gate driver, the frequency divider circuit and the gate driver of the embodiment have the advantage that the scanning pulse signal after the frequency division can trigger a specific driving edge in a certain period.

According to the present invention, a gate driver is provided for generating a plurality of gate signals through a plurality of channels in response to an original clock signal and an input trigger signal. The gate driver includes a frequency divider circuit and a shift register circuit (Shift Register). The frequency divider circuit includes a reset unit and a frequency dividing unit. The reset unit is enabled in response to the enablement level of the system reset signal to set the internal reset signal to the enable level in response to the input trigger signal transition being the enabled first driving edge (Driving Edge). The frequency-dividing unit is enabled in response to the enable level of the internal reset signal to sample the feedback signal in response to the original clock signal transition being the enabled second drive edge to determine the frequency-divided clock signal . The shift register circuit is configured to generate some gate signals in response to the frequency-divided clock signal and the input trigger signal.

According to the invention, a frequency divider circuit is provided for generating a frequency-divided clock signal based on an original clock signal. The frequency divider circuit includes a reset unit and a frequency dividing unit. The reset unit is enabled in response to the enablement level of the system reset signal to set the internal reset signal to the enable level in response to the input trigger signal transition being the enabled first driving edge (Driving Edge). Frequency division unit In response to the enablement level of the internal reset signal, the enable signal is sampled in response to the original clock signal transition being the enabled second drive edge to determine the frequency division clock signal.

According to the present invention, a signal control method is provided for generating a frequency division clock signal. The signal control method includes the following steps: first, sampling the reference voltage in response to the input trigger signal transition to the first driving edge to enable the internal reset signal to be an enable level; and then performing the frequency division clock signal Inverting operation to provide a feedback signal; then, in response to the internal reset signal enabling level deactivating circuit, the frequency divider circuit is responsive to the original clock signal to be enabled as the second driving edge pair The feedback signal is sampled to determine the frequency division clock signal.

In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:

The frequency divider circuit (Frequency Divider) of this embodiment is used to control the frequency division scanning pulse signal to trigger a specific driving edge (Driving Edge) in a specific period.

Please refer to FIG. 2, which is a block diagram of a gate driver in accordance with an embodiment of the present invention. The gate driver 100 includes a frequency divider circuit 10, a shift register 20, an arithmetic circuit 25, an output enable control circuit 30, a level shifter 40, and an output buffer. Output Buffer 50. The shift register 20, the output enable control circuit 30, the level shifter 40, and the output buffer 50 form n channels to correspondingly generate n scan signals G(1)-G(n). n Is a natural number greater than 1. For example, n is an even number.

Further, the shift register circuit 20 is configured to generate the control signals M(1), M(2), ..., M(n/2) in response to the input trigger signal DIO and the time pulse signal CPV2. The operation circuit 25 is configured to generate the shift signals Sh(1)-Sh(n) according to the control signals M(1)-M(n/2) and the pulse signal CPV2. For example, the arithmetic circuit 25 is, for example, according to the equation: Sh(2n-1)=M(n). CPV2

Sh(2n)=M(n). CPV2_Bar generates the shift signals Sh(1)-Sh(n) according to the clock signal CPV2 and the control signals M(1)-M(n/2). The clock signal CPV2_Bar is an inverted signal of the clock signal CPV2.

The output enable control circuit 30 is configured to receive the all-conductance communication number XON and the output enable signal OE to determine the output mode of the gate driver 100 to generate and provide the shift signal E(1)-E(n) according to the corresponding output mode. To the level shifter 40. The bit shift register 40 performs level control on the shift signals E(1)-E(n) and outputs them correspondingly. The output buffer 50 uses the level-adjusted shift signals L(1)-L(n) as the gate signals G(1)-G(n), respectively.

The frequency divider circuit 10 is configured to generate the clock signal CPV2 according to the clock signal CPV1, and provide the clock signal CPV2 to the shift register 20 to control the generation of the shift signals Sh(1)-Sh(n). The clock signal CPV2 is one of the clock signals CPV1. For example, the clock signal CPV2 is, for example, a divide-by-two signal of the clock signal CPV1 (that is, the frequency of the clock signal CPV2 is one-half of the frequency of the clock signal CPV1).

Further, please refer to Figures 3 and 4, and Figure 3 shows FIG. 4 is a detailed block diagram of the frequency divider circuit 10 in FIG. 2, and FIG. 4 is a timing diagram of the related signals of the frequency divider circuit 10 of FIG. The frequency divider circuit 10 includes a reset unit 12 and a frequency dividing unit 14. In Figure 3, the enable levels of all signals are, for example, equal to the high level of the signal.

For example, the reset unit 12 includes a D-type flip-flop DF1, and the D-type flip-flop DF1 is used to respond to the enable level of the system reset signal Srstc at the time point TP1 (ie, a high signal) Level) is enabled.

The reset unit 12 is further configured to set the internal reset signal Srstf to an enable level in response to the input trigger signal DIO transition state being enabled to enable the driving edge (Driving Edge). The driving edge of the input trigger signal DIO is the rising edge (Rising Edge). In other words, the reset unit 12 is configured to respond to the rising edge of the input trigger signal DIO to the input terminal D at the time point TP2. The received signal VDD is sampled to determine the internal reset signal Srstf. The signal VDD has, for example, a high level. Thus, after time point TP2, reset unit 12 sets internal reset signal Srstf to a high potential.

For example, the frequency dividing unit 14 includes a D-type flip-flop DF2 and an inverter 14b. The inverter 14b is configured to receive the clock signal CPV2 generated by the D-type flip-flop DF2 and perform an inversion operation to generate the feedback signal Sfbk. The starting level of the clock signal CPV2 is equal to the low level, and the starting level of the feedback signal Sfbk is equal to the high level.

The D-type flip-flop DF2 is responsive to the high signal level of the internal reset signal Srstf. In other words, the frequency dividing unit 14 is enabled from the time point TP2. The D-type flip-flop DF2 is used to respond to the time pulse when it is enabled. The CPV1 transition state is the driving edge of the enabler to sample the feedback signal Sfbk to determine the clock signal CPV2.

The driving edge of the clock signal CPV1 is, for example, a rising edge. In other words, the D-type flip-flop DF2 samples the feedback signal Sfbk (equal to the high level) at the time point TP3 to generate a high-level clock. Signal CPV2. At time TP4, the D-type flip-flop DF2 samples the feedback signal Sfbk (equal to the low level) in response to the rising edge of the next clock signal CPV1, and has generated the low-level clock signal CPV2. By repeating the above steps, a clock signal CPV2 having a frequency substantially equal to one-half of the frequency of the clock signal CPV1 can be generated.

The frequency divider circuit 10 of the present embodiment further includes, for example, a logic operation circuit for generating a system reset signal Srstc according to the control signal and the power supply start reset signal Srstp of the gate driver 100. For example, please refer to FIG. 5, which is a block diagram of the logic operation circuit in the frequency divider circuit 10 of FIG. The logic operation circuit 16 includes an AND gate 16a, a delay circuit 16b, and an inverter 16c. The inverter 16c is configured to receive the gate signal G(n) and provide an inverted signal Sinv of the shift signal Sh(n).

The delay circuit 16b is configured to delay the inverted signal Sinv by a delay time DT and output it as an inverted signal Sinv' to the AND gate 16a. The gate 16a is configured to generate a system reset signal Srstc in response to the inverted signal Sinv and the power start reset signal Srstp operation. The relationship between the power start reset signal Srstp, the system reset signal Srstc, and the delay time DT is as shown in FIG.

In this embodiment, only the logic operation circuit 16 generates a system reset signal according to the shift signal Sh(n) and the power start reset signal Srstp. The case of Srstc is taken as an example. However, the logic operation circuit 16 of the present embodiment is not limited to use the shift signal Sh(n) and the power start reset signal Srstp to generate the system reset signal Srstc. In another example, referring to FIG. 6, the inverter 16c' in the logic operation circuit 16' generates an inverted output trigger signal DOIv according to the output trigger signal DOI; the delay circuit 16b' in the logic operation circuit 16' The delayed inverting output signal DOIv delay delay time DT is output as the inverted signal DOIv' to the gate 16a'; and the gate 16a is used to generate a system reset in response to the inverted signal DOIv' and the power start reset signal Srstp operation. Signal Srstc. Thus, the logic operation circuit 16' can also generate the system reset signal Srstc according to the output trigger signal DOI and the power start reset signal Srstp.

The frequency divider circuit of the embodiment generates an internal reset signal enabling frequency dividing unit in response to the input trigger signal being converted into a driving edge of the enabling level, so that the frequency dividing unit can generate the frequency dividing clock signal correspondingly, wherein The frequency clock signal triggers the conversion to the driving edge of the enabling level during the period in which the input trigger signal is in the enabled level. Thus, the frequency divider circuit of the present embodiment has the advantage of ensuring that the frequency-divided clock signal can trigger a particular driving edge in a certain period of time compared to a conventional gate driver.

In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧gate driver

10‧‧‧DISP circuit

20‧‧‧Shift register

25‧‧‧Logical Circuit

30‧‧‧Output enable control circuit

40‧‧‧ position shifter

50‧‧‧Output buffer

12‧‧‧Reset unit

DF1, DF2‧‧‧D type flip-flop

14‧‧‧Dividing unit

14b, 16c, 16c'‧‧‧ Inverters

16, 16'‧‧‧Logical Operation Circuit

16a, 16a’‧‧‧ and gate

16b, 16b'‧‧‧ delay circuit

FIG. 1 is a timing diagram of related signals according to a conventional shift register.

2 is a block diagram of a gate driver in accordance with an embodiment of the present invention.

Fig. 3 is a detailed block diagram of the frequency divider circuit 10 in Fig. 2.

FIG. 4 is a timing diagram of related signals of the frequency divider circuit 10 of FIG.

Fig. 5 is a block diagram showing the logic operation circuit in the frequency divider circuit 10 of Fig. 1.

Fig. 6 is a block diagram showing another logic operation circuit in the frequency divider circuit 10 of Fig. 1.

12‧‧‧Reset unit

DF1, DF2‧‧‧D type flip-flop

14‧‧‧Dividing unit

14b‧‧‧Inverter

Claims (15)

A gate driver is configured to generate a plurality of gate signals through a plurality of channels in response to an original clock signal and an input trigger signal, the gate driver comprising: a frequency divider circuit ( Frequency Divider), comprising: a reset unit, responsive to an enable level of a system reset signal, in response to the input trigger signal transition being one of the first driving edges (Driving) Edge) sets an internal reset signal to enable level: and a frequency division unit that is enabled in response to the enable level of the internal reset signal in response to the original clock signal transition being enabled A second driving edge samples a feedback signal to determine a frequency division clock signal, wherein the feedback signal is an inversion of the frequency division clock signal; and a shift register circuit (Shift Register) And generating the gate signals in response to the frequency division clock signal and the input trigger signal. A gate driver as shown in claim 1 wherein the reset unit comprises: a flip-flop circuit responsive to an enable level of the system reset signal to respond A reference voltage is sampled at a Rising Edge of the input trigger signal to generate the internal reset signal, and the flip-flop circuit is further configured to respond to the non-enabled level reset of the system reset signal The internal reset signal is a non-enabled level. The gate driver of claim 1, wherein the frequency dividing unit comprises: a flip-flop circuit responsive to an enable level of the internal reset signal Enabled, in response to the positive edge of the original clock signal, sampling the feedback signal to generate the frequency-divided clock signal, and the flip-flop circuit is further configured to respond to the non-enabling of the internal reset signal The level resets the frequency-divided clock signal to a non-enabling level; and an inverter (Inverter) performs an inversion operation on the frequency-divided clock signal. The gate driver of claim 1, wherein the frequency divider circuit further comprises: a logic operation circuit for generating the system reset according to a first control signal and a power start reset signal operation. Signal. The gate driver of claim 4, wherein: the first control signal is an output trigger signal; the logic operation circuit comprises: a delay circuit for delaying a second control signal by a delay time Outputting, the second control signal is an inversion of the first control signal; and an AND gate is configured to generate the system reset in response to the second control signal and the power start reset signal operation Signal. The gate driver of claim 4, wherein: the first control signal is a gate signal; the logic operation circuit comprises: a delay circuit for delaying a second control signal by a delay time And outputting, the second control signal is an inversion of the first control signal; and a gate is configured to generate the system reset signal in response to the second control signal and the power start reset signal operation. A frequency divider circuit (Frequencv Divider) for An original clock signal generates a frequency-divided clock signal, the frequency divider circuit comprising: a reset unit, responsive to an enable level of a system reset signal, in response to the input trigger The signal transition is enabled. The first driving edge (Driving Edge) sets an internal reset signal to enable level: and a frequency dividing unit is enabled in response to the enabling level of the internal reset signal. In response to the original clock signal being turned into one of the enabled second driving edges, a feedback signal is sampled to determine a frequency division clock signal, wherein the feedback signal is the inverse of the frequency division clock signal phase. The frequency divider circuit as shown in claim 7, wherein the reset unit comprises: a flip-flop circuit, which is enabled in response to an enable level of the system reset signal, In response to the Rising Edge of the input trigger signal, a reference voltage is sampled to generate the internal reset signal, and the flip-flop circuit is further configured to respond to the non-enable level of the system reset signal The internal reset signal is set to a non-enabled level. The frequency divider circuit of claim 7, wherein the frequency dividing unit comprises: a flip-flop circuit responsive to an enable level of the internal reset signal to be responsive to the original time The positive edge of the pulse signal samples the feedback signal to generate the frequency-divided clock signal, and the flip-flop circuit is further configured to reset the frequency-divided clock in response to the non-enabling level of the internal reset signal. The signal is a non-enabled level; and an inverter (Inverter) is used to reverse the frequency division clock signal Phase operation. The frequency divider circuit of claim 7, wherein the frequency divider circuit further comprises: a logic operation circuit, configured to generate the system weight according to a first control signal and a power supply start reset signal operation. Signal number. The frequency divider circuit of claim 10, wherein: the first control signal is an output trigger signal; the logic operation circuit comprises: a delay circuit for delaying a second control signal by a delay time And outputting the second control signal to the first control signal; and an AND gate for generating the system reset signal in response to the second control signal and the power start reset signal operation . The frequency divider circuit of claim 10, wherein: the first control signal is a gate signal; the logic operation circuit comprises: a delay circuit for delaying a second control signal by a delay time The second control signal is related to the first control signal; and a gate is used to generate the system reset signal in response to the second control signal and the power start reset signal operation. A signal control method for generating a frequency-divided clock signal, the signal control method comprising: sampling a reference voltage in response to an input trigger signal transition state being a first driving edge (Driving Edge) Set an internal weight The signal is an enable level: an inversion operation is performed on the frequency-divided clock signal to provide a feedback signal; and an enable level is enabled in response to the internal reset signal to enable the divider circuit to cause the division The frequency converter circuit samples the feedback signal in response to a second clock edge of the original clock signal to determine the frequency division clock signal. The method of controlling the signal as shown in item 13 of the patent application includes: resetting the internal reset signal to a non-enabling level in response to the non-enabled level of the system reset signal; and responding to the internal weight The non-enabled level of the set signal resets the divided clock signal to a non-enabled level. The signal control method of claim 13 further includes: generating a system reset signal in response to a power start reset signal and a control signal operation.