A7 B7A7 B7
Ιίί ψα 標 準 局 員 工 消 費 合 作 衽 印 製 五、發明説明（ry~ 、、本發明係有關於-後掃瞄推動器， 液晶顯不器的掃聪换動器㈤⑽如撕）。… ' 向液晶模組電路大致上係包括:液晶板4平方 ，信號;垂直方向液晶推動器 用以知r田水千線；及電源供應電路。 液晶掃瞒推動器的習知架構係如第1圖所^豆 數個D型正反哭 s 1ηΗ π不，其包括·複 >、+i— 1Qd及後數個及閘12a至⑽。由 則型正反器1〇a至1〇d所構 一輸入時脈信號_控制，將-輪入资二3 ， '位，且每-級正反器的輪出與一輪以f曝移 閑山至12d的運算再輪出爲掃瞒信號^號_經由及 凊參閲第5圖，其繪示了第1网一 時序關#。义 卜 圖〈黾路中各信號間的 f序關係。則述輸入貪料信號贝實 號，當此信號輪入至正反器10a，則在正脈衝信 升邊緣處，正反器10a的輪出會變爲高^_=的上 信號CLK1的下-個上升邊緣處，再 後=時脈 假估耠屮好叫巧兒么變爲低電位。 假使輸出致此信號_始終保持爲高電位表心 號，則經由及閑12a的運算，會輪出„信 號CLK1週期的掃瞄倍號別。然後，正脈二：0了信 期的時脈信號㈣，就移位至下— 出變爲高電位。因此，經由及閘12a =卜使-輪 掃瞒信號X0至腿依序輪出爲持續1運^後輪出的 的高電位信號。 個時脤信號CLIU週期 前述的掃瞄推動器電路在掃瞄點數较低時並没有 -3 - 友 本紙張纽適用中國國家擦準（CNS) M雜（21〇><297公董 (請先閲讀背面之注意事項再填寫本頁)Ιίί ψα Standard bureau staff cost co-operation 衽 Printing V. Description of the invention (ry ~, The present invention is related to the-post-scanning pusher, and the Sonic switch of the LCD monitor is torn). … ”The circuit to the liquid crystal module basically includes: 4 squares of LCD panel, signal; vertical direction liquid crystal pusher for knowing Rizumi line; and power supply circuit. The conventional structure of the liquid crystal concealment pusher is as shown in Fig. 1. Several D-shaped positive and negative crying s 1ηΗ π is not included, which includes · complex >, + i—1Qd and the following ones, and the gates 12a to ⑽. An input clock signal _ control is constructed by regular type flip-flops 10a to 10d, which will be used to input 2 to 3, 'positions, and the rotation of each stage of flip-flops will be shifted with f. The calculation from Xianshan to 12d is turned out as a signal of concealment. ^ Pass and 凊 Refer to Figure 5, which shows the first network a timing off #. Meaning 图 Figure <f-order relationship between signals in Kushiro. The input signal is the real number. When this signal turns into the flip-flop 10a, at the rising edge of the positive pulse signal, the round-out of the flip-flop 10a will become high ^ _ = lower than the upper signal CLK1. -At a rising edge, and then afterwards = clock false estimation, what is the reason for Qiaoer to become a low potential? If the output causes this signal _ to always remain at the high-potential heartbeat number, then through the calculation of Idle 12a, the scanning signal number cycle of the CLK1 cycle will be rotated. Then, the positive pulse 2: the clock of the letter period The signal ㈣ is shifted to the bottom-out and becomes a high potential. Therefore, through the gate 12a = the messenger-wheel sweep signal X0, the legs are sequentially turned out as a high-potential signal that lasts for 1 round. The timing of the CLIU cycle of the time signal is not as low as -3 when the number of scanning points is low-Youben Paper New Zealand is applicable to China National Calibration (CNS) M Miscellaneous (21〇 > < 297) (Please read the notes on the back before filling this page)
經濟夬操隼局員工消費合作社印製 A7 —… ! π ~— -------- -^______ 五、發明説明（) 的問蝻’但疋一旦掃瞄點數提高至240點或360點以上時 ’此種習知電路中使用的D型正反器將會佔用甚高比例的 製作成本。 有鑑於此，本發明特別提出一種掃瞄推動器，其主要 係利用閃鎖（Latch)取代習知掃瞒推動器中使用的正反器 、’同時配合脈波信號的邏辑組合，藉以傳遽高電位信號， 並且本，明之掃瞄推動器的製作成本在液晶顯示器的掃瞒 點數愈高的情況下’越接近於習知電路製作成本的—半， 具有高度的產業上之利用價値。 ) 請參閲第2圖，上述本發明之掃瞒推動器主要係包括 :複數個問鎖2Ga至2Qd，其依序串接而形成一移位暫存 $架構，且受-第—時脈信航瓢第二時脈信號c聰 交(IT的控制，而將輪入的資料信號贝依序傳遞至下一級閂 鎖中；一反相器24,用以將前述第—時脈信號⑽反相而 1產生前述第二時脈信號CLK2B;禕數個及閘2仏至22(1，用 以對應地接收前述旗數_鎖恤至2〇“說出，同時分 別交錯地連接至前述反相器㈣輸入端及輪出端，以分別 接收前述第-時脈信號CLK2及第二時脈信號Μ2Β，並且 受到-輸出致能信號_的_，藉叫定是否將掃瞒信 1號別至XN中的高電位信號輸出。. 上述本發明之掃瞄推動器的架構雖和第i圖中繪示的 習知掃瞄推動器架構有些類似，但因正反器和問鎖特性不 同，故在本發明中使用的輸入資料信號及時脈、信號和習知 .者有很大的不固。 ' .... 、 1----- 本紙張尺度逋用中國國家標準（CNS) A4规格（210 x 297公楚）笨~--— .(請先*«讀背面之注意事項再填寫本頁) -裝 .1Τ B7 B7 5 ) 經濟央標準局員工消費合作社印製 ) 圖 五、發明説明（J ) ~ ——~~一·一~— $外，請參閲第3a圖及第3b圖，.第3a«鱗示一D型 正反器30，，雨個蝓入琅晷c及ϋ ，而其輪出埠爲〇 關則係繪示以問齡成的第3 a圖之D型正反器3〇的等效 電路圖’其包括了兩個問鎖32a及32b，和—個反相器％ 。經由第3a圖及第扑圖的説明，很清楚灰可以兔出—個正 反器的製作所需的面積和成本大约會是一個閃鎖的兩件。 因此，本發明中使用問鎖的特點，可大幅地降低電㈣ 作成本。 爲了更清楚地揭露本發明之架構，方法及特徵， 合附圖説明有關本發明的較佳實施例如下： 附圖之簡要説明 第1圖係、續示習知掃瞄推動器的電路圖； 圖第2圖係績示本發明之掃瞒推動器的—實施例之電路 第繪示一D型正i器魄圖.兮； 第3b圖银繪士以問鎖構成之第3a圓由㈣正 效電路圖之圖式； - < 勺寺 第4圖係繪示本發明之一較佳實施例的電路圖. 第5圖係繪示應用於第丄圖之電路中的信號之時序圖 第6圖係繪示應用於第4圖之電路中的各信號之時序 第7圖係繪示另一應用於第4圖之電路 時序圖。 叫邑號之 本紙張尺度適用中國國家標準（CNS ) 公釐）Printed by A7 of the Consumer Affairs Cooperative of the Economic Affairs Bureau —…! Π ~ — ---------^ ______ V. Questions about the invention description () But once the scanning points are increased to 240 points or Above 360 points' D-type flip-flops used in this conventional circuit will occupy a very high proportion of production costs. In view of this, the present invention particularly proposes a scanning thruster, which mainly uses a latch to replace the flip-flop used in the conventional sweeping thruster, and a logic combination that simultaneously cooperates with the pulse signal to transmit遽 High-potential signal, and the production cost of Mingzhi's scanning pusher is higher when the number of concealment points of the LCD monitor is' closer to the cost of conventional circuit production—half, which has a high industrial use price. . ) Please refer to FIG. 2. The above-mentioned concealment pusher of the present invention mainly includes: a plurality of interrogation locks 2Ga to 2Qd, which are serially connected to form a shift temporary $ structure, and are subject to the -first-clock The second clock signal of the air navigation scoop is controlled by Congjiao (IT), and the data signal in turn is sequentially transferred to the next-level latch; an inverter 24 is used to transmit the aforementioned first clock signal. Inverted and 1 generates the aforementioned second clock signal CLK2B; several numbers and gates 2 to 22 (1, to receive the aforementioned flag number _ lock shirt to 2 ″ correspondingly, and at the same time are connected to the aforementioned The inverter 及 input terminal and the wheel output terminal respectively receive the aforementioned -clock signal CLK2 and the second clock signal M2B, and receive the -output enable signal __ to determine whether or not to conceal the letter 1 Do not output the high-potential signal in XN. Although the structure of the above-mentioned scanning pusher of the present invention is somewhat similar to the conventional scanning pusher structure shown in Figure i, the characteristics of the flip-flop and interlock are different. Therefore, the input data signals, clocks, signals, and knowledge used in the present invention are very unsteady. '...., 1 ----- this paper Zhang Zhiyi uses the Chinese National Standard (CNS) A4 specification (210 x 297 male Chu) stupid ~ ---. (Please * «read the notes on the back before filling this page)-installed. 1T B7 B7 5) Economic Central (Printed by the Consumer Cooperatives of the Bureau of Standards) Figure V. Description of the invention (J) ~ —— ~~ 一 · 一 ~ — $ Except, please refer to Figure 3a and Figure 3b. Inverter 30, the rain goes into Lang 晷 c and ϋ, and its round port is 0. The equivalent circuit diagram of D-type flip-flop 30 shown in Fig. 3a is shown as its age. It includes two interlocks 32a and 32b, and an inverter%. According to the description of Figure 3a and Figure 3, it is clear that gray can be produced. The area and cost required for the production of a flip-flop are approximately It is two pieces of a flash lock. Therefore, the use of the feature of the interlock in the present invention can greatly reduce the electrical operation cost. In order to more clearly disclose the structure, methods and features of the present invention, the description of the present invention will be described with reference to the drawings. The preferred embodiment is as follows: Brief description of the drawings FIG. 1 is a circuit diagram of a conventional scanning pusher; FIG. 2 is a view showing a concealing pusher of the present invention —The circuit diagram of the embodiment shows a D-shaped positive device diagram. Xi; FIG. 3b A diagram of the 3a circle made by a silver painter with an interlock and a positive circuit diagram of ㈣;-< Fig. 4 of a spoon temple FIG. 5 is a circuit diagram showing a preferred embodiment of the present invention. FIG. 5 is a timing chart showing signals applied to the circuit of the first diagram. FIG. 6 is a diagram showing signals applied to the circuit of the 4th diagram. Figure 7 of the timing diagram shows another timing diagram of the circuit applied to Figure 4. The paper size called Yipiao applies the Chinese National Standard (CNS) mm)
Α7 Β7 Τ： 五、發明、説明（y 個pji:參閲第^圖，本發明之一較佳實施例係包括：複數 立至5〇c，依序串接以形成一移位暫存的架構， 帛時脈>(§號(^|(2及-第二時脈信號CLK2B交互控 纺’用以輪入資料信號，並且將資料信號依序傳遞至下一 "貞中，反相器54，用以將前述第一時脈信號CLK2反 藉以產生—第二時脈信號CLK2B ;複數個及閘似至伽 用=對應地接收前述複數個閃鎖5〇a至5〇c的輸入及輸出 D山LO ^)LN，同時分财錯地連接至前述反相器％的輪八 及知出端’用以分別接收前述第—時脈信號㈣2及前述 :時脈^號〇刪，並且受到-輪出致能信號_的控制 ，藉以決定是否將高電位信號輪出至液晶顯示器上。 在本a施例中，爲了和第i圖之習知架構做一比較， 故#包括’頻電路4〇，藉以當本實施例中和第i圖之習 知架構中的輸人㈣信糾細，讀以時祕號均爲 =K1時，前述除頻.電路40可將輪入資料信號DI及輸入時脈 仏號志實.遂L例中需整的輪入資料信號Dn及第 一時脈佗號⑶以。其中，前述除頻電路4〇係包括：兩個乃 型正反器41及42，-或閘43及-非同步重置7型正反器从 及-反相器。兩個D型正反器41和42和反相器及或閣_ 用以接收輪入資料信號01，並受輸入時脈信號CLK1控制， 將其轉換後輸出爲資料信號Du 。f非同步重，置τ型正反 器44則用以直接將輪入時脈信號CLK1除頻並根據DI信號進 行重置而得到第一時脈信號CLK2。 請參閲第6圖或第7圖， ~ 6 - 同時參照第4圖中的電路，Α7 Β7 Τ: 5. Inventions and descriptions (y pji: see Figure ^, a preferred embodiment of the present invention includes: a plurality of numbers to 50c, serially connected to form a shift temporary storage Architecture, 帛 Clock > (§ number (^ | (2 and-the second clock signal CLK2B interactive control spinning) is used to rotate the data signal, and sequentially transfer the data signal to the next " A phaser 54 is used to generate the first clock signal CLK2 in reverse—the second clock signal CLK2B; a plurality of gates and gates are used to receive the corresponding plurality of flash locks 50a to 50c correspondingly. The input and output D mountain LO ^) LN, while at the same time connected to the aforementioned inverter% of the wheel eight and know the terminal 'to receive the aforementioned-clock signal ㈣2 and the aforementioned: clock ^ number 〇 delete And is controlled by the -turn-out enable signal _ to determine whether to rotate the high-potential signal to the LCD. In this embodiment, in order to compare with the conventional architecture of FIG. I, #include 'Frequency circuit 40', so that when the input message is corrected in this embodiment and in the conventional architecture of Fig. I, when the secret number is K1, The circuit 40 can record the data input signal DI and the input clock signal 实. Therefore, in the example L, the data signal Dn and the first clock signal ⑶ which need to be integrated are used. Among them, the frequency division circuit 4 described above 〇 system includes: two non-type flip-flops 41 and 42, or gate 43 and-asynchronous reset 7 type flip-flop and-inverter. Two D-type flip-flops 41 and 42 and inverter It is used to receive the turn-in data signal 01, and is controlled by the input clock signal CLK1, and converts it into a data signal Du. F is asynchronously re-synchronized, and a τ-type flip-flop 44 is used to directly convert The clock signal CLK1 is divided by frequency and reset according to the DI signal to obtain the first clock signal CLK2. See Figure 6 or Figure 7, ~ 6-Also refer to the circuit in Figure 4,
本紙&度適用中國國家標準（CNS ) A4^i7lT〇^297^i7 五、發明説明（υ ) '—：- 其中’第6圖與第7圖的差別是㈣之知始相位反相，亩 到DI信號之前緣才開始同相。當輸入的時脤信號爲， 且輸入資料信號細（㈣以掃瞒液晶顯^ ς 1電^ 脈衝信號），則經由前述除頻電路40後，分別得到 脈信號CLK2及第三輪入資料信號DII 。其中，第一時ϋ 號CLK2在經過反相器54後得到—第二時脈信號。而 第三輸入資料信號DII财複數個問鎖5〇a至5〇c中，隨著 第一時脈信號CLK2及第二時脈信號(^1(2；8的週期變化，而 逐級傳遞下去，各級的輪出分別爲DL〇和DLN。如此，合 10 致能信號0ΕΝ均爲高電位時，第一時脈信號CLK2、第二"時 脈信號CLK2B及各級問鎖的輸出入資料信號DL〇、DU、沉2 至DLN在經過複數個及閘52a至52d的運算之後，便得到 輸出爲X0至XN。將此X0至XN的掃瞄信號和利用習知電路產. 生的掃瞄信號（即第5圖中所示）相比，可得到相同的結 果。也就是說，利用本發明之電路架構，可在輪出入信號 均不變的情況，完全地取代f知的掃瞒推動器㈣路^ 。=利用本發明《電路架構，在掃瞄點愈高時，製作成本 及電路面積愈接近習知電路的—半。 經 濟 央 標 準 Λ 員 工 消 合 作 社 印 製 (請先閲讀背面之注意事項再填寫本頁) 雖然本發明已以一較佳實施例揭露如上，煞其並非用 錄足本發明，任何熟習此項技藝者，在不脱離本發明之 精=範圍内，當可作些許之更動與潤飾，因此本發明之 保護範圚當視後附之申讀專利範圍所界定者爲準。， 本紙張尺度適财ϋ國家轉（cns )从雜（21GX297公楚） , A7 _B7 五、發明說明（芗） 標號說明： 1〇1〜]Od正反器 12a〜】.2d及問 20a〜20d閂鎖 22a~22cl 及閘 24反相器 30 D型正反器 32a〜32b閂鎖 34反相器 40除頻電路 41、42 D型正反器 43或閘 44非同步重置T型正反器 50a~50c 閂鎖 52a 〜52d 及_ 54反相器 (靖先閲讀背面之注*事項再填κ本頁> 經濟部智¾財產局貝工消费合作社印製 參#、条尺度適用中固國家標準<CNS)A4規格（210 297公S )The paper & degree applies the Chinese National Standard (CNS) A4 ^ i7lT〇 ^ 297 ^ i7 V. Description of the Invention (υ) '—:-The difference between Figure 6 and Figure 7 is that the starting phase of the known phase is reversed, Mu is not in phase until the leading edge of the DI signal. When the input time signal is and the input data signal is fine (to hide the LCD display ^ ς 1 electrical pulse signal), the pulse signal CLK2 and the third round data input signal are obtained after the frequency dividing circuit 40 described above. DII. Among them, the first clock signal CLK2 is obtained after passing through the inverter 54-the second clock signal. In the third input data signal DII, a plurality of interlocks 50a to 50c are transmitted step by step as the first clock signal CLK2 and the second clock signal (^ 1 (2; 8) change. Next, the rotations at each level are DL0 and DLN. In this way, when the enable signal 0EN is at a high level, the output of the first clock signal CLK2, the second " clock signal CLK2B, and the locks at all levels The input data signals DL0, DU, Shen2 to DLN are outputted as X0 to XN after a plurality of calculations with the gates 52a to 52d. The scan signals of X0 to XN are generated using a conventional circuit. Compared with the scanning signal (shown in Figure 5), the same result can be obtained. That is to say, by using the circuit architecture of the present invention, the known signal can be completely replaced when the input and output signals are unchanged. Sweeping the pusher ㈣ =. = Using the circuit structure of the present invention, the higher the scanning point, the closer the production cost and circuit area are to the conventional circuit—half. Economic Central Standard Λ Printed by the staff consumer cooperative (please first (Read the notes on the back and fill out this page) Although the present invention has been described in a preferred embodiment As described above, it is not intended to fully record the present invention. Any person skilled in this art can make some modifications and retouching without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should be regarded as The attached patents shall be as defined in the scope of the patent application. The paper size is suitable for financial transfer, national transfer (cns) from miscellaneous (21GX297), A7 _B7 V. Description of the invention (芗) Symbol description: 1〇1 ～] Od Flyback 12a ~]. 2d and 20a ~ 20d latch 22a ~ 22cl and gate 24 inverter 30 D-type inverter 32a ~ 32b latch 34 inverter 40 divider circuit 41, 42 D-type positive and negative Inverter 43 or gate 44 non-synchronous reset T-type flip-flops 50a ~ 50c Latches 52a ~ 52d and _ 54 inverters (Jing first read the note on the back * Matters before filling this page > Ministry of Economic Affairs Intellectual Property Bureau Beige Consumer Cooperative Co., Ltd. prints the parameters, and the scale is applicable to the national solid standard < CNS) A4 specification (210 297 S)