經濟部智慧財產局員工消費合作社印製 513636 6420twf.doc/006 A7 _ B7 五、發明說明（ί ) 本發明是有關於一種PCI匯流排相容結構，特別是一 種支援倍速傳輸之PCI匯流排結構。 第1圖所繪示的便是一般在電腦架構中，使用PCI系 統的一種架構。中央處理器10經由主橋(host bridge)12耦 接到PCI匯流排14。PCI匯流排14則可以耦接多數個PCI 相谷之週邊裝置的主控器（master)16a/16b/16c/16d。每一主 控器均可以送出要求訊號(request，REQ)要求使用PCI匯流 排14，而主橋12中的匯流排仲裁器(arbiter)則可送出核准 訊號(grant，GNT)給主控器，同意其使用PCI匯流排14。 PCI相容裝置（如主控器或電腦晶片組中之北橋）之間 的資料傳送主要係由下列之介面控制訊號所控制。週期框 格訊號(cycle frame，FRAME#)係由起始器(其可以是主控器 或北橋)所送出，用以確認傳輸資料是否爲最後一筆。週期 框格訊號送出時，表示透過PCI匯流排的傳輸資料之交易 (transaction)動作開始進行，當週期框格訊號維持在低準位 則表示傳輸資料交易持續進行。此時，資料位址訊號AD 便會於位址週期期間送出有效位址(valid address)，同時會 在命令/位元組致能(command/byte enable，CBE[3:0])送出有 效的匯流排命令，用以對回應器指出起始器所要求的資料 /交易型態。緊接所送出的有效位址後，資料位址訊號AD 便送出要傳送的資料，此時期稱爲資料週期，同時於CBE 線送出編碼後匯流排命令之位元組致能訊號，藉以傳送資 料。當週期框格訊號停止送出，就表示交易狀態爲最後一 筆資料傳送，或是已經完成資料傳送。起始器備妥訊號 (請先閱讀背面之注意事項再填寫本頁) tr--------- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 513636 A7 B7 » 4 2 0 twf. doc/006 五、發明說明（2) (initiator ready，IRDY#)與回應器備妥訊號（target ready， TRDY#)，兩者配合使用，用以分別指示起始裝置與回應器 已經備妥而可以進行資料之傳送。在一讀取動作進行時， IRDY#訊號表示起始器準備好接收資料；而在進行一寫入 操作時，TRDY#訊號表示回應器準備好接收資料。停止訊 號（stop，STOP#)，用以指示回應器要求起始器停止目前的 傳輸資料交易行爲。 然而，在傳輸之時，皆根據匯流排時脈訊號33MHz 之時脈傳輸所有的訊號，並依照時脈之上升緣來觸發 (Trigger)，如此，資料訊號於一個時脈週期內只能傳輸一 組資料，所以資料傳輸之速度受限於匯流排之時脈，無法 因應高速資料傳輸的需求。 有鑒於此，本發明是在提供一種在PCI匯流排上傳送 資料的匯流排資料介面、結構及其運作方法，利用匯流排 要求訊號及匯流排核准訊號之接腳來傳送‘33MHz時脈之資 料選通(Data Strobe)訊號，以此資料選通訊號之高電位與與 低電位作爲傳輸之依據，如此，可以相容於原有之PCI匯 流排，且以原有之傳輸時脈做二倍傳輸之動作，以增加整 體資料傳輸之速度。 本發明所提供之一種在PCI匯流排上傳送資料的匯流 排資料介面係應用於PCI匯流排之相容裝置中，而此PCI匯 流排至少具有匯流排核准訊號及匯流排要求訊號，本發明 之匯流排資料介面至少包括：傳送高位元緩衝器、傳送低 位元緩衝器、多工器、仲裁訊號裝置、以及資料分配器。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) · n n i-i n ϋ n n^eJ丨·ΒΙ·ΙΙ * W Ml·丨 ^ 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 513636 6420twf.doc/006 A7 ------B7 五、發明說明（$ ) i述傳送高位元緩衝器係用以接收並暫存傳送高位 元資料’而词樣的，傳送低位元緩衝器係用以接收並暫存 傳送低位元資料。有關本發明之多工器，其耦接至傳送高 位元緩衝器及傳送低位元緩衝器，其接收此匯流排資料介 面之內部匯流排時脈訊號，當內部匯流排時脈訊號爲高電 位時’多工器選擇傳送高位元資料或傳送低位元資料之一 輸出至PCI匯流排上，當內部匯流排時脈訊號爲低電位時， 多工器選擇傳送高位元資料或傳送低位元資料之另一輸出 至PCI匯流排上。 本發明之仲裁訊號裝置以匯流排核准訊號及匯流排 要求訊號二者之一的接腳爲定義其爲傳送資料選通訊號接 腳’而本發明之資料分配器以匯流排核准訊號及該匯流排 要求訊號二者之另一的接腳定義其爲接收資料選通訊號接 腳。當匯流排資料介面輸出資料至PCI匯流排上時，仲裁訊 號裝置依據內部匯流排時脈訊號，在傳送資料選通訊號接 腳上傳送出傳送資料&通訊號。而親接至PCI匯流排之資料 分配器’其依據接收資料選通訊號接腳上的接收資料選通 訊號，由PCI匯流排上接收資料，再分別輸出接收高位元資 料與接收低位元資料。 本發明之一實施例之在PCI匯流排上傳送資料的匯流 排資料介面顯示：如果此匯流排資料介面應用於匯流排主 控裝置，則當此匯流排主控裝置進行寫入資料，亦即輸出 資料至PCI匯流排上時，以匯流排要求訊號的接腳爲傳送資 料選通訊號接腳，當匯流排主控裝置進行讀取資料，亦即 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -----------裝--------訂- ---— I — I (請先閱讀背面之注意事項再填寫本頁) 513636 6420twf . doc/ 006 A7 _ B7 五、發明說明（+)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 6420twf.doc / 006 A7 _ B7 V. Description of the Invention (ί) The present invention relates to a PCI bus compatible structure, especially a PCI bus structure that supports double-speed transmission . Figure 1 shows an architecture that generally uses the PCI system in a computer architecture. The CPU 10 is coupled to the PCI bus 14 via a host bridge 12. The PCI bus 14 can be coupled to a master 16a / 16b / 16c / 16d of most peripheral devices of the PCI phase valley. Each master controller can send a request (REQ) request to use the PCI bus 14, and the bus arbiter in the main bridge 12 can send a grant (GNT) to the master controller. Agreed to use PCI bus 14. The data transfer between PCI compatible devices (such as the host controller or the North Bridge in the computer chipset) is mainly controlled by the following interface control signals. The cycle frame (FRAME #) signal is sent by the initiator (which can be the main controller or the Northbridge) to confirm whether the transmitted data is the last one. When the periodic frame signal is sent, it indicates that the transaction action of transmitting data through the PCI bus is started. When the periodic frame signal is maintained at a low level, it means that the data transmission transaction is continued. At this time, the data address signal AD will send a valid address during the address cycle, and at the same time, it will send a valid address at the command / byte enable (CBE [3: 0]). The bus command is used to indicate to the responder the data / transaction type requested by the initiator. Immediately after the valid address is sent, the data address signal AD sends the data to be transmitted. This period is called the data cycle. At the same time, the byte enable signal of the bus command after the encoding is sent on the CBE line to transmit the data. . When the periodic frame signal stops sending, it means that the transaction status is the last data transmission, or the data transmission has been completed. Starter ready signal (please read the precautions on the back before filling this page) tr --------- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 513636 A7 B7 »4 2 0 twf. Doc / 006 V. Description of the invention (2) (initiator ready (IRDY #) and responder ready signal (target ready, TRDY #) are used together to indicate the starting device respectively And the responder is ready for data transmission. When a read operation is performed, the IRDY # signal indicates that the initiator is ready to receive data; and when a write operation is performed, the TRDY # signal indicates that the responder is ready to receive data. A stop signal (stop, STOP #) is used to instruct the responder to request the initiator to stop the current data transfer transaction. However, at the time of transmission, all signals are transmitted according to the bus clock signal 33MHz, and triggered according to the rising edge of the clock. Therefore, the data signal can only be transmitted in one clock cycle. Data, the speed of data transmission is limited by the timing of the bus, and it cannot meet the needs of high-speed data transmission. In view of this, the present invention is to provide a bus data interface, structure and operation method for transmitting data on a PCI bus, and to use the pins of the bus request signal and the bus approval signal to transmit data of the '33MHz clock' Data Strobe signal, using the data to select the high and low potentials of the signal as the basis for transmission. In this way, it is compatible with the original PCI bus and doubles the original transmission clock. Transmission action to increase the speed of overall data transmission. A bus data interface for transmitting data on a PCI bus provided by the present invention is applied to a compatible device of the PCI bus, and the PCI bus has at least a bus approval signal and a bus request signal. The bus data interface includes at least: transmitting high-bit buffer, transmitting low-bit buffer, multiplexer, arbitration signal device, and data distributor. This paper size applies to China National Standard (CNS) A4 (210 X 297 public love) (Please read the precautions on the back before filling this page) · nn ii n ϋ nn ^ eJ 丨 · ΒΙ · ΙΙ * W Ml · 丨^ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 513636 6420twf.doc / 006 A7 ------ B7 V. Description of the Invention ($) It is used to receive and temporarily transmit the high-order data, and the word, the low-order transmission buffer is used to receive and temporarily transmit the low-order data. With regard to the multiplexer of the present invention, it is coupled to the transmission high-bit buffer and the transmission low-bit buffer, and receives the internal bus clock signal of the bus data interface. When the internal bus clock signal is high potential 'The multiplexer chooses to send either high-bit data or low-bit data to the PCI bus. When the internal bus clock signal is low, the multiplexer chooses to send high-bit data or another low-bit data. One output is on the PCI bus. The arbitration signal device of the present invention defines a pin of one of the bus approval signal and the bus request signal as a pin for transmitting data selection signals, and the data distributor of the present invention uses the bus approval signal and the bus The other pin of the request signal is defined as the signal selection pin for receiving data. When the bus data interface outputs data to the PCI bus, the arbitration signal device sends the transmission data & communication number on the transmission data selection signal pin according to the internal bus clock signal. The data distributor that is connected to the PCI bus ′ selects the received data strobe signal on the pin of the received signal according to the received data, receives the data from the PCI bus, and outputs the received high-level data and the received low-level data, respectively. According to an embodiment of the present invention, a bus data interface for transmitting data on a PCI bus shows that if the bus data interface is applied to a bus master control device, when the bus master control device writes data, that is, When outputting data to the PCI bus, use the pin of the bus request signal as the transmission data to select the signal pin. When the bus master control device reads the data, that is, 6 paper standards are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----------- install -------- order- ----- I — I (Please read the notes on the back before filling this page ) 513636 6420twf .doc / 006 A7 _ B7 V. Description of the invention (+)
由PCI匯流排上接收資料時，以匯流排核准訊號的接腳爲接 收資料選通訊號接腳；如果此匯流排資料介面應用於匯流 排橋接裝置，而此匯流排橋接裝置依據匯流排要求訊號及 匯流排核准訊號，來仲裁PCI匯流排之主控權，則當匯流排 橋接裝置輸出資料至PCI匯流排上時，以匯流排核准訊號的 接腳爲傳送資料選通訊號接腳，當匯流排橋接裝置由PCI 匯流排上接收資料時，以匯流排要求訊號的接腳爲接收資 料選通訊號接腳。 ^ 本發明另提供一種在PCI匯流排上傳送資料的匯流排 結構，特別強調的是，本發明主要利用？(:1匯流排上所具有 之匯流排核准訊號及匯流排要求訊號之訊號接腳，本發明 之匯流排結構至少包括：傳送相容裝置及接收相容裝置， 兩者皆耦接至PCI匯流排，以在PCI匯流排上傳輸資料。其 中傳送相容裝置中至少包括：傳送高位元緩衝器、傳送低 位元緩衝器、多工器以及仲裁訊號裝置。而接收相容裝置 至少包括資料分配器。 上述傳送高位元緩衝器係用以接收並暫存傳送高位 元資料。同樣地’傳送低位元緩衝器係用以接收並暫存傳 送低位元資料。至於本發明之多工器，其耦接至傳送高位 元緩衝器及傳送低位元緩衝器，其接收傳送相容裝置中之 第一內部匯流排時脈訊號，當第一內部匯流排時脈訊號爲 闻電位時’多工器選擇傳送高位元資料與傳送低位元資料 二者之一輸出至PCI匯流排上，當第一內部匯流排時脈訊號 爲低電位時’多工器選擇傳送高位元資料與傳送低位元資 个Am尺哎遇用中國國家標準(CNS)A4規格（210>Γ297公爱） (請先閱讀背面之注意事項再填寫本頁) _裝 — — — — — — — — 經濟部智慧財產局員工消費合作社印製 513636 6420twf.doc/006 A7 _ B7 五、發明說明（$ ) 料之另一輸出至PCI匯流排上。當傳送相容裝置輸出資料至 PCI匯流排上時，上述仲裁訊號裝置依據第一內部匯流排時 脈訊號’在匯流排核准訊號及匯流排要求訊號二者之—的 接腳上傳送出資料選通訊號。至於本發明之接收相容裝置 中的資料分配器，依據上述的資料選通訊號，由PCI匯流排 上接收資料，再分別輸出接收高位元資料與接收低位元資 料。 本發明之一實施例之在PCI匯流排上傳送資料的匯流 排結構顯示：如果傳送相容裝置係應用於匯流排主控裝 置，而接收相容裝置係應用於匯流排橋接裝置，則當匯流 排主控裝置輸出資料至PCI匯流排上時，係以匯流排要求訊 號的接腳來傳送出資料選通訊號；如果接收相容裝置係應 用於匯流排主控裝置，而傳送相容裝置係應用於匯流排橋 接裝置，則當匯流排主控裝置由PCI匯流排上接收資料時， 係以匯流排核准訊號的接腳來接收資料選通訊號。上述匯 流排橋接裝置依據匯流排要求訊號及匯流排核准訊號，來 仲裁PCI匯流排之主控權。 本發明利用匯流排要求訊號及匯流排核准訊號之接 腳來傳送33MHz時脈之資料選通訊號，且以此資料選通訊 號之上升緣與下降緣作爲傳輸之依據，如此，可以相容於 原有之PCI匯流排，又可以利用原33MHz時脈做二倍資料 傳輸之動作。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂------I ! ^ 經濟部智慧財產局員工消費合作社印製 513636 A7 6420twf.doc/006When receiving data from the PCI bus, the pin of the bus approval signal is used to select the signal pin for receiving data; if this bus data interface is applied to a bus bridge device, and this bus bridge device is based on the bus request signal And the bus approval signal to arbitrate the master control of the PCI bus. When the bus bridge device outputs data to the PCI bus, the pin of the bus approval signal is used as the data transmission pin. When the bus bridge device receives data from the PCI bus, the pin of the bus request signal is selected as the signal pin for receiving data. ^ The present invention also provides a bus structure for transmitting data on a PCI bus. It is particularly emphasized that the present invention mainly uses? (: 1 The signal pins of the bus approval signal and the bus request signal on the bus. The bus structure of the present invention includes at least: a transmitting compatible device and a receiving compatible device, both of which are coupled to the PCI bus. To transmit data on the PCI bus. The transmission-compatible devices at least include: transmitting high-bit buffers, transmitting low-bit buffers, multiplexers, and arbitration signal devices. The receiving-compatible devices include at least a data distributor. The above-mentioned transmission high-order buffer is used to receive and temporarily store the transmission of high-order data. Similarly, the 'transmission low-order buffer is used to receive and temporarily store the transmission of high-order data. As for the multiplexer of the present invention, it is coupled To the transmission high-order buffer and the transmission low-order buffer, which receive the first internal bus clock signal in the transmission compatible device, when the first internal bus clock signal is the snoop potential, the multiplexer selects to transmit the high bit One of the metadata and the transmission of low-level metadata is output to the PCI bus. When the clock signal of the first internal bus is low, the multiplexer chooses to transmit high Metadata and transmission of low-level assets: Am-footer, China National Standard (CNS) A4 specification (210 > Γ297 public love) (Please read the precautions on the back before filling this page) _ 装 — — — — — — — — Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 6420twf.doc / 006 A7 _ B7 V. Description of the Invention ($) Another output of the data is output to the PCI bus. When transmitting compatible device output data to the PCI bus At the time, the above arbitration signal device transmits a data selection signal on the pin of both the bus approval signal and the bus request signal according to the first internal bus clock signal. As for the receiving compatible device of the present invention, The data distributor selects the communication number according to the data, receives data from the PCI bus, and then outputs the received high-bit data and the received low-bit data. A bus for transmitting data on the PCI bus according to an embodiment of the present invention. Structure display: If the transmitting compatible device is applied to the bus master control device and the receiving compatible device is applied to the bus bridge device, when the bus master control device is output When data is sent to the PCI bus, the data selection signal is sent by the pin of the bus request signal; if the receiving compatible device is applied to the bus master control device, and the transmission compatible device is applied to the bus bridge Device, when the bus master control device receives data from the PCI bus, it uses the pin of the bus approval signal to receive the data selection signal. The above-mentioned bus bridge device according to the bus request signal and the bus approval signal, To arbitrate the master control of the PCI bus. The present invention uses the pins of the bus request signal and the bus approval signal to transmit the 33MHz clock data selection signal, and uses the rising edge and falling edge of the data selection signal as The basis of transmission, in this way, can be compatible with the original PCI bus, and can use the original 33MHz clock to double the data transmission action. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description. This paper size applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) (Please read the precautions on the back before filling out this page) ▼ Install -------- Order ------ I! ^ Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 A7 6420twf.doc / 006
五、發明說明（6 ) 經濟部智慧財產局員工消費合作社印製 說明如下： 圖式之簡單說明： 第1圖繪示的是習知之PCI匯流排基本架構之方塊 圖； 第2圖繪示的是依照本發明之一較佳實施例的一種支 援二倍傳輸模式的PCI匯流排結構傳輸狀態之方塊圖； 第3圖繪示的是依照本發明之一較佳實施例的一種支 援二倍傳輸模式的PCI匯流排結構之時序圖形； 第4圖繪示的是依照本發明之一較佳實施例的一種具 有二倍傳輸模式的PCI匯流排結構上之相容裝置之方塊 圖； 第5圖繪示的是第4圖中的具有二倍傳輸模式的PCI 匯流排相容裝置中的資料分配器之方塊圖；以及 第6圖繪示的是第5圖與第4圖中PCI匯流排相容裝 置之時序圖形。 圖式之標號說明： 10 :中央處理器 11 :系統記憶體 16a/b/c/d，56，58 :主控器 20 :具二倍傳輸之PCI相容裝置 62 :先進先出記憶體 40:先進先出記憶體控制器之延遲結構 52 :具有二倍傳輸之主橋 54 :具有二倍傳輸之主控器 55 :輸出相容裝置 9 (請先閱讀背面之注意事項再填寫本頁)V. Description of the invention (6) The printed description of the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is as follows: A brief description of the diagram: Figure 1 shows a block diagram of the basic structure of a conventional PCI bus; Figure 2 shows FIG. 3 is a block diagram of a transmission state of a PCI bus structure supporting a double transmission mode according to a preferred embodiment of the present invention; FIG. 3 illustrates a method of supporting double transmission according to a preferred embodiment of the present invention. Timing diagram of the PCI bus structure in the mode; FIG. 4 shows a block diagram of a compatible device on the PCI bus structure with a double transmission mode according to a preferred embodiment of the present invention; FIG. 5 FIG. 4 is a block diagram of a data distributor in a PCI bus-compatible device with a double transmission mode in FIG. 4; and FIG. 6 is a diagram showing the phase relationship between the PCI buses in FIGS. 5 and 4 Timing diagram of the device. Description of the drawing numbers: 10: CPU 11: System memory 16a / b / c / d, 56, 58: Main controller 20: PCI compatible device with double transmission 62: FIFO memory 40 : Delay structure of FIFO memory controller 52: Main bridge with double transmission 54: Main controller with double transmission 55: Output compatible device 9 (Please read the precautions on the back before filling this page)
· ϋ I I I n I n^"J· n ϋ ϋ -ϋ I ϋ 1 I %, 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 川636 6 4 2 0 twf . doc / 0 0 6 Ά/ —^_SZ-— _ 五、發明說明（η ) 57 :接收相容裝置 60 :具有二倍傳輸之PCI匯流排相容裝置 64，74:資料緩衝器對 66 :多工器 68 :要求訊號裝置 72 :資料分配器 80，82 :緩衝器 84，86，88，90 :輸出控制器 實施例 本申請案之原理及方法係利用中華民國專利申請案 第88103699號之主要技術內容，在此先予敘明。上述申請 案僅指出在PCI匯流排上傳送資料的系統及方法，本案進 一步揭露實施的裝置與匯流排結構。 請參照第2圖，第2圖繪示的是依照本發明之一較佳 實施例的一種支援二倍傳輸模式的PCI匯流排結構傳輸狀 態之方塊圖。此較佳實施例中包含：本發明之具有二倍傳 輸能力之主控器54與主橋52,以及單純與一般PCI相容的 主控器56/58,本實施例中這些裝置可與原先的PCI匯流排 系統正常運作，絕無不相容的情形發生。 如第2圖所示，並非所有之PCI裝置54/56/58皆支援 二倍傳輸模式，其中只有在具有二倍傳輸之主控器54與具 有二倍傳輸之主橋52作寫入或讀出資料位址訊號時才運 用到二倍傳輸模式，其餘如主控器54/56/58與主控器 54/56/58之間的傳輸，或由主橋52發出命令與主控器 54/56/58之間的傳輸，爲了確保資料之完整皆以原先PCI 相容之控制時脈來傳輸資料。 -----------裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 513636 6420twf.doc/006 A7 B7 五、發明說明（》） (請先閱讀背面之注意事項再填寫本頁) 其中，電腦系統於開機之初首先要偵測主橋52是否 具有二倍傳輸能力，如果主橋52有的話，便立即判別主控 器54、主控器56、以及主控器58是否支援二倍傳輸之模 式，例如：系統之BIOS中列舉所有可支援二倍傳輸模式之 廠商識別碼（Vendor ID)及裝置識別碼(Device ID)，系統比對 主控器54、56、58是否屬於上述之一，藉以判斷主控器是 否支援二倍傳輸模式，這是由於標準PCI匯流排之規格 中，並沒有支援二倍傳輸模式之特殊識別碼的原故；又或 是詢問（Query)組態空間（Configuration Space)中一預定的位 址來識別，只要偵測出任一主控器支援二倍傳輸模式，可 令所有支援二倍傳輸模式之主控器將要求訊號（REQ)致 動，再由主橋52將所有主控器之要求訊號的狀態回報給系 統，就可以確實得知那些要求訊號對應的主控器支援二倍 傳輸模式，並將其結果加以儲存至系統內。系統(例如：BIOS) 依據上述結果，去程式化主橋52，因此主橋52就可以輕 易辨別那些要求訊號所對應的主控器支援二倍傳輸模式。 經濟部智慧財產局員工消費合作社印製 當主橋將匯流排授權核准給具二倍傳輸之主控器 54,且主控器54欲以二倍傳輸模式動作時，具有二倍傳輸 之主控器54則於所發出之資料位址訊號上送出數個可識 ’別的位元組，例如：將位址訊號的最低兩個位元addreSS[l:〇] 設爲2，以告知主橋52將進入二倍傳輸模式。當接收到自 主控器54發出的匯流排命令內的位址訊號之最低兩個位 元等於2時，並且主橋52從核准訊號（GNT)判別主控器54 支援二倍傳輸模式，則主橋就進入二倍傳輸模式。BIOS必 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 513636 6420twf.doc/006 A7 B7 五、發明說明（1 ) 須告訴支援二倍傳輸模式之主控器，可支援二倍傳輸模式 的位址範圍，也就是主橋可接受的位址範圍（通常是系統記 憶體的範圍）。當位址範圍不在主橋可接受的位址範圍時， 則以正常的模式進行傳輸，只有那些在二倍傳輸模式的位 址範圍內的匯流排交易（transaction)可使主橋52與主控器 54進入二倍傳輸模式。另外，雖然主控器54支援二倍傳 輸模式，但其也可將位址訊號的最低兩個位元不設爲2， 例如：address[l:0]等於0，如此，匯流排交易就以正常的模 式進行。因此綜上所述，進入二倍傳輸模式的條件如下： 1. 主橋52將匯流排授權核准給具二倍傳輸之主控器 54 ； · 2. 具有二倍傳輸之主控器54發出之位址訊號的最低 兩個位元address[l:0]設爲2 ;以及 3. 位址訊號的位址範圍支援接受二倍傳輸模式。 以上的條件中，只要缺少任一條件就以正常的模式進行匯 流排交易傳輸。 請參照第3圖，其繪示的是依照本發明之一較佳實施 例的一種支援二倍傳輸模式的PCI匯流排結構之時序圖 形，其中當PCI匯流排於開始傳送資料位址訊號之時(如圖 中之資料位址訊號 D0/D1 /D2/D3/D4/D5/D6/D7/D8/D9)，其皆 是利用REQ訊號上之傳輸選通訊號以觸發栓鎖資料，而於 資料週期時，開始傳輸資料位址訊號D0/D1傳送至PCI匯 流排上，但是被選擇之主橋或主控器備妥訊號TRDY#仍未 確認，因此，主控器再重新傳送資料位址訊號D0/D1，按 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂---------· 經濟部智慧財產局員工消費合作社印製 513636 6420twf.doc/006 A7 B7 五、發明說明（π ) 此，資料位址訊號D4/D5與資料位址訊號D8/D9皆可同理 相推。 週期框格訊號FRAME#在最後一筆資料位址訊號 D8/D9時拉起，用以告知被選擇之主橋或主控器，資料位 址訊號D8/D9爲最後一筆傳輸資料，然而，在資料位址訊 號D8/D9第二次傳送時，STOP#訊號的產生，使得傳輸動 作完全結束。 請參照第4圖，第4圖繪示的是依照本發明之一較佳 實施例的一種具有二倍傳輸模式的PCI匯流排結構上之相 容裝置之方塊圖，此PCI匯流排結構中包括具有二倍傳輸 能力之主控器54與主橋52，此兩個裝置中各包含有各自 的具有二倍傳輸能力之輸出相容裝置與接收相容裝置，其 對應地透過PCI匯流排70而連接在一起，舉例：主控器54 之輸出相容裝置55透過PCI匯流排70，對應地與主橋52 之接收相容裝置57接起來，請注意，當主控器54輸出資 料至PCI匯流排上，以寫入資料進入主橋52所連接之記憶 體(未繪示)時，係以匯流排要求訊號REQ的接腳來傳送出 資料選通(Data Strobe)訊號；同理，主橋52之輸出相容裝 置（未標示)透過PCI匯流排70，對應地與主控器54之接收 相容裝置(未標示）接起來，當主控器54由PCI匯流排上接 收資料，以讀取主橋52所連接之記憶體資料時，係以匯流 排核准訊號GNT的接腳來接收資料選通訊號。 先進先出記憶體62稱接至傳送高位元緩衝器 及傳送低位元緩衝器ADL〇ut，其接收複數個傳送資料，並 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------· 經濟部智慧財產局員工消費合作社印製 513636 6420twf.d〇c/006 A7 B7 五、發明說明（（（） 依序分別傳送其中的傳送高位元資料與傳送低位元資料至 ADH〇UT及ADL謝。資料緩衝器對64之ADW與ADH〇4 照傳送資料AD之先後順序分別接收，並且將所接收到的 資料，以傳送高位元資料與傳送低位元資料分別送至多工 器66。而多工器66則依據匯流排時脈訊號(PCICLKt)之高 電位與低電位（或是上升緣與下降緣）分別將所接收到之資 料位址訊號AD傳輸至PCI匯流排70上。 PCI匯流排70則將資料位址訊號AD傳送至資料分配 器72,而同時匯流排時脈訊號(PCICLKt)藉由仲裁訊號裝置 68，在此爲要求訊號(REQ)裝置68，藉由REQ訊號之傳輸 接腳及傳輸線傳送至資料分配器72,亦即以REQ訊號之傳 輸接腳作爲資料選通訊號的接腳，來傳送頻率與匯流排時 脈訊號一樣的資料選通訊號，當然，經由要求訊號裝置68 之傳輸線所送出之資料選通訊號會和資料一樣，在到達主 橋時，因傳遞而產生延遲之現象。 資料分配器72則依據從要求訊號裝置68之傳輸線所 接收到的資料選通訊號，以及匯流排時脈訊號(PCICLKr)， 將所接收到之資料位址訊號AD加以區隔，並將資料位址 訊號AD分別依序傳送至資料緩衝器對74之接收低位元緩 衝器ADLin與接收高位元緩衝器ADHin*。其中，資料分配 器72所接收之匯流排時脈訊號(PCICLK0，其最主要之目 的是，使得接收的資料AD能在輸出至內部時與內部之匯 流排時脈訊號同步。· Ϋ III n I n ^ " J · n ϋ ϋ -ϋ I ϋ 1 I%, this paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) Chuanchuan 636 6 4 2 0 twf .doc / 0 0 6 Ά / — ^ _ SZ-— _ V. Description of the Invention (η) 57: Receive compatible device 60: PCI bus compatible device 64 with double transmission, 74: Data buffer pair 66: Multiplexer 68: Request signal device 72: Data distributor 80, 82: Buffer 84, 86, 88, 90: Output controller Example The principle and method of this application are using Chinese The main technical content of the Republic of China Patent Application No. 88103699 will be described here first. The above application only points out the system and method for transmitting data on the PCI bus, and this case further discloses the implemented device and bus structure. Please refer to FIG. 2. FIG. 2 is a block diagram showing a transmission state of a PCI bus structure supporting a double transmission mode according to a preferred embodiment of the present invention. This preferred embodiment includes: the main controller 54 and the main bridge 52 with double transmission capability of the present invention, and the main controller 56/58 which is simply compatible with general PCI. In this embodiment, these devices can be compared with the original The PCI bus system operates normally, and no incompatibilities occur. As shown in Figure 2, not all PCI devices 54/56/58 support double transmission mode, and only the master controller 54 with double transmission and the main bridge 52 with double transmission are used for writing or reading. The double transmission mode is used only when the data address signal is output, and the rest such as the transmission between the main controller 54/56/58 and the main controller 54/56/58, or the command issued by the main bridge 52 and the main controller 54 For transmission between / 56/58, in order to ensure the integrity of the data, the original PCI-compatible control clock is used to transmit the data. ----------- Installation -------- Order --------- (Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 mm) 513636 6420twf.doc / 006 A7 B7 V. Description of the invention (") (Please read the precautions on the back before filling this page) Among them, the computer system must first be started Detect whether the main bridge 52 has double transmission capacity. If the main bridge 52 has it, it will immediately determine whether the main controller 54, the main controller 56, and the main controller 58 support the double transmission mode. For example: The BIOS lists all Vendor IDs and Device IDs that can support the double transmission mode. The system compares whether the main controllers 54, 56, and 58 belong to one of the above to determine whether the main controller Supports double transmission mode. This is because there is no special identification code that supports double transmission mode in the standard PCI bus specifications; or it is a predetermined bit in the Query configuration space. Address to identify, as long as it is detected that any master controller supports the double transmission mode, you can make If the master controller that supports the double transmission mode will request the signal (REQ) to be actuated, then the main bridge 52 will report the status of the request signals of all the master controllers to the system. The device supports the double transmission mode and stores the results in the system. The system (for example: BIOS) deprograms the main bridge 52 according to the above result, so the main bridge 52 can easily identify those requesting signals corresponding to the master controller supporting the double transmission mode. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs When the main bridge authorizes the busbar to the master controller 54 with double transmission, and the master controller 54 wants to operate in the double transmission mode, the master with double transmission The device 54 sends several identifiable bytes on the data address signal. For example, the lowest two bits of the address signal addreSS [1: 〇] are set to 2 to inform the main bridge. 52 will enter double transmission mode. When receiving the lowest two bits of the address signal in the bus command from the autonomous controller 54 equal to 2, and the main bridge 52 judges from the approved signal (GNT) that the master controller 54 supports the double transmission mode, then the master The bridge then enters the double transmission mode. The BIOS must comply with the Chinese standard (CNS) A4 specification (210 X 297 mm) 513636 6420twf.doc / 006 A7 B7 V. Description of the invention (1) The master controller supporting the double transmission mode must be told that it can support The address range of the double transmission mode, that is, the address range acceptable to the main bridge (usually the range of system memory). When the address range is not within the acceptable address range of the main bridge, transmission is performed in the normal mode, and only those bus transactions within the address range of the double transmission mode enable the main bridge 52 and the main control The device 54 enters the double transmission mode. In addition, although the main controller 54 supports the double transmission mode, it can also set the two least significant bits of the address signal to not be 2. For example: address [l: 0] is equal to 0. In this way, the bus transaction is based on Proceed in normal mode. Therefore, in summary, the conditions for entering the double transmission mode are as follows: 1. The main bridge 52 authorizes the bus to authorize to the master controller 54 with double transmission; 2. The master controller 54 with double transmission issues The lowest two bits of the address signal address [l: 0] are set to 2; and 3. The address range of the address signal supports double transmission mode. Among the above conditions, as long as any of the conditions is missing, the bus transaction transmission is performed in the normal mode. Please refer to FIG. 3, which illustrates a timing diagram of a PCI bus structure supporting a double transmission mode according to a preferred embodiment of the present invention. When the PCI bus starts to transmit data address signals, (The data address signal D0 / D1 / D2 / D3 / D4 / D5 / D6 / D7 / D8 / D9) in the data address in the figure is used to select the transmission signal on the REQ signal to trigger the latching data. During the data cycle, the data address signal D0 / D1 starts to be transmitted to the PCI bus, but the selected master bridge or master controller has the ready signal TRDY # still unconfirmed. Therefore, the master controller retransmits the data address signal D0 / D1, according to the size of this paper, applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) ▼ 装 -------- Order- -------- · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 6420twf.doc / 006 A7 B7 V. Description of the invention (π) Therefore, the data address signal D4 / D5 and the data address signal D8 / D9 can be used for the same reasoning. The periodic frame signal FRAME # is pulled up when the last data address signal D8 / D9 is used to inform the selected main bridge or master controller. The data address signal D8 / D9 is the last data transmission. However, in the data When the address signal D8 / D9 is transmitted for the second time, the STOP # signal is generated, so that the transmission operation is completely ended. Please refer to FIG. 4. FIG. 4 shows a block diagram of a compatible device on a PCI bus structure having a double transmission mode according to a preferred embodiment of the present invention. The PCI bus structure includes The main controller 54 and the main bridge 52 with double transmission capabilities, each of which includes an output-compatible device and a reception-compatible device with double transmission capabilities, which correspond to each other through the PCI bus 70. Connected together, for example: the output compatible device 55 of the main controller 54 is connected to the receiving compatible device 57 of the main bridge 52 through the PCI bus 70, please note that when the main controller 54 outputs data to the PCI bus On the bank, when writing data into the memory (not shown) connected to the main bridge 52, the data strobe signal is transmitted by the pin of the bus request signal REQ; similarly, the main bridge The output compatible device (not labeled) of 52 is connected to the receiving compatible device (not labeled) of the main controller 54 through the PCI bus 70. When the main controller 54 receives data from the PCI bus, it reads When fetching the memory data connected to the main bridge 52, Approved signal GNT row of pins to receive the data strobe signal. The first-in-first-out memory 62 is said to be connected to the transmission high-order buffer and the transmission low-order buffer ADL0ut, which receives a plurality of transmission data, and the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) (Please read the precautions on the back before filling out this page) -------- Order --------- · Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 6420twf.d〇c / 006 A7 B7 V. Description of the invention ((() Send the high-order data and the low-order data to ADHOOT and ADL respectively in order. The data buffer pairs 64 ADW and ADH〇4 according to the data transmission AD They are received in order, and the received data is transmitted to the multiplexer 66 by transmitting the high-level data and the low-level data. The multiplexer 66 is based on the high potential of the bus clock signal (PCICLKt) and The low potential (or rising edge and falling edge) respectively transmits the received data address signal AD to the PCI bus 70. The PCI bus 70 transmits the data address signal AD to the data distributor 72, and at the same time Bus clock signal (PCICLKt) by arbitration signal Set 68, here is the request signal (REQ) device 68, which is transmitted to the data distributor 72 through the transmission pin and transmission line of the REQ signal, that is, the transmission pin of the REQ signal is used as the data selection signal pin. The data selection signal is transmitted at the same frequency as the bus clock signal. Of course, the data selection signal sent by the transmission line of the request signal device 68 will be the same as the data. When it reaches the main bridge, there will be a delay due to the transmission. The data distributor 72 selects a communication signal based on the data received from the transmission line of the request signal device 68 and a bus clock signal (PCICLKr), separates the received data address signal AD, and divides the data bit. The address signal AD is sequentially transmitted to the receiving low-order buffer ADLin and the receiving high-order buffer ADHin * of the data buffer pair 74. Among them, the bus clock signal (PCICLK0, which is the most important one) received by the data distributor 72 The purpose is to enable the received data AD to be synchronized with the internal bus clock signal when it is output to the inside.
第5圖繪示的是第4圖中的具有二倍傳輸模式的PCI (請先閱讀背面之注意事項再填寫本頁) 訂---------： 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 513636 6420twf.doc/006 A7 B7 五、發明說明（/2) 匯流排相容裝置中的資料分配器72之方塊圖，請參照第5 圖與第4圖。緩衝器8〇從PCI匯流排70所接收到之資料 位址訊號AD送至輸出控制器84/86，又稱爲：正相觸發栓 鎖器86與反相觸發栓鎖器84 (於本實施例以D-TYPE正反 窃爲輸出控制器），其中每一輸出控制器84/86具有資料輸 入端、觸發端及資料輸出端，資料輸入端耦接至資料緩衝 器80之輸出，觸發端耦接至選通訊號緩衝器82之輸出， 以依據接收資料選通訊號(在此爲R.EQ訊號線上的訊號）， 栓鎖住局位兀資料pre ADHin與低位兀資料pre ADLin。 正相觸發栓鎖器88之資料輸入端耦接至反相觸發栓 鎖器84之資料輸出端，其觸發端耦接至內部匯流排時脈訊 號（PCICLKO，以使資料輸入端之資料輸出在資料輸出端 時，亦即輸出接收低位元資料時，與內部匯流排時脈訊號 同步。同理，反相觸發栓鎖器90之資料輸入端耦接至正相 觸發栓鎖器86之資料輸出端，觸發端耦接至內部匯流排時 脈訊號，以使資料輸入端之資料輸出在資料輸出端時，亦 即輸出接收高位元資料時，與內部匯流排時脈訊號同步。 也就是此兩個輸出控制器88/90則依據匯流排時脈訊號分 別將pre ADLin與pre ADHin之訊號輸出，如此可將此二資 料分別輸出至資料緩衝器對74之ADLin與ADH,n中。 如熟悉此藝者可輕易知曉，上述第5圖係將正相觸發 栓鎖器88之資料輸入端耦接至反相觸發栓鎖器84之資料 輸出端，而反相觸發栓鎖器90之資料輸入端耦接至正相觸 發栓鎖器86之資料輸出端，但是本實施例分成兩組栓鎖器 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)Figure 5 shows the PCI with the double transmission mode in Figure 4 (please read the precautions on the back before filling this page). Order ---------: Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs The paper size printed by the cooperative applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 513636 6420twf.doc / 006 A7 B7 V. Description of the invention (/ 2) Bus For a block diagram of the data distributor 72 in the compatible device, please refer to FIG. 5 and FIG. 4. The buffer 80 sends the data address signal AD received from the PCI bus 70 to the output controller 84/86, also known as: normal phase trigger latch 86 and reverse phase trigger latch 84 (in this implementation For example, the D-TYPE is the output controller.) Each output controller 84/86 has a data input terminal, a trigger terminal, and a data output terminal. The data input terminal is coupled to the output of the data buffer 80 and the trigger terminal. The output coupled to the selection signal buffer 82 is used to select a communication signal according to the received data (in this case, a signal on the R.EQ signal line), and latch the local data pre ADHin and the low data pre ADLin. The data input terminal of the positive phase trigger latch 88 is coupled to the data output terminal of the inverse trigger latch 84, and its trigger terminal is coupled to the internal bus clock signal (PCICLKO, so that the data output of the data input terminal is At the data output end, that is, when receiving low-level data, it is synchronized with the internal bus clock signal. Similarly, the data input end of the inverse trigger latch 90 is coupled to the data output of the positive phase trigger latch 86. End, the trigger end is coupled to the internal bus clock signal, so that when the data input end is output at the data output end, that is, when receiving high-level data, it is synchronized with the internal bus clock signal. Each output controller 88/90 outputs the signals of pre ADLin and pre ADHin respectively according to the bus clock signal, so that these two data can be output to ADLin and ADH, n of data buffer pair 74 respectively. If you are familiar with this The artist can easily know that the above-mentioned Fig. 5 is the data input terminal of the normal phase trigger latch 88 coupled to the data output terminal of the reverse phase trigger latch 84 and the data input terminal of the reverse phase trigger latch 90 Coupled to normal phase The data output terminal of the latch 86 is triggered, but this embodiment is divided into two groups of latches. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this page)
513636 6420twf.doc/006 A7 B7 五、發明說明（（>) rtt先閱讀背面之注意事項再填寫本頁) 對之理由主要是必須將資料與內部匯流排時脈訊號取得同 步，故亦可將反相觸發栓鎖器90之資料輸入端耦接至反相 觸發栓鎖器84之資料輸出端，而正相觸發栓鎖器88之資 料輸入端耦接至正相觸發栓鎖器86之資料輸出端。 第6圖繪示的是第5圖與第4圖中PCI匯流排相容裝 置之時序圖形。請同時參照第6圖、第5圖與第4圖，其 中，以資料位址訊號L0與資料位址訊號H0爲例，資料 L0/H0被依序存放至先進先出記憶體62，並分別輸出至資 料緩衝器對64之ADLcurr與ADHqut，並且分別輸出至多工 器66 〇 經濟部智慧財產局員工消費合作社印製 然而，多工器66則依據匯流排時脈訊號(PCICLKt)之 低電位與高電位分別將資料位址訊號L0與資料位址訊號 H0送出至PCI匯流排70,而此時PCICLKt訊號經要求訊號 裝置68,經由REQ之接腳送出資料選通訊號REQ〇UT，再經 由PCI匯流排70延遲後，以REQm傳送至資料分配器72， 根據第6圖可知，資料分配器72依據經傳輸線傳送而延遲 之PCICLKt訊號，亦即資料選通訊號，與匯流排時脈訊號 (PCICLKO將資料位址訊號L0與資料位址訊號H0分別輸出 至資料緩衝器對74之ADLin與ADHin，而其餘之資料位址 訊號皆以相同之方式傳輸。 如熟悉此藝者知曉，第6圖與第5圖係主要解釋主控 器輸出資料至PCI匯流排上，以匯流排要求訊號REQ的接 腳來傳送出資料選通訊號。同理可推知，主橋輸出資料至 PCI匯流排上，而主控器由PCI匯流排上接收資料時，以 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 513636 6420twf.doc/006 A7 _B7_ 五、發明說明（i+) 匯流排核准訊號GNT的接腳來接收資料選通訊號。二者運 作與時序係相類似。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 一裝513636 6420twf.doc / 006 A7 B7 V. Explanation of the invention ((>) rtt first read the notes on the back and then fill out this page) The main reason is that the data must be synchronized with the internal bus clock signal, so it can also be The data input terminal of the anti-phase trigger latch 90 is coupled to the data output terminal of the anti-phase trigger latch 84, and the data input terminal of the non-phase trigger latch 88 is coupled to the non-phase trigger latch 86 Data output. Figure 6 shows the timing diagrams of the PCI bus compatible devices in Figures 5 and 4. Please refer to FIG. 6, FIG. 5 and FIG. 4 at the same time. Among them, taking the data address signal L0 and the data address signal H0 as examples, the data L0 / H0 are sequentially stored in the FIFO memory 62 and are respectively Output to the data buffer pair 64 ADLcurr and ADHqut, and output to the multiplexer 66 〇 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs However, multiplexer 66 is based on the low potential of the bus clock signal (PCICLKt) and High potential sends the data address signal L0 and data address signal H0 to the PCI bus 70 respectively. At this time, the PCICLKt signal sends the data selection signal REQ〇UT via the REQ pin via the request signal device 68, and then via PCI After the delay of the bus 70, it is transmitted to the data distributor 72 with REQm. According to FIG. 6, it can be known that the data distributor 72 delays the PCICLKt signal transmitted through the transmission line, that is, the data selection signal, and the bus clock signal (PCICLKO The data address signal L0 and the data address signal H0 are output to the ADLin and ADHin of the data buffer pair 74, and the rest of the data address signals are transmitted in the same way. If the artist is familiar with this, Figure 6 And Figure 5 mainly explain the output data of the main controller to the PCI bus, and the data selection signal is sent by the pin of the bus request signal REQ. Similarly, it can be inferred that the main bridge outputs data to the PCI bus. And when the main controller receives data from the PCI bus, the Chinese national standard (CNS) A4 specification (210 X 297 mm) applies to this paper size 513636 6420twf.doc / 006 A7 _B7_ V. Description of the invention (i +) bus The pin of the approval signal GNT receives the data selection signal. The operation of the two is similar to that of the timing system. Although the present invention has been disclosed as above with the preferred embodiment, it is not intended to limit the present invention. Various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this (Page) One Pack
n I I ί V n n ϋ n 1-1 «ϋ ϋ I %- 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）n I I ί V n n ϋ n 1-1 «ϋ ϋ I%-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)