JPH07325640A - Standby control circuit - Google Patents

Abstract

PURPOSE:To secure a startup stable time at the time of resonator operation, and to eliminate an unnecessary oscillation time at the time of external clock supply operation and improve response by controlling the operation of a clock generating circuit with the signal outputted from a flip-flop. CONSTITUTION:The signal 103 outputted from the flip-flop 1 and the underflow signal 107 outputted from a counter 4 are inputted and a signal 108 is outputted and inputted to the clock generating circuit 6 and an OR gate 7. The operation of the clock generating circuit 6 is controlled with the signal 108 and the resetting of a counter 4 is controlled. The clock generating circuit 6 inputs the clock signal 104 outputted from an oscillation circuit 2 and outputs specific clock signals 109 and 110 on the basis of the clock signal 104. Consequently, the startup stable time at the time of resonator operation is secured and the unnecessary oscillation stable time at the time of external clock supply operation is eliminated to improve the responsiveness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standby control circuit, and more particularly to a standby control circuit which incorporates a clock signal generation circuit and controls internal and external clock signals in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent semiconductor integrated circuits, particularly in microcomputers formed by such semiconductor integrated circuits, there is a strong demand for low power consumption.
In order to deal with this, the adoption of CMOS technology is being promoted. In addition to the CMOS technology, the original oscillation clock output from the oscillation circuit for generating the clock is stopped during the standby of the microcomputer, so that the semiconductor integrated circuit included in the microcomputer is stopped. A semiconductor integrated circuit has been developed in which the power consumption is minimized by prohibiting the circuit operation.

The setting of the standby state in these microcomputers is generally performed by executing a corresponding instruction by a user program, and the instruction causes the oscillation circuit to stop the original oscillation clock. To be executed. Conversely, when releasing the standby state of the microcomputer,
Original oscillation start processing is performed by the reset terminal number and the like, and execution of the user program is started from a predetermined address. At that time, since the clock is not stable at the rise of the oscillation circuit, supply as an internal clock after a predetermined time until the oscillation by the oscillation circuit stabilizes, or until the oscillation stabilizes. The clock oscillation is performed by causing the counter, which has the count number corresponding to the predetermined time of (1), to be incremented by the oscillation output of the clock and release the internal reset by the overflow signal generated when the set count number is reached. The system is configured so that the oscillation stabilization time of the circuit is secured and the execution of the program is started by a stable clock.

FIG. 6 is a diagram showing an example of a conventional standby control circuit. During standby, the flip prop 18 is set by the stop command 112 sent from the microcomputer.
Then, the clock oscillation of the oscillation circuit 19 is stopped. Standby release is performed by resetting the flip-flop 18 by an active reset signal 113 from the outside. Upon receiving the output of the set flip-flop 18, the clock oscillation in the oscillation circuit 12 is restarted. And at the same time, flip-flop 1
Although the internal reset signal 114 output from the counter 4 is also activated, the reset number for the flip-flop 18 is released by the counter 17 when the internal clock signal output from the oscillation circuit 19 via the Schmitt trigger inverter 20 is released. Is reached, the flip-flop 14 is reset and performed.
Therefore, the program execution is resumed after the oscillation determination stable time is secured for the first time after the predetermined count time in the counter 17 has elapsed.

In such a conventional standby circuit, even in the case of a system in which the microcomputer is operated by the supply of the external clock without using the resonator, the operation is restarted only after the oscillation stabilization time described above has elapsed. Since it cannot be done, there is a problem that the response is poor. In order to deal with this problem, as another conventional example, Japanese Patent Application Laid-Open No. 5-277809 (Japanese Patent Application No. 3-3).
9650), a clock signal control circuit is proposed. The clock signal control circuit according to the present proposal is a clock signal control circuit that includes an oscillator circuit that uses a resonator and a clock signal generation circuit that generates a clock signal based on the output signal of the oscillator circuit. A first control circuit, which is controlled by a reset signal and controls the operation of the oscillation circuit, is initialized by the first control circuit, counts the output signal of the oscillation circuit, and reaches a predetermined count value. And a second control circuit for controlling the count signal, and a third control circuit for controlling the operation of the clock generation circuit by the first and second control circuits. It is characterized by having.

FIG. 7 is a diagram showing an embodiment of a clock signal control circuit according to the proposal, which is an example applied as a clock signal control circuit of a microcomputer. Figure 7
As shown in FIG. 1, the conventional example includes an inverter 21, a flip-flop 22 functioning as a first control circuit,
Flip-flop 28 functioning as a second control circuit
And a flip-flop 2 that functions as a third control circuit
3, an oscillator 24 using a resonator, OR gates 25 and 27, a counter 26, and a clock generation circuit 29. The flip-flop 23 is reset by the output of the counter 26 in advance. It is set by the output of the flip-flop 28, which indicates whether the operation is based on an external clock or an oscillator using a resonator.

The flip-flop 22 is an RS flip-flop, and has a stop instruction 10 of the microcomputer.
2 and a low level reset signal 101
Is reset by the active reset signal 103 which is inverted and output by the inverter 21, and the output controls the operation of the oscillator 24. Counter 26
Counts the oscillation output 104 of the oscillator 24, and outputs an overflow signal 105 when it reaches a predetermined count value after a lapse of a fixed time. The flip-flop 28 is a power-on flip-flop which is initialized to logic "0" when the power is turned on and is set by executing a specific instruction.
The flip-flop 23 is a set-priority RS flip-flop, and the output of the flip-flop 22 and
The clock generation circuit 29 receives the output of the OR gate 27.
Control the behavior of. Then, clock generation circuit 29 receives oscillation output 104 of oscillator 24 and a control signal from flip-flop 23, and outputs clock signals 106 and 107.

The operation of the flip-flop 28 is controlled by an external signal or a signal according to an instruction of a microcomputer. In this embodiment, the output signal of the flip-flop 28 is "1" in advance during the external clock operation. Is set to "0", and is set to "0" during operation by the oscillator using the resonator. In the standby release operation, in the case of the resonator operation, the flip-flop 28
6 is set to "0", and when the count value of the counter 26 reaches a predetermined value, the flip-flop 23 is reset and the oscillation stabilization time is secured, as in the conventional example of FIG. Then, the clock runs and the program is executed. On the other hand, during the external clock operation, the output of the flip-flop 28 is set to "1",
As a result, when the standby is released, the counter 2
External reset signal 10 regardless of the count value of 6
At the same time that 1 is released, the flip-flop 23 is also reset, so that the clock operates and the execution of the program is restarted. Therefore, it is possible to secure a stable time at the time of rising of the oscillator 24 using the resonator, and to eliminate an extra waiting time for stabilizing the oscillation even when receiving an external clock. Therefore, the response is good without waiting for the unnecessary oscillation stabilization time.

[0009]

In the above-described conventional standby control circuit, even in the case of a system in which a microcomputer is operated by the supply of an external clock without using a resonator as a built-in oscillation circuit,
Although a stable clock is obtained from the rising time, it takes time until the counter for ensuring the oscillation stabilization time operates, and the responsiveness at the time of restarting the microcomputer is deteriorated. .

Further, as a method for solving the above drawbacks,
JP-A-4-277809 (Japanese Patent Application No. 3-39650)
However, in this proposal, it is necessary to add an instruction, a terminal, or the like, which has a drawback that the circuit scale and the cost are increased.

Further, since it is necessary to set in advance whether the operation is the resonator operation or the external clock operation, it is inevitable to change the corresponding program for the system change or the like. There is a drawback of lacking in flexibility.

[0012]

A standby control circuit according to a first aspect of the present invention includes an oscillator circuit using a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit, and an oscillation circuit of the oscillator circuit. In a standby control circuit including a clock generation circuit that generates the clock signal based on an output signal, a first control for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside. A first control circuit that outputs a signal and an amplitude level of an oscillation output signal of the oscillation circuit are detected, and a complete clock signal and an incomplete clock signal corresponding to the amplitude level are separately generated. Input the count clock generation circuit that outputs and the complete clock signal and the incomplete clock signal, and use the complete clock signal Performs decrement operation, performs an increment operation by the incomplete clock signal,
A counting circuit that outputs an underflow signal corresponding to a predetermined count value, a first control signal output from the first control circuit, and an underflow signal output from the counting circuit are input. And a second control circuit for controlling initialization of the counting circuit and outputting a second control signal for controlling the operation of the clock generation circuit.

In the first control circuit of the first invention, a control signal and a reset signal supplied from the outside are input to the S terminal and the R terminal, respectively.
The first control signal is formed by a flip-flop output from the Q terminal, and the counting clock generation circuit inputs the oscillation output signal of the oscillation circuit and outputs the complete clock signal; It is formed by an inverter that inputs and inverts and outputs an oscillation output signal of an oscillation circuit, and an EXOR gate that inputs the outputs of these Schmitt trigger inverters and the inverter and outputs the incomplete clock, and The control circuit may be formed by a flip-flop in which the first control signal is input to the S terminal, the underflow signal is input to the R terminal, and the second control signal is output from the Q terminal. .

The standby control circuit of the second invention is based on an oscillation circuit using a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit and an oscillation output signal of the oscillation circuit. A standby control circuit including a clock generation circuit for generating the clock signal, and outputs a first control signal for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside. A first control circuit,
Detecting the amplitude level of the oscillation output signal of the oscillation circuit,
A counting clock generation circuit that separately generates and outputs a complete clock signal and an incomplete clock signal corresponding to the amplitude level, and the complete clock signal and the incomplete clock signal are input, and the complete clock signal is input. A decrementing operation according to the above-mentioned incomplete clock signal and an incrementing operation according to the predetermined count value, and a counting circuit for outputting an underflow signal corresponding to a predetermined count value; and a first control output from the first control circuit. A second control signal for inputting a signal and an underflow signal output from the counting circuit to control initialization of the counting circuit and reset operation of an internal circuit of the semiconductor integrated circuit. A second control circuit for outputting a signal, an inverted signal of the second control signal, and a reset signal supplied from the outside. Enter the door, at least comprising constituted a third control circuit for generating and outputting an internal reset signal, the for the internal circuit.

In the first control circuit of the second invention, a control signal and a reset signal supplied from the outside are input to the S terminal and the R terminal, respectively, and the first control signal is output from the Q terminal. And a counting clock generation circuit for inputting the oscillation output signal of the oscillation circuit to output the complete clock signal, and an oscillation output signal of the oscillation circuit for inversion. And an output of the Schmitt trigger inverter and the inverter, and outputs the incomplete clock.
And an XOR gate, the second control circuit receives the first control signal at the S terminal, the underflow signal at the R terminal, and the second control signal at the Q terminal. And a reset signal supplied from the outside is input to the S terminal of the third control circuit.
An inverted signal of the control signal is input to the R terminal,
It may be formed by a flip-flop whose control signal is output from the Q terminal.

Further, the standby control circuit of the third invention is based on an oscillation circuit using a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit, and an oscillation output signal of the oscillation circuit. A standby control circuit including a clock generation circuit for generating the clock signal, and outputs a first control signal for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside. A first control circuit,
Detecting the amplitude level of the oscillation output signal of the oscillation circuit,
A complete clock signal and an incomplete clock signal corresponding to the amplitude level are separately generated and controlled by a counting clock generation circuit, which is generated and output, and the complete clock signal and the reset signal supplied from the outside,
A second control circuit for outputting a second control signal;
A counting circuit which is controlled by the control signal to switch between incrementing and decrementing and which operates to input the incomplete clock signal to perform a counting operation and which outputs an underflow signal corresponding to a predetermined count value; The first control signal output from the first control circuit and the underflow signal output from the counting circuit are input to control the initialization of the counting circuit and to operate the clock generating circuit. And a third control circuit that outputs a third control signal for controlling.

In the first control circuit of the third invention, a control signal and a reset signal supplied from the outside are input to the S terminal and the R terminal, respectively, and the first control signal is output from the Q terminal. In the second control circuit, the reset signal supplied from the outside is input to the R terminal, the complete clock signal is input to the S terminal, and the second control signal is input to the second control circuit. A Schmitt trigger inverter, which is formed by a flip-flop output from the Q terminal, receives the oscillation output signal of the oscillation circuit and outputs the complete clock signal, and the oscillation output signal of the oscillation circuit. And an inverter that outputs the incomplete clock, and the third control circuit
It may be formed by a flip-flop in which the first control signal is input to the S terminal, the underflow signal is input to the R terminal, and the second control signal is output from the Q terminal.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in this embodiment, the flip-flops 1 and 5, the oscillation circuit 2, the Schmitt trigger inverter 31, the inverter 32, and the EXOR.
A counting clock generation circuit 3 including a gate 33, a counter 4, a clock generation circuit 6, and an OR circuit 7 are provided.

In FIG. 1, the flip-flop 1 is RS
A flip-flop, which is set by a stop signal 102 from a microcomputer, reset by a high-active reset signal 101, and output as a signal 103, which is sent to an oscillator circuit 2 to control the operation of the oscillator circuit. . While the flip-flop 1 is set, the low-level signal 103 is output as its output. The oscillation circuit 2 is oscillated in response to the “0” signal 103 output from the flip-flop 2, the oscillation signal 104 is output from the oscillation circuit 2, and the count clock generation circuit 3 and the clock generation circuit combination 6 are output. Entered in. The counting clock generation circuit 3 is formed by a Schmitt trigger inverter 31, a normal type inverter 32 having no hysteresis characteristic, and a 2-input EXOR gate 33.
When the oscillation signal 104 output from the oscillation circuit 2 is a clock having a sufficient amplitude level, the complete clock signal 105 is output via the Schmitt trigger inverter 31, and the oscillation signal 104 output from the oscillation circuit 2 is not output. In the case of a clock having a sufficient amplitude level, the incomplete clock 106 is output via the EXOR gate 33 which is the output of the Schmitt trigger inverter 31 and the normal inverter 32.

The counter 4 is an up / down counter that decrements by the complete clock 105 output from the count clock generation circuit 3 and increments by the incomplete clock 106, and underflows corresponding to a predetermined count value. A signal (hereinafter referred to as UDF signal) 107 is generated and output. Further, the flip-flop 5 is a set-priority RS flip-flop,
Upon receiving the signal 103 output from the flip-flop 1 and the UDF signal 107 output from the counter 4, a signal 108 is output and input to the clock generation circuit 6 and the OR gate 7. Through the signal 108, the operation of the clock generation circuit 6 is controlled and the reset of the counter 4 is controlled. In the clock generation circuit 6, the clock signal 104 output from the oscillation circuit 2
Is input, and predetermined clock signals 109 and 110 are generated and output based on the clock signal.

2A, 2B, 2C, 2D,
(E), (f), (g) and (h) are timing charts showing the signals of the respective parts when the resonator of the present embodiment is used, and FIGS. 3 (a), (b), (C),
(D), (e), (f), (g) and (h) are timing charts showing the signals of the respective parts when the clock pulse is supplied from the outside of the present embodiment.

Next, with reference to FIGS. 1 and 2, the operation of the resonator of this embodiment will be described. First, at time T ₀ , the power is turned on,
When the reset signal 101 (see FIG. 2A) becomes "1", the flip-flop 1 and the counter 4, the internal circuits in the semiconductor integrated circuit, etc. are initialized. In addition, the signal 108 output from the flip-flop 5 (FIG. 2 (g))
However, there is no problem because the reset signal 101 at power-on is "1" during a time period sufficient for stabilizing the normal oscillation regardless of whether "0" or "1". Here, it is assumed that it is “1” for convenience. Therefore,
Even if the oscillation circuit 2 is in an oscillating state, the clock generation circuit 6
The clock generator circuit 6 is in a stopped state because the signal 108 input to the clock signal "1" is "1". Further, since the signal 103 (see FIG. 2B) output from the flip-flop 1 is “0”, the oscillation circuit 2 starts oscillating, and the oscillation signal 104 output from the oscillation circuit 2 (see FIG. 2 (c)
The amplitude level of (see) gradually increases. Next, at time T ₁ , the reset signal 101 becomes “0”, but since the signal 108 output from the flip-flop 5 is “1”, the clock signals 109 and 110 are output from the clock generation circuit 6. Never. In the counter 4, the reset is released and the counter is started, but since the amplitude of the oscillation signal 104 output from the oscillation circuit 2 is small, the Schmitt trigger inverter 31 is not sensitive to this and the normal inverter 32 Only the clock signal is transmitted, the complete clock signal 105 (see FIG. 2D) is stopped, and only the incomplete clock 106 (see FIG. 2E) operates. In 4, the increment operation is performed.

At time T ₂ , the clock signal 104
When the amplitude level of 1 reaches a predetermined level at which the Schmitt trigger inverter 31 is sensitive, the incomplete clock 105 is stopped and the operation of the complete clock 106 is started. Therefore, in the counter 4, the operation shifts from the increment operation to the decrement operation. Then, at time T ₃ , when the counter 4 underflows and the UDF signal 107 is output, in response to this,
The flip-flop 5 is reset, the clock generation circuit 6 is activated via the signal 108 of “1” output from the flip-flop 5, receives the oscillation signal 104, and receives the clock signal 109 from the clock generation circuit 6.
And 110 are output and sent to the internal circuit in the semiconductor integrated circuit. Then, at time T ₄ , when a stop signal 102 (see FIG. 2 (h)) is input from the outside,
In response to this, the flip-flops 1 and 5 are set together, the oscillation of the oscillation circuit 2 is stopped in response to the signal 103 of "1" output from the flip-flop 1, the counter 4 is initialized, and the flip-flop In response to the signal 108 of "1" output from the circuit 5, the output of the clock signals 109 and 110 from the clock generation circuit 6 is also stopped. Therefore, the power consumption of the semiconductor integrated circuit is extremely small.

Then, the reset signal 101 is set to "1" again.
By this, the oscillation of the oscillation circuit 2 is started via the output 103 of the flip-flop 1, and the OR gate 7
The counter 4 is initialized via. Reset signal 10
By setting 1 to “0”, the counter 4 can perform the increment operation by the incomplete clock 105 output from the count clock generation circuit 3 during the period when the amplitude level of the oscillation signal 104 is insufficient as described above. After the predetermined amplitude level is reached, the decrement operation is performed by the complete clock 106. Further, since the UDF signal 107 is generated and output in the counter 4, the output of the clock signals 109 and 110 from the clock generation circuit 6 is restarted via the output 108 of the flip-flop 5. That is, it becomes possible to secure an oscillation stabilization time according to the time until the amplitude level of the oscillation signal 104 output from the oscillation circuit 3 reaches a predetermined level.

Next, with reference to FIGS. 1 and 3, the operation of the present embodiment when the clock pulse is externally supplied will be described. It should be noted that, here, the description of the points overlapping with the operation of the present embodiment in the case of using the above-described resonator is omitted, and the operation shown in FIG.
Differences from the operations shown in the timing diagrams of (b), (c), (d), (e), (f), (g), and (h) will be described. Since the oscillation signal 104 (see FIG. 3C) output from the oscillation circuit 2 in FIG. 1 is in the state of being supplied with the clock from the outside, the reset signal input to the flip-flop 1 at time T ₀ . When the signal 101 (see FIG. 3 (a)) becomes active, it immediately receives the "0" signal 103 (see FIG. 3 (b)) output from the flip-flop 1 and starts oscillating at a sufficient amplitude level. . Therefore, the clock signal is similarly transmitted from the Schmitt trigger inverter 31 and the normal inverter 32, and the complete clock 105 (see FIG. 3D) is output in the operating state, and the incomplete clock 106 (see FIG. )) Is stopped. Correspondingly, when the counter 4 is released from reset at time T ₁ , the decrement operation is performed and the counter 4
More, one clock later, the UDF signal 107 (see FIG. 3 (f)
Is output and input to the flip-flop 5.
In the flip-flop 5, this UDF signal 107
Is received by the reset terminal and is reset, and its output 108
(See FIG. 3G) is input to the clock generation circuit 6. The clock generation circuit 6 receives the signal 108 of “0” output from the flip-flop 5, and becomes the operating state,
Clock signals 109 and 110 are output in response to the input of the oscillation signal 104 from the oscillation circuit 2, are sent to the internal circuit in the semiconductor integrated circuit, and the operation of the internal circuit is started.

When the stop signal 102 (see FIG. 3 (h)) is input at time T ₄ , both flip-flops 1 and 5 are set, and the signal 103 of "1" output from the flip-flop 1 is thereby set. In response to this, the oscillation of the oscillator circuit 2 is stopped. Also, the counter 3 is initialized through the signal 108 of “1” output through the flip-flop 5, the operation of the clock generation circuit 6 is stopped, and the oscillation signal 104 is input from the oscillation circuit 2. The output of the clock signals 109 and 110 to be activated is also stopped. Therefore, in this state, the power consumption of the semiconductor integrated circuit is extremely small. Then, when the reset signal 101 is set to "1" again, the oscillation circuit 2 starts oscillation and the counter 4 is initialized. When the reset signal 101 is set to “0”, the counter 4 performs the increment operation with the incomplete clock 106 because the amplitude of the clock 104 output from the oscillation circuit 2 is at a sufficient level. Instead, the decrement operation is immediately performed by the complete clock 105. Further, in this case, the UDF signal 107 is generated and output in the counter 4, so that the signal 108 output from the flip-flop 5 becomes "0", whereby the clock generation circuit 6 is brought into an operating state. Then, the transmission of the clock signals 109 and 110 to the internal circuits of the semiconductor integrated circuit is restarted. That is, since the amplitude level of the oscillation signal 104 output from the oscillation circuit 2 has reached the predetermined level from the beginning, the operation of the semiconductor integrated circuit can be started without oscillation stabilization time.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of this embodiment. As shown in FIG. 4, in this embodiment, the flip-flops 1, 5 and 9, the oscillation circuit 2, the count clock generation circuit 3, the counter 4, the clock generation circuit 8 and the O
The R clock 7 and the inverter 10 are provided, and the configuration of the count clock generating circuit 3 is the same as that of the first embodiment shown in FIG. 1, and the Schmitt trigger inverter 31 and the normal type are provided. It is formed by an inverter 32 and an EXOR gate 33. The structural difference between this embodiment and the first embodiment is that a flip-flop 9 and an inverter 10 are newly added.

In FIG. 4, the flip-flop 1 is RS
The signal 103 output from the flip-flop 1 is a flip-flop, which is set by the stop signal 102 from the microcomputer and reset by the high-active reset signal 101.
Then, the operation control for the oscillation circuit 2 is performed.
In this case, the signal 1 output from the flip-flop 1
03 is output as a "0" signal while the flip-flop 1 is reset, and is output as a "1" signal while it is set. In response to this, in the oscillation circuit 2, while the flip-flop 1 is reset (the signal 103 is “0”), the oscillation circuit 104 is in an oscillation state and the oscillation signal 104 is output, and the flip-flop 1 is set (the signal 103 is While it is "1"), a low level signal is output.

The counting clock generation circuit 3 is formed by a Schmitt trigger inverter 31, a normal type inverter 32 having no hysteresis characteristic and a 2-input EXOR gate 33, and the oscillation signal 104 output from the oscillation circuit 2 is sufficient. In the case of a clock having a different amplitude level, the complete clock signal 105 is output via the Schmitt trigger inverter 31, and the oscillation circuit 2
When the output oscillation signal 104 is a clock having an insufficient amplitude level, the Schmitt trigger inverter 31
And the output of the normal type inverter 32 is EXO
It is output as the incomplete clock 106 via the R gate 33.

The counter 4 is an up / down counter that performs a decrement operation by the complete clock 105 output from the count clock generation circuit 3 and an increment operation by the incomplete clock 106, and outputs a UDF signal corresponding to a predetermined count value. 107 is generated and output.
The flip-flop 5 is a set-priority RS flip-flop, and the signal 103 output from the flip-flop 1 and the UDF signal 10 output from the counter 4 are set.
In response to the input of 7, the signal 108 is output and input to the counter 4 via the OR gate 7 and the flip-flop 9 via the inverter 10, and functions as a control for the internal reset signal. Further, in the clock generation circuit 8, the oscillation signal 104 output from the oscillation circuit 2 is input, and predetermined clock signals 109 and 110 are generated and output based on the oscillation signal 104, and the clock signal of the semiconductor integrated circuit is output. It is sent to the internal circuit. The newly added flip-flop 9 is a set-priority RS flip-flop, and receives a signal obtained by inverting the signal 108 output from the flip-flop 5 by the inverter 10 and a reset signal 101, The reset signal 114 is generated, output, and sent to the internal circuit of the semiconductor integrated circuit.

The difference between this embodiment and the above-described first embodiment is that in the first embodiment, the operation of the clock generation circuit 6 is controlled by the signal 108 output from the flip-flop 5. On the other hand, in the clock generation circuit 8 of this embodiment, the immediate clock signal 10 is generated in response to the input of the oscillation signal 104 output from the oscillation circuit 2.
9 and 110 are output, and as long as the oscillation signal 104 is input, the clock signals 109 and 110 are necessarily output from the clock generation circuit 8 to the internal circuit. That's what it means.

Another difference of the present embodiment from the first embodiment is that the reset signal 101 is used as a reset signal for the internal circuit of the semiconductor integrated circuit in the first embodiment.
However, in the present embodiment, the reset signal 114 for the internal circuit of the semiconductor integrated circuit is input to the internal circuit as it is, and the reset signal 114 of the flip-flop 5 set by receiving the input of the reset signal 101. Output 1
That is, the signal output from the flip-flop 9 via the inverted signal of 08 is used as the reset signal 114.

Therefore, in the above-described first embodiment, the clock signal 109 is generated after the oscillation stabilization time is secured.
And 110 are output and the operation of the internal circuit of the semiconductor integrated circuit is started, in contrast to the operation of the oscillator circuit 2, the clock signals 109 and 110 are output from the beginning in the present embodiment. The internal reset signal is released after the oscillation stabilization time has been secured and the operation of the internal circuit of the semiconductor integrated circuit is started. However, the same applies to both the first and second embodiments described above in that the operation of the internal circuit is started after the oscillation stabilization time has elapsed.

Further, even in the case of operating with an external clock without using a resonator, in the case of this embodiment in the state where there is no oscillation stabilization time as in the case of the first embodiment, in the case of this embodiment, It goes without saying that the internal reset signal is released and the operation of the internal circuit of the semiconductor integrated circuit is immediately started.

Next, a third embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of this embodiment. As shown in FIG. 5, in this embodiment, flip-flops 1, 5 and 12, an oscillation circuit 2, a count clock generation circuit 11 including a Schmitt trigger inverter 31 and a normal type inverter 32, and a counter 13.
And a clock generation circuit 6 and an OR gate 7. The structural difference of this embodiment from the first embodiment resides in the configuration contents including the count clock generation circuit 11, the flip-flop 12 and the counter 13.

In FIG. 5, the flip-flop 1 has a set-priority R as in the case of the first and second embodiments.
An S flip-flop, which is set by a stop signal 102 from a microcomputer, reset by a high-active reset signal 101, and a signal 103 output from the flip-flop 1 is sent to an oscillator circuit 2 and an oscillator circuit 2 Is controlled. In this case, the signal 103 output from the flip-flop 1 is output as a “0” signal while the flip-flop 1 is being reset and a “1” signal while being set. At the output point, and in response to this, in the oscillation circuit 2,
Flip-flop 1 is reset (signal 103 is "0")
The oscillation signal 10 is oscillated while the oscillation signal 10
4 is output and the flip-flop 1 is set (signal 10
While the signal 3 is "1"), the low level signal is output as in the case of the first and second embodiments.

The counting clock generation circuit 11 is composed of a Schmitt trigger inverter 31 and a normal type inverter 32 having no hysteresis characteristic, and the oscillation signal 104 output from the oscillation circuit 2 is a clock of a sufficient amplitude level. In this case, the complete clock signal 105 is output via the Schmitt trigger inverter 31, and the oscillation signal 10 output from the oscillation circuit 2 is also output.
Normal inverter 3 regardless of the amplitude level of 4
The incomplete clock 111 is output via 2. The counter 4 is an up / down counter that operates in response to the incomplete clock 111 output from the count clock generation circuit 11 and receives the signal output from the flip-flop 12 to switch between increment and decrement. Yes, U corresponding to the predetermined count value
The DF signal 107 is generated and output. The flip-flop 5 is a set-priority RS flip-flop, and includes the signal 103 output from the flip-flop 1,
Upon receiving the UDF signal 107 output from the counter 4, a signal 108 is output and input to the clock generation circuit 6 and the OR gate 7. The operation of the clock generation circuit 6 is controlled via this signal 108, and OR
The reset of the counter 4 is controlled via the gate 7.
In the clock generation circuit 6, the oscillation signal 104 output from the oscillation circuit 2 is input, and predetermined clock signals 109 and 110 are generated and output based on the oscillation signal.

In the above-mentioned first embodiment, the counter 4 is incremented by the incomplete clock 106 generated when the amplitude level of the oscillation signal 104 output from the oscillation circuit 2 is small, and the amplitude level is sufficient. Counter 4 by the complete clock 105 generated in the case of
Is decremented to detect underflow. In contrast to this, in the present embodiment, the incomplete clock 11 generated regardless of the amplitude level of the oscillation signal 104.
The counter 13 is incremented by using 1 as the counting clock for the counter 13. Then, after that, when the amplitude level of the clock becomes sufficiently large, the counter 13 is started at the rising edge of the complete clock 105 that starts the operation.
The underflow is detected by switching the operation mode in (3) from increment to decrement. Also in the case of the present embodiment, as in the case of the first embodiment, when operating by the supply of the external clock, the complete clock 105 operates immediately, so that the counter 13 must perform the increment operation. Since the decrement operation is started instead, the oscillation stabilization time is deleted.

[0040]

As described above, according to the present invention, when the resonator is used, the stabilization time at the time of rising of the oscillation circuit is secured, and when the operation is performed by the clock supplied from the outside, the oscillation stabilization is achieved. Therefore, it is possible to eliminate unnecessary waiting time for improving the responsiveness.

Further, by recognizing whether the standby circuit itself is an operation using a resonator or an external clock supply, the user does not need to be aware of the clock supply method and the program and system There is an effect that can be built.

Furthermore, in the present invention, the faster the rise, the shorter the stabilization time is automatically set, and the slower the rise, the longer the stabilization time is automatically set. This has the effect of ensuring a stable time adapted to the changing rise time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an operation timing chart at the time of resonator operation in the first embodiment.

FIG. 3 is an operation timing chart during an external clock supply operation in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a block diagram showing another conventional example.

[Explanation of symbols]

1, 5, 9, 12, 14, 18, 22, 23, 28
Flip-flop 2, 19 Oscillation circuit 3, 11 Counting clock generation circuit 4, 13, 17, 26 Counter 6, 8 Clock generation circuit 7, 25, 27 OR gate 10, 16, 21, 32 Inverter 15 NOR gate 20, 31 Schmidt Trigger inverter 24 Oscillator 29 Clock signal generation circuit 33 EXOR gate

Claims (6)

[Claims] 1. An oscillation circuit using a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit, and a clock generation circuit for generating the clock signal based on an oscillation output signal of the oscillation circuit. A standby control circuit including a first control circuit for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside.
A first control circuit for outputting a control signal of, and detecting an amplitude level of an oscillation output signal of the oscillation circuit,
A counting clock generation circuit that separately generates and outputs a complete clock signal and an incomplete clock signal corresponding to the amplitude level, and the complete clock signal and the incomplete clock signal as input, and the complete clock signal A decrementing operation according to the above, an incrementing operation according to the incomplete clock signal, and a counter circuit for outputting an underflow signal corresponding to a predetermined count value; and a first control output from the first control circuit. Signal and
A second control that inputs an underflow signal output from the counting circuit to control initialization of the counting circuit and outputs a second control signal for controlling the operation of the clock generation circuit. A standby control circuit comprising at least a circuit. 2. The first control circuit is configured by a flip-flop in which a control signal and a reset signal supplied from the outside are input to an S terminal and an R terminal, respectively, and the first control signal is output from a Q terminal. A Schmitt trigger inverter that is formed and in which the counting clock generation circuit inputs the oscillation output signal of the oscillation circuit and outputs the complete clock signal; and an inverter that inputs and inverts and outputs the oscillation output signal of the oscillation circuit. And an EXOR gate that inputs the outputs of the Schmitt trigger inverter and the inverter and outputs the incomplete clock, and the second control circuit includes the first control circuit.
2. The standby control circuit according to claim 1, wherein the standby control circuit is formed by a flip-flop in which the control signal is input to the S terminal, the underflow signal is input to the R terminal, and the second control signal is output from the Q terminal. 3. An oscillation circuit that uses a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit, and a clock generation circuit that generates the clock signal based on an oscillation output signal of the oscillation circuit. A standby control circuit including a first control circuit for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside.
A first control circuit for outputting a control signal of, and detecting an amplitude level of an oscillation output signal of the oscillation circuit,
A counting clock generation circuit that separately generates and outputs a complete clock signal and an incomplete clock signal corresponding to the amplitude level, and the complete clock signal and the incomplete clock signal as input, and the complete clock signal A decrementing operation according to the above, an incrementing operation according to the incomplete clock signal, and a counter circuit for outputting an underflow signal corresponding to a predetermined count value; and a first control output from the first control circuit. Signal and
An underflow signal output from the counting circuit is input to control initialization of the counting circuit and output a second control signal for controlling a reset operation of an internal circuit of the semiconductor integrated circuit. A third control circuit that inputs a second control circuit, an inverted signal of the second control signal, and a reset signal supplied from the outside, and generates and outputs an internal reset signal for the internal circuit. And a standby control circuit comprising: 4. The first control circuit is configured by a flip-flop in which a control signal and a reset signal supplied from the outside are input to an S terminal and an R terminal, respectively, and the first control signal is output from a Q terminal. A Schmitt trigger inverter that is formed and in which the counting clock generation circuit inputs the oscillation output signal of the oscillation circuit and outputs the complete clock signal; and an inverter that inputs and inverts and outputs the oscillation output signal of the oscillation circuit. And an EXOR gate that inputs the outputs of the Schmitt trigger inverter and the inverter and outputs the incomplete clock, and the second control circuit includes the first control circuit.
Is input to the S terminal, the underflow signal is input to the R terminal, and the second control signal is formed by a flip-flop output from the Q terminal, and the third control circuit is Formed by a flip-flop in which a reset signal supplied from the outside is input to an S terminal, an inverted signal of the second control signal is input to an R terminal, and the third control signal is output from a Q terminal The standby control circuit according to claim 3, wherein the standby control circuit is provided. 5. An oscillation circuit using a resonator for generating a clock signal supplied to an internal circuit in a semiconductor integrated circuit, and a clock generation circuit for generating the clock signal based on an oscillation output signal of the oscillation circuit. A standby control circuit including a first control circuit for controlling the operation of the oscillation circuit, which is controlled by a control signal and a reset signal supplied from the outside.
A first control circuit for outputting a control signal of, and detecting an amplitude level of an oscillation output signal of the oscillation circuit,
A count clock generation circuit that separately generates and outputs a complete clock signal and an incomplete clock signal corresponding to the amplitude level; and a complete clock signal and a reset signal supplied from the outside, A second control circuit that outputs a control signal of 2; and a second control signal that is controlled by the second control signal to switch between increment and decrement to operate; input the incomplete clock signal to perform a counting operation; A counter circuit that outputs an underflow signal corresponding to a count value; a first control signal that is output from the first control circuit;
A third control for inputting an underflow signal output from the counting circuit to control initialization of the counting circuit and to output a third control signal for controlling operation of the clock generating circuit. A standby control circuit comprising at least a circuit. 6. The first control circuit comprises a flip-flop in which a control signal and a reset signal supplied from the outside are input to S terminals and R terminals, respectively, and the first control signal is output from a Q terminal. In the second control circuit, the reset signal supplied from the outside is input to the R terminal, the complete clock signal is input to the S terminal, and the second control signal is output from the Q terminal. And a Schmitt trigger inverter which is formed by a flip-flop and which inputs the oscillation output signal of the oscillation circuit and outputs the complete clock signal, and the oscillation clock output signal of the oscillation circuit. And an inverter that outputs an incomplete clock, and the third control circuit inputs the first control signal to the S terminal. 6. The standby control circuit according to claim 5, wherein the underflow signal is input to an R terminal and the second control signal is formed by a flip-flop output from a Q terminal.