JPH03133139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with the limit of a wiring length by a method wherein a barrier metal layer, which has patterns covering covering contact parts with a diffused layer and patterns arranged at prescribed intervals, is formed and the barrier metal layer is removed using a wiring layer as a mask. CONSTITUTION:Contact holes are opened in prescribed regions of an oxide film 2 on a semiconductor substrate 1 with a diffused layer formed therein,a plurality of pieces of barrier metal layers 3 the contact holes are filled and which cover contact parts, are formed and at the same time, plurality of pieces of barrier metal layers 4 are formed on the film 2 at prescribed intervals in a striped pattern. Then, Al wirings 5, each having a glare-proof silicon film 6, are formed in a prescribed pattern, the layers 4 are selectively removed using the wirings 5 as masks and at the same time, the films 6 are removed. Here as the layers 4 are formed on the substrate 1 through the film 2, a discharge of a charge is performed from the layers 4 formed into a striped form on the substrate 1 as well. Thereby, restrictions on design to a wiring length, which is caused by a metal eluation at the time of water washing and peeling of a resist, are dissolved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device suitable for manufacturing a semiconductor device having a heat-resistant electrode provided with a barrier metal layer.

[Prior Art] FIGS. 5(a) and 5(b) are plan views showing the conventional method for manufacturing a semiconductor device using this mallet in order of steps, and FIG. 6 is a cross section taken along the line VI-VI in FIG. 5(b). It is a diagram.

First, as shown in FIG. 5(a), an oxide film 18 is formed on a semiconductor substrate 15, and a contact hole is formed in a region of this oxide film 16 where an electrode is to be formed. Then, the surface of the substrate 16 exposed through this contact hole is converted into platinum silicide to form a platinum silicide film. Thereafter, the contact hole is filled with Tlw, and TiW is selectively deposited on the oxide film 16 around the contact hole to form a barrier metal layer 17.

next,! 5 As shown in Figure (b), aluminum wiring 1
8 is patterned. That is, first, the entire surface is coated with an aluminum film by sputtering. Then, silicon is deposited on the aluminum film by sputtering or vapor deposition to form an anti-glare silicon film (not shown). This anti-glare silicon film is formed in order to prevent light from being scattered on the surface of the aluminum film when aluminum wiring in a predetermined pattern is formed by photographic technology in a later process.

Next, using a photographic technique, a photoresist is formed in a predetermined wiring pattern on the anti-glare silicon film, and using this photoresist as a mask, the anti-glare silicon film and the aluminum film are selectively etched by plasma etching or the like. Remove. As a result, the remaining aluminum film becomes the aluminum wiring 18.

After that, the CF4 was washed with water and the photoresist was removed.
By performing plasma etching in an atmosphere such as
The remaining anti-glare silicon film on the aluminum wiring 18 is removed.

Conventionally, the barrier metal layer 17 is formed on the electrode portion on the surface of the semiconductor substrate 15 as described above, and the wiring layer in a predetermined pattern is formed while preventing direct contact between the semiconductor substrate 15 and the aluminum wiring 18. is formed.

[Problems to be Solved by the Invention] However, the above-described conventional semiconductor device manufacturing method has a drawback that aluminum is eluted from the aluminum wiring 18 when washing with water and when removing the photoresist.

FIG. 7 is a schematic cross-sectional view showing the contact portion immediately before washing with water after forming the aluminum wiring 18.

An oxide film 16 in which contact holes are formed is formed on the semiconductor substrate 15 . In this contact hole, a barrier metal layer 17 is formed to fill the contact hole through a platinum silicide film 21 formed on the surface of the semiconductor substrate 15, and an aluminum wiring 18 is formed on this barrier metal layer 17. , anti-glare silicone film 19
A photoresist 20 is formed with a predetermined wiring pattern.

After patterning the anti-glare silicon film 19 and the aluminum wiring 18 by plasma etching, it is necessary to wash the aluminum wiring 18 with water to prevent corrosion of the aluminum wiring 18 due to chlorine-based etching gas. Further, when removing the photoresist 20, the semiconductor substrate 15 is immersed in a solution such as a stripping solution.

By the way, when forming the anti-glare silicon film 19 and the aluminum wiring 18 by plasma etching using the photoresist 20 as a mask, the photoresist 20 is charged with a positive charge, and the aluminum wiring 18 is charged with a negative charge. When the semiconductor substrate 15 is immersed in a solution such as cleaning water or a stripping solution while the photoresist (photoresist) 20 and the aluminum wiring 18 are charged, the difference in ionization tendency between the barrier metal layer 17 and the aluminum wiring 18 causes the aluminum wiring 18 to The negative charge charged on the barrier metal layer 17
into the wash water or solution. At this time, since the aluminum forming the wiring 18 has a higher ionization tendency than the TiW forming the barrier metal layer 17,
Aluminum is ionized (A!3ゝ) from the barrier metal layer 17 and the aluminum wiring 18 in the portion that is in contact with the cleaning water or solution and is eluted into the water or solution.

By the way, the aluminum wiring 18, which has a long wiring length, has a large total amount of charge that is charged during plasma etching. Since charge is released from the barrier metal layer 17 in the contact area, if the wiring length is long, this barrier metal layer 1
The amount of aluminum eluted from the aluminum wiring 18 on the wire 7 increases. Therefore, the aluminum wiring 18
By limiting the wiring length when designing the wiring, elution of aluminum from the aluminum arrangement 1118 can be suppressed. However, although this method is effective in the case of dedicated design of semiconductor devices, it has the disadvantage that automatic design becomes difficult in the case of semiconductor devices such as gate arrays.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device in which metal elution from a wiring layer is suppressed during water washing and resist peeling, and design constraints on wiring length due to metal elution are eliminated.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes a first part that covers a contact portion with a diffusion layer formed on a semiconductor substrate, and a first part that is arranged in stripes at predetermined intervals. The method is characterized by comprising a step of forming a barrier metal layer with a pattern consisting of two parts, a step of forming a wiring layer with a predetermined pattern, and a step of removing the barrier metal layer using the wiring layer as a mask.

[Function] In the present invention, in addition to the first pattern formed on the contact portion, a barrier metal layer is also formed on the second pattern arranged in stripes at predetermined intervals, and then a predetermined pattern is formed on the second pattern. A wiring layer is formed using the pattern. Therefore, the barrier metal layer of the second part pattern formed at predetermined intervals is interposed between the wiring layer and the semiconductor substrate.

Therefore, during water washing and resist removal, the electrical charges that have been accumulated in the wiring layer due to plasma etching, etc. are transferred to the barrier metal layer of the first part pattern of the contact part and the barrier metal layer of the second part pattern below the wiring layer. It is dispersed and released into layers.

As described above, in the present invention, the discharge of charges charged in the wiring layer is not performed concentratedly from the contact hole as in the conventional case, but is performed in a dispersed manner over a wide range. Therefore, metal elution from the wiring layer can be suppressed without limiting the wiring length.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIGS. 1(a) to (C) are plan views showing the method of the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to (C) are the same as those shown in FIGS. IIa-IIa line, nb-n
FIG. 3 is a cross-sectional view taken along line b and line nc-IIa.

First, as shown in FIGS. 1(a) and 2(a), an insulating oxide film having a thickness of, for example, 3,000 yen is deposited on a semiconductor substrate 1 on which a predetermined diffusion layer (not shown) has been formed. form 2. A contact hole is then opened in a predetermined region of this oxide film 2. Next, the surface of the substrate 10 (the surface of the diffusion layer) in the contact hole portion is made into platinum silicide. Thereafter, a plurality of barrier metal layers 3 are formed to fill the contact holes and cover the contact portions, and a plurality of barrier metal layers 4 are formed on the oxide film 2 in a striped pattern at predetermined intervals. This barrier metal layer 3゜4 has T on the entire surface.
After depositing the iW, a resist is formed into stripes using a photographic technique, and then TiW in areas not covered by the resist is selectively removed using, for example, hydrogen peroxide.

Note that the aluminum wiring 5, which will be described later, is usually arranged so as to extend parallel or perpendicular to the side of the semiconductor substrate (IC chip) 1 in plan view.

In this case, it is preferable to form the barrier metal layer 4 in the form of a stripe forming an angle of 45@ with respect to the side of the semiconductor substrate 1, as shown in FIG. 1(a).

Next, as shown in FIG. 1(b) and FIG. 2(b), aluminum wiring 6 is formed in a predetermined pattern. That is,
First, an aluminum film and an anti-glare silicon film 6 are formed on the entire surface by sputtering, and then a photoresist is formed in a predetermined wiring pattern using a photographic technique. Then, using this photoresist as a mask, for example CC. Plasma etching is performed in an atmosphere to remove the aluminum film and anti-glare silicon in the area excluding the area directly under the photoresist.
Remove X6 at the same time. As a result, the remaining aluminum film becomes the aluminum wiring 6.

After that, washing with water and removing the resist are performed.

Next, as shown in FIG. 1(C) and FIG. 2(C),
For example, by plasma etching using CF4, the barrier metal layer 4 is selectively removed using the aluminum wiring 5 as a mask, and the anti-glare silicon film 6 is also removed.

In this embodiment, as described above, when washing with water and removing the photoresist, the striped barrier metal layer 4 is formed on the semiconductor substrate 1 with the oxide film 2 interposed therebetween. Therefore, in the conventional method, discharge of electric charge is performed from the barrier metal layer around the contact hole, but in this embodiment, the discharge of charge is also performed from the barrier metal layer 4 formed in a stripe shape on the substrate 1. In this manner, in this embodiment, the charges on the aluminum wiring 5 are dispersed and discharged into the liquid, so that the elution of aluminum from the aluminum wiring 5 is suppressed.

FIGS. 3(a) to (C) are plan views showing the second embodiment method of the present invention in the order of steps, and FIGS. 4(a) to (c) are the same as those shown in FIGS. IVa -4Va line, IVb-
FIG. 3 is a cross-sectional view taken along the IVb line and the IVc-IVa line.

First, as shown in FIGS. 3(a) and 4(a), the surface of the substrate 1 at the contact hole portion formed in the oxide film 2 on the semiconductor substrate 1 is made into platinum silicide. Then, a plurality of barrier metal layers 3a are formed by filling the contact holes, and a plurality of barrier metal layers 4a are formed on the oxide film 2 in a stripe pattern with predetermined intervals. Unlike the first embodiment, this barrier metal layer 4a is formed in such a shape that it is not connected to the barrier metal layer 3a.

Next, as shown in FIG. 3(b) and FIG. 4(b), the entire surface is coated with an aluminum film and an anti-glare silicone film θ, and the aluminum film and anti-glare silicone film θ are coated using a photographic technique.
is formed into a predetermined wiring pattern to obtain aluminum wiring 5. After that, washing with water and removing the resist are performed.

Next, as shown in FIG. 3(C) and FIG. 4(C),
At the same time as removing the anti-glare silicon film 6, the barrier metal layer 4a in the area not covered by the aluminum wiring 5 is selectively removed.

In this embodiment as well, as in the first embodiment, during water washing and resist removal, charges accumulated in the aluminum wiring 5 are dispersed and discharged in the barrier metal layers 3a and 4a. Thereby, elution of aluminum from the aluminum wiring layer 5 is suppressed.

Further, in this embodiment, the barrier metal layer 4a is not formed around the contact hole, that is, in the area directly above the transistor region. - In the film, various processes are performed on the transistor region of the semiconductor substrate 1, and undulations are formed. For this reason, when the barrier metal layer 4a is removed using the aluminum film 5 as a mask, etching residues are likely to be left on uneven parts. However, in this embodiment, the barrier metal layer 4a is formed on the transistor region.
Since no etching is formed, defects caused by etching residue can be avoided. Therefore, compared to the first embodiment, there is an advantage that the wiring in the transistor region can be further miniaturized.

Note that in the above embodiment, the barrier metal layer is made of Ti.
Although the case where the barrier metal layer is formed of W has been described, the material of the barrier metal layer is not limited to this, and for example, T.
It may also be formed of iN.

Furthermore, the same effect as in the above-described embodiment can be obtained by forming, for example, titanium silicide instead of platinum silicide between the barrier metal layer and the semiconductor substrate.

[Effects of the Invention] As explained above, in the present invention, the first part of the pattern covers the contact part with the diffusion layer of the semiconductor substrate, and the second part of the pattern is arranged in stripes at predetermined intervals. This barrier metal layer is removed using the wiring layer as a mask, so after the wiring layer is formed, the distribution f! Charges in the layer are also released from the barrier metal layer of the second part of the pattern in contact with the wiring layer during the water washing and resist removal steps. That is, in the present invention, charge is discharged from the barrier metal layer of the second pattern, which was conventionally performed from the barrier metal layer of the first pattern that covers the periphery of the contact portion. This suppresses the elution of metal from the wiring layer, which would otherwise occur due to discharge of charges from a concentrated narrow region. Therefore, there is no need to limit the wiring length when designing the wiring of a semiconductor device, and it is possible to automatically design the gate array.

[Brief explanation of the drawing]

Figures 1(a) to (c) are plan views showing the method of the first embodiment of the present invention in the order of steps, and Figures 2(a) to (c) are the same as those shown in Figures 1(a) to (c), respectively. IIa-IIa line, mb-mb
3(a) to (C) are plan views showing the second embodiment method of the present invention in the order of steps, and FIG. 4(a) to (c) are sectional views taken along the IVa-IVa line, IVb-IVb line and IV in Figures 3 (a) to (c)
5(a) and 5(b) are plan views showing the conventional semiconductor device manufacturing method in the order of steps;
The figure is a cross-sectional view taken along the line Vl--Vl in FIG. 5(b), and FIG. 7 is a schematic cross-sectional view showing the contact portion immediately before washing with water in the conventional method. 1.15; Semiconductor substrate, 2.18; Oxide film, 3°3 a
, 4 + 4 a + 17: pariah metal layer, 5, 18; aluminum layer s, e, i9: anti-glare silicon film, 20: photoresist, 21: platinum silicide film

Claims (1)

[Claims] (1) A process of forming a barrier metal layer with a pattern consisting of a first part covering a contact part with a diffusion layer formed on a semiconductor substrate and a second part arranged in a stripe shape at a predetermined interval; 1. A method of manufacturing a semiconductor device, comprising: forming a wiring layer; and removing the barrier metal layer using the wiring layer as a mask.