KR970006934B1 - Forming method of metal pattern - Google Patents
Forming method of metal pattern Download PDFInfo
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- KR970006934B1 KR970006934B1 KR1019940014570A KR19940014570A KR970006934B1 KR 970006934 B1 KR970006934 B1 KR 970006934B1 KR 1019940014570 A KR1019940014570 A KR 1019940014570A KR 19940014570 A KR19940014570 A KR 19940014570A KR 970006934 B1 KR970006934 B1 KR 970006934B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
Description
제1A도 내지 제1F도는 종래 기술의 실시예에 의한 금속패턴 형성공정을 도시한 단면도1A to 1F are cross-sectional views showing a metal pattern forming process according to an embodiment of the prior art.
제2A도 내지 제2C도는 본 발명의 실시예로서 금속패턴 형성공정을 도시한 단면도2A through 2C are cross-sectional views showing a metal pattern forming process as an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1, 21: 반도체기판 3, 23: 산화막1, 21: semiconductor substrate 3, 23: oxide film
5, 25: 식각장벽층 6, 26, 26': 식각장벽층패턴5, 25: etching barrier layer 6, 26, 26 ': etching barrier layer pattern
7, 27: 금속층 8, 28, 28': 금속층패턴7, 27: metal layer 8, 28, 28 ': metal layer pattern
9, 29 반사방지막 10, 30, 30': 반사방지막패턴9, 29 Anti-reflection film 10, 30, 30 ': Anti-reflection film pattern
11: 제2산화막 12: 제2산화막패턴11: second oxide film 12: second oxide film pattern
13, 33:하층감광막 14, 34: 하층감광막패턴13, 33: lower photosensitive film 14, 34: lower photosensitive film pattern
15, 35: 중간층 16, 36: 중간층패턴15, 35: middle layer 16, 36: middle layer pattern
17, 37: 상층감광막패턴 19, 39: 폴리머17, 37: upper photoresist pattern 19, 39: polymer
40: 폴리머패턴40: polymer pattern
본 발명은 금속패턴 형성방법에 관한 것으로, 특히 단층감광막을 이용하여 실시하기 어려울 때 다층감광막을 이용하여 금속층들을 식각하여 미세패턴을 형성하되, 금속층 식각시에 산화막을 사용함으로써 폴리머 형성과 하층감광막의 리프팅 현상을 방지할 수 있는 기술이다.The present invention relates to a method of forming a metal pattern, and in particular, when it is difficult to carry out by using a single layer photoresist film, the metal layer is etched using a multilayer photoresist film to form a fine pattern, and an oxide film is used to etch the metal layer to form a polymer and an underlayer photoresist film. This technology can prevent lifting phenomenon.
반도체소자의 표면이 평단치 못한 부분에 단층감광막을 사용하여 패턴을 형성하는 경우에 일정한 패턴 형성이 어렵기 때문에 하층감광막을 두껍게 도포하여 평탄화시킨 다음, 중간층을 증착하고 그 상부에 상층감광막을 도포한 다음, 마스크 공정으로 감광막패턴을 형성하는 다층감광막공정을 사용하였다.In the case where a pattern is formed using a single layer photoresist film on an uneven surface of the semiconductor device, it is difficult to form a uniform pattern. Therefore, the lower photoresist film is thickened and planarized, and then an intermediate layer is deposited and an upper photoresist film is applied thereon. Next, a multilayer photoresist film process of forming a photoresist film pattern by a mask process was used.
이하, 첨부된 도면을 참고로 하여 종래 기술을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the prior art.
제1A도 내지 제1F도는 종래 기술에 의한 금속미세패턴 형성공정을 도시한 단면도이다.1A to 1F are cross-sectional views showing a metal fine pattern forming process according to the prior art.
제1A도는 반도체기판(21) 상부에 산화막(23), 식각장벽층(25), 금속층(27) 및 반사방지막(29) 을 순차적으로 증착하고 그 상부에 하층감광막(33), 중간층(35) 및 상층감광막을 순차적으로 도포한 다음, 노광 및 현상공정으로 상층감광막패턴(37)을 형성한 것을 도시한 단면도로서, 상기 식각장멱층(25)는 Ti/TiN층으로 형성하고, 상기 금속층(27)은 알루미늄합금으로 형성하고, 상기 반사방지막본 TiN으로 형성하며 상기 중간층(35)은 플라즈마 화학기상증착(PECVD: Plasma Enhanced CVD, 이하에서 PECVD라 함) 기술로 형성한 PECVD산화막으로 형성한 것이다.FIG. 1A sequentially deposits an oxide film 23, an etch barrier layer 25, a metal layer 27, and an antireflection film 29 on the semiconductor substrate 21, and a lower photoresist film 33 and an intermediate layer 35 thereon. And the upper photoresist film is sequentially applied, and then the upper photoresist film pattern 37 is formed by an exposure and development process, wherein the etching layer 25 is formed of a Ti / TiN layer, and the metal layer 27 ) Is formed of an aluminum alloy, the anti-reflection film TiN, and the intermediate layer 35 is formed of a PECVD oxide film formed by a plasma chemical vapor deposition (PECVD) technique.
제1B도는 상기 상층감광막패턴(37)을 마스크로 하여 상기 중간층(35) 및 하층감광막(33)을 순차적으로 식각함으로써 중간층패턴(36)과 하층감광막패턴(34)을 형성한 다음, 상기 상층감광막패턴(37)을 제거한 것을 도시한 단면도로서, 후공정으로 상기 중간층패턴(36)을 습식 또는 건식방법으로 제거하고 상기 하층감광막패턴(34)를 마스크로 하여 하부에 형성된 금속층들(29, 27, 25)를 식각하여 패턴을 형성한다.FIG. 1B illustrates the intermediate layer pattern 36 and the lower layer photoresist pattern 34 by sequentially etching the intermediate layer 35 and the lower layer photoresist layer 33 using the upper photoresist pattern 37 as a mask, and then the upper photoresist layer. A cross-sectional view showing the removal of the pattern 37, wherein the intermediate layer pattern 36 is removed by a wet or dry method in a later step, and the metal layers 29, 27, formed at the lower portion of the lower photoresist pattern 34 as a mask. 25) is etched to form a pattern.
제1C도는 상기 중간층패턴(36)을 건식방법으로 제거한 것을 도시한 단면도로서, 상기 중간층패턴(36)이 식각공정시 발생하는 스퍼터링(sputtering) 현상으로 인하여 상기 하층감광막패턴(34)의 측벽에 폴리머(39)가 형성된 것을 도시한 단면도로서, 상기 폴리머(39)는 거의 제거가 불가능하다.FIG. 1C is a cross-sectional view illustrating the removal of the intermediate layer pattern 36 by a dry method. A polymer is formed on a sidewall of the lower photoresist pattern 34 due to the sputtering phenomenon generated during the etching process of the intermediate layer pattern 36. As a cross-sectional view showing that 39 is formed, the polymer 39 is almost impossible to remove.
제1D도는 상기 제1C도의 공정후에 상기 하층감광막페턴(34)과 측벽에 형성된 폴리머패턴(40)를 마스크로 하여 상기 반사방지막(29), 금속층(27) 및 식각장벽층(25)을 순차적으로 식각함으로써 반사방지막패턴(30), 금속층패턴(28) 및 식각장벽층패턴(25)을 형성하고 상기 하층감광막패턴(34)을 제거한 것을 도시한 단면도로서, 상기 제1C도의 공정후에 상기 폴리머(39) 제거공정을 실시하였으나 완전히 제거되지 않아 폴리머패턴(40)이 형성된 것과, 상기 반사방지막패턴(30), 금속층패턴(28) 및 식각장벽층패턴(25)의 선폭이 예정된 것보다 두껍게 형성된 것을 도시한다.FIG. 1D shows the anti-reflection film 29, the metal layer 27, and the etch barrier layer 25 sequentially using the lower photoresist pattern 34 and the polymer pattern 40 formed on the sidewalls as a mask after the process of FIG. 1C. A cross-sectional view showing that the anti-reflection film pattern 30, the metal layer pattern 28, and the etch barrier layer pattern 25 are removed by etching, and the lower photosensitive film pattern 34 is removed. The polymer 39 after the process shown in FIG. 3) the polymer pattern 40 is formed because the removal process is performed but not completely removed, and the line widths of the anti-reflection film pattern 30, the metal layer pattern 28, and the etch barrier layer pattern 25 are thicker than the predetermined ones. do.
제1E도는 상기 제1C도의 공정후에 습식방법으로 상기 중간층패턴(36)을 제거한 것을 도시한 단면도로서, 상기 하층감광막패턴(34)의 일부가 리프팅되어 일부 소실된 것을 도시한다.FIG. 1E is a cross-sectional view showing that the intermediate layer pattern 36 is removed by a wet method after the process of FIG. 1C, and part of the lower photoresist pattern 34 is lifted and partially lost.
제1F도는 상기 제1E도는 공정후에 담아있는 하층감광막패턴(34)을 마스크로 하여 상기 반사방지막(29), 금속층(27) 및 식각장벽층(25)을 순차적으로 식각함으로써 반사반지막패턴(30'), 금속층패턴(28') 및 식각장벽층패턴(25')을 형성하고 상기 하층감광막패턴(34)을 제거한 것을 도시한 단면도로서, 예정된 금속패턴이 형성되지 않은 것을 도시한다.In FIG. 1F, the anti-reflection film 29, the metal layer 27, and the etch barrier layer 25 are sequentially etched using the lower photoresist pattern 34 contained after the process shown in FIG. 1E as a mask. '), The metal layer pattern 28' and the etch barrier layer pattern 25 'are formed and the lower photoresist pattern 34 is removed, showing that no predetermined metal pattern is formed.
상기한 종래 기술에 의하면, 중간층패턴 건식식각시 하층감광막패턴의 측벽에 형성되는 폴리머 또는 습식식각시 발생되는 하층감광막패턴의 소실로 인하여 예정대로 금속패턴을 형성할 수 없어 반도체소자의 신뢰성 및 수율을 감소기키는 문제점이 발생된다.According to the above-mentioned prior art, due to the loss of the polymer formed on the sidewalls of the lower layer photoresist pattern during the dry etching of the intermediate layer pattern or the lower layer photoresist pattern generated during the wet etching, the metal pattern cannot be formed as expected, thereby improving reliability and yield of the semiconductor device. Reducer keys are a problem.
따라서, 본 발명은 종래 기술의 문제점을 해결하고 예정대로 금속패턴을 형성하기 위하여, 금속층 상부에 얇은 산화막을 증착한 후에 삼층감광막의 중간층을 건식방법으로 제거함으로써 발생되는 폴리머를 방지하고 상기 하층감광막패턴을 마스크하여 금속층들을 식각함으로써 패턴을 형성하는 금속패턴 형성방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention, in order to solve the problems of the prior art and to form a metal pattern as scheduled, to prevent the polymer caused by removing the intermediate layer of the three-layer photosensitive film by a dry method after depositing a thin oxide film on the upper metal layer and the lower layer photosensitive film pattern It is an object of the present invention to provide a metal pattern forming method for forming a pattern by etching the metal layers by masking.
이상의 목적을 달성하기 위한 본 발명의 특징은, 반도체기판 상부에 산화막, 식각장벽층, 금속층, 반사방지막 및 제2산화막을 순차적으로 증착하고 그 상부에 하층감광막, 중간층 및 상층감광막을 도포한 다음, 노광및 현상공정으로 상층감광막패턴을 형성하는 공정과, 상기 상층감광막패턴을 마스크로 하여 상기 중간층과 하층감광막을 식각함으로써 중간층패턴과 하층감광막패턴을 형성하고 상기 상층감광막패턴을 제거하는 공정과, 상기 중간층패턴을 건식방법으로 식각하여 제거하는 동시에 상기 제2산화막을 식각하여 제2산화막패턴을 형성하는 공정과, 상기 제거공정시 상기 하층감광막패턴의 측벽에 형성된 약간의 폴리머를 습식방법으로 제거한 다음, 상기 하층감광막패턴을 마스크하여 상기 반사방지막, 금속층 및 식각장벽층을 순차적으로 식각하고 상기 하층감광막패턴을 제거함으로써 제2산화막패턴, 반사방지막패턴, 금속층패턴 및 식각장벽층패턴 등으로 형성된 금속패턴을 형성하는 공정을 포함하는데 있다.A feature of the present invention for achieving the above object is to sequentially deposit an oxide film, an etch barrier layer, a metal layer, an antireflection film and a second oxide film on top of a semiconductor substrate, and then apply a lower photoresist film, an intermediate layer and an upper photoresist film thereon, Forming an upper photoresist pattern by an exposure and development process, forming an intermediate layer pattern and a lower photoresist pattern by etching the intermediate layer and the lower photoresist layer using the upper photoresist pattern as a mask, and removing the upper photoresist pattern; Etching and removing the intermediate layer pattern by a dry method, and simultaneously etching the second oxide layer to form a second oxide layer pattern; and removing a small amount of polymer formed on the sidewall of the lower photoresist pattern during the removal process by a wet method. The anti-reflection film, the metal layer and the etching barrier layer are sequentially masked by masking the lower photoresist pattern And forming a metal pattern formed of a second oxide film pattern, an anti-reflection film pattern, a metal layer pattern, and an etch barrier layer pattern by etching and removing the lower photoresist pattern.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2A도 내지 제2C도는 본 발명의 실시예에 의한 반도체소자의 금속패턴 형성공정을 도시한 단면도이다.2A to 2C are cross-sectional views showing a metal pattern forming process of a semiconductor device according to an embodiment of the present invention.
제2A도는 반도체기판(1) 상부에 산화막(3), 식각장벽층(5), 금속층(7), 반사방지막(9) 및 제2산화막(11) 을 순차적으로 증착하고 그 상부에 하층감광막(13), 중간층(15) 및 상층감광막을 순차적으로 도포한 다음, 노광 및 현상공정으로 상층감광막패턴(17)을 형상한 것을 도시한 단면도로서, 상기 식각장벽층(5)은 TiN으로 형성하고, 상기 금속층(7)은 알루미늄금속으로 형성하고, 상기 반사방지막(9)을 Ti/TiN으로 형성하며 상기 제2산화막(11)과 중간층(15)은 PECVD 산화막으로 형성하되, 상기 제2산화막(11)은 500Å 이하의 두께로 형성하고 상기 중간층(15)은 1000Å 이하의 두께로 형성한 것을 도시한다.FIG. 2A sequentially deposits an oxide film 3, an etch barrier layer 5, a metal layer 7, an antireflection film 9 and a second oxide film 11 on the semiconductor substrate 1, and a lower photoresist film thereon. 13), a cross-sectional view showing that the intermediate layer 15 and the upper photoresist film were sequentially applied, and then the upper photoresist pattern 17 was formed by an exposure and development process, wherein the etch barrier layer 5 was formed of TiN, The metal layer 7 is formed of aluminum metal, the anti-reflection film 9 is formed of Ti / TiN, and the second oxide film 11 and the intermediate layer 15 are formed of PECVD oxide film, but the second oxide film 11 ) Is formed to a thickness of 500 kPa or less, and the intermediate layer 15 is formed to a thickness of 1000 kPa or less.
제2B도는 상기 상층감광막패턴(17)을 마스크로 하여 상기 중간층(15)과 하층감광막(13)을 순차적으로 식각함으로써 중간층패턴(도시안됨)과 하층감광막패턴(14)을 형성하고 상기 중간층패턴을 건식식각하여 제거하는 동시에 상기 제2산화막(11)을 식각하여 제2산화막패턴(12)을 형성하고 상기 하층감광막패턴(14)의 측벽에 약간의 폴리머(19) 가 형성된 것을 도시한 단면도로서, 상기 폴리머(19)는 현상액으로 쉽게 제거할 수 있다. 여기서, 상기 중간층패턴 제거공정시 습식식각을 사용하면 상기 하층감광막패턴(14)이 리프팅되어 습식방법은 사용할 수 없다.2B shows an intermediate layer pattern (not shown) and an underlayer photoresist pattern 14 by sequentially etching the intermediate layer 15 and the lower photoresist layer 13 using the upper photoresist pattern 17 as a mask. A cross-sectional view showing that the second oxide film 11 is etched to form a second oxide film pattern 12 while being dry etched and removed, and some polymer 19 is formed on the sidewall of the lower photoresist pattern 14. The polymer 19 can be easily removed with a developer. In this case, when wet etching is used in the process of removing the intermediate layer pattern, the lower photoresist layer pattern 14 is lifted and a wet method cannot be used.
제2C도는 제2B도의 공정후에 현상으로 상기 폴리머(19)를 제거한 다음, 상기 하층감광막패턴(14)을 마스크로 하여 상기 반사방지막(9), 금속층(7) 및 식각장벽층(5)을 순차적으로 식각하고 상기 하층감광막패턴(14)을 제거함으로써 제2산화막패턴(12), 반사방지막패턴(10), 금속층패턴(8) 및 식각장벽층패턴(6) 등으로 형성된 금속패턴을 형성한 것을 도시한 단면도이다.2C shows that the polymer 19 is removed after development in FIG. 2B, and then the anti-reflection film 9, the metal layer 7, and the etch barrier layer 5 are sequentially formed using the lower photoresist pattern 14 as a mask. To form a metal pattern formed of the second oxide film pattern 12, the anti-reflection film pattern 10, the metal layer pattern 8 and the etching barrier layer pattern 6 by removing the lower photoresist pattern 14 It is sectional drawing.
상기한 본 발명에 의하면, 금속층들의 상부에 얇은 산화막을 증착하고 상층감광막을 이용한 금속패턴 형성함으로써 종래 기술에서 발생되었던 폴리머의 생성 및 하층감광막패턴의 리프팅 등의 문제점을 해결하여 예정대로 패턴을 형성하여 반도체소자의 신뢰성 및 수율을 향상시킨다.According to the present invention, by depositing a thin oxide film on top of the metal layers and forming a metal pattern using the upper photosensitive film to solve the problems such as the generation of the polymer generated in the prior art and the lifting of the lower photosensitive film pattern to form a pattern as scheduled Improve the reliability and yield of semiconductor devices.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940014570A KR970006934B1 (en) | 1994-06-24 | 1994-06-24 | Forming method of metal pattern |
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| KR1019940014570A KR970006934B1 (en) | 1994-06-24 | 1994-06-24 | Forming method of metal pattern |
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| KR960002675A KR960002675A (en) | 1996-01-26 |
| KR970006934B1 true KR970006934B1 (en) | 1997-04-30 |
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| KR1019940014570A KR970006934B1 (en) | 1994-06-24 | 1994-06-24 | Forming method of metal pattern |
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