CN117832078A - Passivation layer etching method, structure and application for avoiding arc discharge at edge of wafer - Google Patents
Passivation layer etching method, structure and application for avoiding arc discharge at edge of wafer Download PDFInfo
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- CN117832078A CN117832078A CN202311835020.6A CN202311835020A CN117832078A CN 117832078 A CN117832078 A CN 117832078A CN 202311835020 A CN202311835020 A CN 202311835020A CN 117832078 A CN117832078 A CN 117832078A
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- 238000002161 passivation Methods 0.000 title claims abstract description 114
- 238000005530 etching Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000010891 electric arc Methods 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 13
- 229910052721 tungsten Inorganic materials 0.000 description 13
- 239000010937 tungsten Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Abstract
The invention discloses a passivation layer etching method, a passivation layer etching structure and application for avoiding arc discharge at the edge of a wafer. The passivation layer etching method comprises the following steps: providing a wafer, wherein the wafer comprises a substrate and a chip layer, the surface of the chip layer is covered with a passivation layer, and the edge of the substrate protrudes out of the edge of the chip layer; covering the surface of the passivation layer with a negative photoresist layer, wherein the negative photoresist layer also covers the side wall of the edge; carrying out patterned exposure on the chip area, wherein the unexposed part of the negative photoresist layer can be removed by development; performing edge exposure on the edge area; developing the negative photoresist layer subjected to the patterning exposure and the edge exposure to form a patterning opening; and carrying out plasma etching on the passivation layer by using the patterned opening. The invention protects the conductive structure of the wafer edge part which is not well electrically connected by utilizing the photoresist layer and the passivation layer at the edge, and prevents the occurrence of edge arc discharge, thereby remarkably improving the yield of the wafer passivation layer during etching and having excellent application prospect.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, in particular to a passivation layer etching method, a passivation layer etching structure and application for avoiding arc discharge at the edge of a wafer.
Background
In the manufacturing process of semiconductor integrated circuits, passivation layers (Passivation) are used as protection structures for integrated circuit devices and metal wires, on the one hand, to provide a certain stress buffer, so that the devices are not damaged by subsequent cutting, cleaning, packaging and other processes, and on the other hand, to protect products from moisture, contamination and to protect internal structures from corrosion.
The dielectric materials used for the passivation layer are typically silicon oxide and silicon nitride, and the structure is typically one or more layers of SiO deposited first 2 Finally deposit a layer of compact Si 3 N 4 . The back-end Passivation layer etching process is mainly used for opening a Passivation layer to form a PAD (PAD), and usually adopts plasma to Etch the Passivation layer, and due to the specific high radio frequency Power (RF Power), the Passivation layer is the process with the highest occurrence frequency of arc discharge of a Wafer, which is one of the main common problems faced by the current integrated circuit Passivation layer etching (passage etching) process, and an arc discharge area is usually a Wafer Mark, a Scribe Line, a Seal Ring, a Wafer edge and other areas.
Arcing in the wafer edge region is mainly two conditions:
1. unhealthy edge wash conditions: as shown in fig. 1, when the metal layer edge is less than the CT layer or the VIA layer edge, the VIA layer tungsten plug in the edge area is in a floating state. In the passivation layer etching step, when the edge of the wafer is windowed, a large amount of charges can be accumulated near the tungsten plugs, and the accumulated charges cannot be timely led out through the metal wires because the tungsten plugs are in a floating state. When the charge reaches a certain energy, arc discharge occurs to damage the wafer;
2. edge misalignment: as shown in fig. 2, the topography is worst near the wafer edge, and the high and low fluctuations are severe, which may cause misalignment between the metal and VIA layers. This also causes tungsten plugs in a floating state, causing arcing, damaging the wafer.
Therefore, in the current chip manufacturing process, arc discharge is easily generated at the edge of the wafer in the passivation layer etching step, so that the yield of the wafer is lost. Particularly, for some products with more tightly controlled quality, as long as arc discharge occurs on the wafer, the whole wafer needs to be scrapped no matter how much damage is caused to the wafer, and huge cost loss is caused.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a passivation layer etching method, a passivation layer etching structure and application for avoiding arc discharge at the edge of a wafer.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
in a first aspect, the present invention provides a passivation layer etching method for avoiding arc discharge at a wafer edge, comprising:
providing a wafer, wherein the wafer comprises a substrate and a chip layer formed on the surface of the substrate, the surface of the chip layer is covered with a passivation layer, and the edge of the substrate protrudes out of the edge of the chip layer;
covering a negative photoresist layer on the surface of the passivation layer, wherein the negative photoresist layer also covers the passivation layer and the side wall of the edge of the chip layer;
carrying out patterned exposure on a chip area positioned in the middle of the wafer so that the unexposed part of the negative photoresist layer can be removed by development;
performing edge exposure on an edge area positioned at the edge of the wafer;
developing the negative photoresist layer subjected to the patterning exposure and the edge exposure to form a patterning opening;
and carrying out plasma etching on the passivation layer by utilizing the patterned opening.
In a second aspect, the invention further provides an application of the passivation layer etching method in preparing a semiconductor device.
In a third aspect, the present invention further provides a passivation layer etching structure, where the passivation layer etching structure is formed on a wafer, the wafer includes a chip area located in the middle of the wafer and an edge area located at the edge of the wafer, and a passivation layer is covered on the surface of the wafer; and the passivation layer in the chip area is etched to form a passivation opening penetrating through the passivation layer, the passivation layer in the edge area is a continuous passivation layer, and the passivation opening is not formed.
Based on the technical scheme, compared with the prior art, the invention has the beneficial effects that:
the invention protects the conductive structure of the wafer edge part which is not well electrically connected by utilizing the photoresist layer and the passivation layer at the edge, and prevents the occurrence of edge arc discharge, thereby remarkably improving the yield of the wafer passivation layer during etching and having excellent application prospect.
The above description is only an overview of the technical solutions of the present invention, and in order to enable those skilled in the art to more clearly understand the technical means of the present application, the present invention may be implemented according to the content of the specification, the following description is given of the preferred embodiments of the present invention with reference to the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of a wafer edge arcing scenario provided in the background of the invention;
FIG. 2 is a schematic diagram of another example of arc discharge at the edge of a wafer according to the background of the invention;
FIG. 3 is a schematic cross-sectional view of a passivation structure formed by a passivation layer etching method according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a front structure of a passivation structure formed by a passivation layer etching method according to an exemplary embodiment of the present invention;
FIG. 5a is a schematic diagram of a wafer exposure process according to an exemplary embodiment of the present invention and a comparative example;
FIG. 5b is a schematic diagram of another wafer exposure process according to an exemplary embodiment of the present invention and a comparative example.
Reference numerals illustrate:
1. a substrate; 2. a first vertical structure; 3. a first dielectric layer; 4. a first horizontal interconnect sublayer; 5. a second vertical structure; 6. a second dielectric layer; 7. a second horizontal interconnect sublayer; 8. a passivation layer; 9. the openings are passivated.
Detailed Description
In the current chip manufacturing process, arc discharge is easily generated at the edge of a wafer in the passivation layer etching step, so that the yield of the wafer is lost. For some products with more tightly controlled quality, as long as arc discharge occurs on the wafer, the whole wafer needs to be scrapped no matter how much the wafer is damaged, and great cost loss is caused. In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below.
Moreover, relational terms such as "first" and "second", and the like, may be used solely to distinguish one from another component or method step having the same name, without necessarily requiring or implying any actual such relationship or order between such components or method steps.
As shown in fig. 3 and 4, an embodiment of the present invention provides a passivation layer etching method for avoiding arc discharge at a wafer edge, which includes the following steps:
providing a wafer, wherein the wafer comprises a substrate 1 and a chip layer formed on the surface of the substrate 1, the surface of the chip layer is covered with a passivation layer 8, and the edge of the substrate 1 protrudes out of the edge of the chip layer;
covering the surface of the passivation layer 8 with a negative photoresist layer, wherein the negative photoresist layer also covers the passivation layer 8 and the side wall of the chip layer edge;
carrying out patterned exposure on a chip area positioned in the middle of the wafer so that the unexposed part of the negative photoresist layer can be removed by development;
performing edge exposure on an edge area positioned at the edge of the wafer;
developing the negative photoresist layer subjected to the patterning exposure and the edge exposure to form a patterning opening;
and carrying out plasma etching on the passivation layer 8 by utilizing the patterned opening.
With respect to a specific process, in some embodiments, the negative photoresist layer in the edge region is preserved as the developing is performed; the passivation layer 8 at the edge region is not in contact with the plasma when the plasma etching is performed.
Some prior art also provides some technical schemes for protecting the wafer edge from arcing by using photoresist, and the specific adopted process route is that a positive photoresist layer is used, and the device area is exposed, but the edge area is not exposed, so that the specific technical route of forming the annular structure covered by the photoresist at the edge is different from the process route of the patent and cannot be realized at all.
The specific reasons are as follows: as shown in fig. 5a and 5b, the patterning lithography may be performed sequentially using a mask (mask) as a barrier, with full exposure as shown in fig. 5a, and edge non-exposure as shown in fig. 5 b. If the prior art adopts positive photoresist, the photoresist can be retained only by adopting the mode that the edge shown in fig. 5b is not exposed, so that an annular structure with better appearance cannot be formed due to the zigzag inscribed shape, and a large amount of wafer area is wasted due to space occupation, especially the chip particles at the corner position cannot be utilized, and the chip production cost is obviously increased.
In contrast, the present patent adopts the negative photoresist for protection, and after the etching method is adopted, the mercury lamp of the developing machine is used for exposing the edge (WEE), so that the retention of the edge photoresist can be completely realized, and the required effect is realized.
With respect to specific implementation details, in some embodiments, with continued reference to fig. 3, the chip layer includes a vertical interconnect structure and a horizontal interconnect sub-layer, and a portion of the vertical interconnect structure in the edge region is in a state of not being connected to the corresponding horizontal interconnect sub-layer.
More specifically, in some embodiments, the chip layer includes, in order, a semiconductor layer, a first dielectric layer 3, a first horizontal interconnect sublayer 4, a second dielectric layer 6, and a second horizontal interconnect sublayer 7, in a direction away from the substrate 1; the second horizontal interconnect sublayer 7 is in contact with the passivation layer 8; the vertical interconnect comprises a first vertical structure 2 arranged in the first dielectric layer 3 and a second vertical structure 5 arranged in the second horizontal interconnect sublayer 7.
In some embodiments, the main cause of the edge arcing described above is generally: the portion of the second vertical structure 5 at the edge region is not connected to the second horizontal interconnect sublayer 7. Taking as an example a tungsten plug as the first or second vertical structure 5, it is generally known in the art that a tungsten plug in such a state is not connected to the second horizontal interconnect sublayer 7 is referred to as a floating state.
While the typical wafer process further includes an edge removal process step, for example, in some embodiments, the passivation layer 8 etching method may further include the following steps:
after the negative photoresist layer is covered, edge photoresist removal treatment is performed on the wafer so that the substrate 1 protrudes from the edge of the photoresist layer.
With respect to specific dimensional parameters, in some embodiments, the width of the edge photoresist removal process is from 0 to 1mm.
In some embodiments, the edge exposure has a width of 3mm or more.
With respect to the passivation layer 8, in some embodiments, the passivation layer 8 is prepared by chemical vapor deposition.
As some typical application examples of the above technical solutions, the technical solutions provided by the present invention utilize a photolithography edge-washing process to fully retain a circle of passivation layer 8 at the edge of a wafer, so as to avoid the direct exposure of a vertical interconnection structure in the etching step of the passivation layer 8, and effectively prevent the occurrence of arc discharge at the edge of the wafer, where the specific process adopted may be as follows:
s1, providing a substrate 1, forming a first dielectric layer 3 and a tungsten plug (a first vertical structure 2) in the first dielectric layer to form a CT layer, forming a first metal interconnection layer as a first horizontal interconnection sublayer 4, forming a second dielectric layer 6 and a tungsten plug (a second vertical structure 5) in the second dielectric layer to form a VIA layer on the substrate 1, and forming a top metal interconnection layer as a second horizontal interconnection layer.
S2, depositing a Passivation layer 8 (Passivation) by using a Chemical Vapor Deposition (CVD) mode.
S3, spin-coating a layer of photoresist through a photoresist coater table, wherein the photoresist is negative photoresist.
S4, after the photoresist spin coating is finished, removing residual photoresist at the most edge of the wafer and residual photoresist at the back of the wafer through an EBR (Edge Bead Removal, edge photoresist removal) step, wherein the EBR is set to be 0-1mm in width.
S5, completing the exposure process through a photoetching machine. Since the photoresist is a negative photoresist, the unexposed areas will undergo a photoacid reaction.
S6, the wafer is sent to WEE (Wafer Edge Exposure ) step, and the edge of the wafer is exposed by a mercury lamp of a developing machine, wherein the exposure width is larger than 3mm.
S7, the wafer passes through a developing machine to complete the developing step of the photoresist. After development, the photoresist will remain in the areas exposed by the lithography machine and the WEE, and the unexposed areas will be fully opened. Thus, the edge area of the wafer is exposed to WEE, so that photoresist is left on the edge of the wafer.
S8, through the etching step of the passivation layer 8, the passivation layer 8 without photoresist protection is etched, and a passivation opening 9 is obtained. The passivation layer 8 at the edge of the wafer is protected by photoresist, so that etching can not occur and all the passivation layer can be reserved, and therefore the tungsten plug in a floating state is protected from accumulating charges and arc discharge is prevented.
Correspondingly, the second aspect of the embodiment of the invention also provides an application of the passivation layer 8 etching method provided by any one of the embodiments in preparing a semiconductor device.
As a specific example of the above application, with continued reference to fig. 3, a third aspect of the embodiment of the present invention provides a passivation layer etching structure, which is preferably manufactured by using the passivation layer etching method provided in any one of the foregoing embodiments, where the passivation layer etching structure is formed on a wafer, and the wafer includes a chip area located in a middle of the wafer and an edge area located at an edge of the wafer, and a passivation layer 8 is covered on a surface of the wafer; the passivation layer in the chip region is etched to form a passivation opening 9 penetrating through the passivation layer 8, the passivation layer 8 in the edge region is a continuous passivation layer, and the passivation opening 9 is not formed.
In some embodiments, the passivation layer is formed on a surface of a chip layer, and the chip layer includes a vertical interconnection structure and a horizontal interconnection sub-layer, and a portion of the vertical interconnection structure in the edge region is in a state of not being connected to the corresponding horizontal interconnection sub-layer.
The technical scheme of the invention is further described in detail below through a plurality of embodiments and with reference to the accompanying drawings. However, the examples are chosen to illustrate the invention only and are not intended to limit the scope of the invention.
Example 1
The present embodiment illustrates a method for etching the passivation layer 8 of a wafer, which is specifically as follows:
s1, preparing a wafer, after a chip area is formed on a substrate 1, forming a first dielectric layer 3 and a tungsten plug (a first vertical structure 2) in the first dielectric layer on the surface of the wafer to form a CT layer, forming a first metal interconnection layer as a first horizontal interconnection sublayer 4, forming a second dielectric layer 6 and a tungsten plug (a second vertical structure 5) in the second dielectric layer to form a VIA layer, and forming a top metal interconnection layer as a second horizontal interconnection layer.
S2, depositing a Passivation layer 8 (Passivation) by using a Chemical Vapor Deposition (CVD) mode.
S3, spin-coating a layer of photoresist through a photoresist coater table, wherein the photoresist is negative photoresist.
And S4, after the photoresist spin coating is finished, removing the residual photoresist at the most edge of the wafer and the residual photoresist at the back of the wafer through an EBR (Edge Bead Removal, edge photoresist removal) step, wherein the EBR is set to be 1mm.
S5, completing the exposure process through a photoetching machine. Since the photoresist is a negative photoresist, the unexposed areas will undergo a photoacid reaction.
S6, the wafer is sent to WEE (Wafer Edge Exposure ) step, and the edge of the wafer is exposed by a mercury lamp of a developing machine, wherein the exposure width is 4mm.
S7, the wafer passes through a developing machine to complete the developing step of the photoresist. After development, the photoresist will remain in the areas exposed by the lithography machine and the WEE, and the unexposed areas will be fully opened, forming photoresist openings. Thus, the edge area of the wafer is exposed to WEE, so that photoresist is left on the edge of the wafer.
S8, through the etching step of the passivation layer 8, the passivation layer 8 without photoresist protection is etched, and a passivation opening 9 is obtained. The passivation layer 8 at the edge of the wafer is protected by photoresist, so that etching can not occur and all the passivation layer can be reserved, and therefore the tungsten plug in a floating state is protected from accumulating charges and arc discharge is prevented.
Example 2
This embodiment is substantially the same as embodiment 1, except that:
in step S4, the EBR setting width is 0.5mm; in step S6, the WEE exposure width was 3mm.
The technical effect of preventing arcing during etching of the passivation layer 8 in step S8 can also be achieved.
Example 3
This embodiment is substantially the same as embodiment 1, except that:
in step S4, the EBR is set to 0, i.e. no edge removal is performed; in step S6, the WEE exposure width was 3mm.
The technical effect of preventing arcing during etching of the passivation layer 8 in step S8 can also be achieved.
Based on the above embodiment, it can be clear that, by adjusting the lithography edge-washing process, the method provided by the embodiment of the invention can fully retain a circle of passivation layer 8 at the edge of the wafer, thereby avoiding the tungsten plug in the floating state from being directly exposed in the etching step of the passivation layer 8, effectively preventing the occurrence of arc discharge at the edge of the wafer, and improving the yield of the wafer process.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. A passivation layer etching method for avoiding arc discharge at the edge of a wafer is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises a substrate and a chip layer formed on the surface of the substrate, the surface of the chip layer is covered with a passivation layer, and the edge of the substrate protrudes out of the edge of the chip layer;
covering a negative photoresist layer on the surface of the passivation layer, wherein the negative photoresist layer also covers the passivation layer and the side wall of the edge of the chip layer;
carrying out patterned exposure on a chip area positioned in the middle of the wafer so that the unexposed part of the negative photoresist layer can be removed by development;
performing edge exposure on an edge area positioned at the edge of the wafer;
developing the negative photoresist layer subjected to the patterning exposure and the edge exposure to form a patterning opening;
and carrying out plasma etching on the passivation layer by utilizing the patterned opening.
2. The passivation layer etching method according to claim 1, wherein a negative photoresist layer in the edge region is left when the developing is performed; the passivation layer at the edge region is not in contact with the plasma while the plasma etching is performed.
3. The passivation layer etching method according to claim 1, wherein the chip layer includes a vertical interconnection structure and a horizontal interconnection sub-layer, and a portion of the vertical interconnection structure in the edge region is in a state of not being connected to the corresponding horizontal interconnection sub-layer.
4. The passivation layer etching method according to claim 3, wherein the chip layer sequentially comprises a semiconductor layer, a first dielectric layer, a first horizontal interconnection sub-layer, a second dielectric layer and a second horizontal interconnection sub-layer along a direction away from the substrate;
the second horizontal interconnection sub-layer is in contact with the passivation layer;
the vertical interconnection structure comprises a first vertical structure arranged in the first dielectric layer and a second vertical structure arranged in the second horizontal interconnection sublayer.
5. The method of claim 4, wherein a portion of the second vertical structure at the edge region is not connected to the second horizontal interconnect sub-layer.
6. The passivation layer etching method according to claim 1, further comprising:
and after the negative photoresist layer is covered, performing edge photoresist removal treatment on the wafer so that the substrate protrudes out of the edge of the photoresist layer.
Preferably, the width of the edge photoresist removing treatment is 0-1mm;
preferably, the width of the edge exposure is more than 3mm.
7. The method of claim 1, wherein the passivation layer is prepared by chemical vapor deposition.
8. Use of a passivation layer etching method according to any of claims 1 to 7 for the manufacture of a semiconductor device.
9. The passivation layer etching structure is characterized in that the passivation layer etching structure is formed on a wafer, the wafer comprises a chip area positioned in the middle of the wafer and an edge area positioned at the edge of the wafer, and a passivation layer is coated on the surface of the wafer;
and the passivation layer in the chip area is etched to form a passivation opening penetrating through the passivation layer, the passivation layer in the edge area is a continuous passivation layer, and the passivation opening is not formed.
10. The passivation layer etching structure according to claim 9, wherein the passivation layer is formed on a surface of a chip layer, the chip layer includes a vertical interconnection structure and a horizontal interconnection sub-layer, and a portion of the vertical interconnection structure in the edge region is in a state of not being connected to the corresponding horizontal interconnection sub-layer.
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| CN202311835020.6A CN117832078A (en) | 2023-12-28 | 2023-12-28 | Passivation layer etching method, structure and application for avoiding arc discharge at edge of wafer |
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| CN202311835020.6A CN117832078A (en) | 2023-12-28 | 2023-12-28 | Passivation layer etching method, structure and application for avoiding arc discharge at edge of wafer |
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